Increase In Interface State Density Research Articles

Study of gamma-ray radiation effects on the passivation properties of atomic layer deposited Al2O3 on silicon using deep-level transient spectroscopy

Aluminum oxide (Al2O3) has emerged as a potential dielectric material and exhibited an excellent passivation property on silicon surface. However, such oxide layer is extremely sensitive to γ-ray irradiation. In this work, deep-level transient spectroscopy has been applied to study the influence of γ-ray irradiation on the passivation properties of atomic layer deposited Al2O3 on silicon. It is shown that γ-ray irradiation leads to a significant increase of interface state density (Dit). Meanwhile, its energy distribution is broadened and shifts deeper with respect to the top of valence band, and therefore evolves into more efficient recombination centers for carriers. Besides, capacitance–voltage (C–V) curves shows a progressive shift toward the negative voltages with increased radiation doses. This indicates the hole trapping in Al2O3, which can neutralize the negatively charged defects and therefore degrade its field-effect passivation. Hence, the passivation quality of Al2O3 on silicon deteriorates significantly after γ-ray radiation.

Identification of swift heavy ion induced defects in Pt/n-GaN Schottky diodes by in-situ deep level transient spectroscopy

In-situ measurements such as deep level transient spectroscopy (DLTS) provide reliable information for the identification of defects in electronic devices. For GaN-based devices exposed to swift heavy ion (SHI) irradiation, in situ DLTS investigations are not reported. The defect characterization of irradiated devices has significant relevance in the reliability testing of devices for space applications, detectors for high energy physics experiments, nuclear radiation environments near reactors and for device engineers to design better and high-performance electronic components. The present work reports on the identification of defects by employing in situ DLTS in Pt/n-GaN Schottky devices before and after SHI irradiation by 200 MeV 107Ag14+ ions at various fluences in the range of 1 × 1010 to 1 × 1011 ions cm−2. For pristine or un-irradiated diodes, trap levels at 0.173, 0.504, 0.283 and 1.012 eV below the conduction edge are observed which are reported as growth-related defects in GaN. The ion beam introduces more electron and hole traps in the bandgap. A significant increase in interface state density was instigated by irradiation which practically pinned the Schottky barrier height at 0.73 eV at an experimental time scale. The origin of these defects was compared and discussed based on literature.

Analytical derivation of interface state density from sub-threshold swing in AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors

We present an analytical expression of sub-threshold swing (SS) in AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs), and describe dependences of SS on structural and relevant material parameters of the MIS-HEMTs. In this work, we derived two different equations where interface states reside at the dielectric/AlGaN interface (proposed equation) and at the AlGaN/GaN interface (conventional equation), which is the customary assumption in the literature. Analysis indicates that SS calculated by using conventional equation is always higher than that calculated by using proposed equation. To confirm the validity of the proposed equation, AlGaN/GaN MIS-HEMTs with and without recess etched gate structure are fabricated and their corresponding interface state densities are derived directly from the measured SS. The MIS-HEMTs with recess show higher SS than those without recess, which is attributed to the increase of interface state density, probably due to the damage introduced during the etching process.

Enhancing rectification of Nb:SrTiO3/ZnO heterojunctions by magnetic field

(100)Nb:SrTiO3/(110)ZnO heterojunction were epitaxially grown by RF magnetron sputtering. A typical rectification characteristic was observed before and after applying a magnetic field, but the rectifying effect was significantly enhanced after applying a magnetic field. From high and low frequency capacitance-voltage measurement, the interface state density is found to increase from 3.8 × 1012 to 8.2 × 1012 eV−1 cm−2 after applying a magnetic field of 0.55 T at room temperature. Furthermore, both the rectification ratio and interface state density increase after applying a magnetic field at temperatures from 90 to 300 K. The magnetic field enhanced rectifying effect can be understood by the increase of interface state density. This result is promising for magnetoelectric applications.

Part II: Investigation of Subthreshold Swing in Line Tunnel FETs Using Bias Stress Measurements

The role of trap-assisted tunneling (TAT) in the degradation of the subthreshold swing (SS) in n-type line tunnel field-effect transistors (TFETs) is investigated through the experiments and simulations. A two to fourfold increase in the interface state density is achieved by applying a positive or a negative stress between the gate and the source. The negative stress shows no impact on the SS in spite of nearly fourfold increase in the interface state density. A nearly twofold increase in interface state density and improvement in SS are observed under the application of positive stress. The improvement in SS is attributed to H+ species released from the Si/ SiO2 interface during stress, which moves toward the bulk Si, passivating boron and bulk Si traps, thereby improving the SS. Under negative stress bias, the released H+ species drifts toward the gate electrode, and hence no change in SS was observed. These experiments suggest that the SS degradation is mainly caused by TAT through bulk Si traps and insensitive to interface traps. A good control of bulk semiconductor trap density will be required to achieve sub-60-mV/decade SS in line TFETs.

Reliability of modified tunneling barriers for high performance nonvolatile charge trap flash memory application

Charge trap flash memory devices with modified tunneling barriers were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin SiO2 and Si3N4 dielectric layers were used as engineered tunneling barriers. High-k dielectrics were used as charge trapping and blocking oxide layer to improve the program/erase speed. The VARIOT type tunneling barrier composed of oxide-nitride-oxide layers revealed reliable electrical characteristics; long retention time and superior endurance. On the other hand, the CRESTED tunneling barrier composed of nitride-oxide-nitride (NON) layers showed degraded retention and endurance characteristics. It is found that the degradation of NON barrier is associated with the increase in interface state density at tunneling barrier/silicon channel by programming and erasing (P/E) stress.

Tunneling barrier engineered charge trap flash memory with ONO and NON tunneling dielectric layers

Tunneling barrier engineered charge trap flash (TBE-CTF) memory devices were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin SiO 2 and Si 3N 4 dielectric layers were used as engineered tunneling barrier. A faster program/erase speed as well as a larger memory window was achieved from the TBE-CTF memory. The VARIOT-type tunneling barrier composed of oxide–nitride–oxide (ONO) layers revealed a longer retention time and superior endurance characteristic. On the other hand, the CRESTED tunneling barrier composed of nitride–oxide–nitride (NON) layers showed degraded retention and endurance characteristics. It is found that the degradation of NON barrier is associated with the increase of interface state density at the tunneling barrier/silicon channel by programming and erasing ( P/ E) stress.

Evidence of negative bias temperature instability in 4H-SiC metal oxide semiconductor capacitors

Generation lifetimes and interface state densities of n-type 4H-SiC metal oxide semiconductor (MOS) capacitors are characterized by using the pulsed MOS capacitor technique. A decrease in lifetime and increase in interface state density occurs when the devices are negatively biased at 400°C. This behavior is consistent with an effect seen in Si∕SiO2 devices known as negative bias temperature instability. A portion of the lifetime degradation caused by this effect can be recovered by removing the negative bias as well as by positively biasing the device.

Effects of Thermal Annealing for Restoration of UV Irradiation Damage during Plasma Etching Processes

During plasma etching processes, UV and vacuum ultraviolet (VUV) photon irradiation generates defects and causes an increase in interface state density between SiO2 and Si. To understand the effects of pulse-time-modulated plasma on reducing damage, defects in a SiO2 film (E' center) after etching processes were measured using the electron spin resonance (ESR) method. We found that the density of the E' center was markedly reduced using C4F8/O2 pulse-time-modulated (TM) plasma etching, as compared with continuous wave (CW) plasma etching. This corresponds to the changes in interface state density using the charge pumping method. Conversely, in both cases, these E' centers were almost eliminated by H2/N2 annealing at 400 °C. Interface state density, however, remained constant even by annealing in both cases, whereas, interface state density when using TM plasma was much smaller than that when using CW plasma. This result suggests that H2/N2 annealing is not sufficient to restore the interface state density between SiO2 and Si. To reduce the increase in interface state density, UV irradiation damage must first be suppressed during plasma etching. Consequently, a combination of TM plasma etching and thermal annealing is very effective for reducing UV irradiation damage to achieve high reliability in metal–insulator–silicon (MIS) devices.

Characterization of thermally oxidized Ti∕SiO2 gate dielectric stacks on 4H–SiC substrate

The structural and electrical characteristics of thermally oxidized Ti∕SiO2 gate dielectric stacks on 4H–SiC substrates have been investigated. X-ray photoelectron spectroscopy shows a good stoichiometry of TiO2 films formed by thermal oxidation of evaporated Ti. No evidence of the formation of titanium silicide at the surface as well as in the interfacial layer was observed. Electrical measurements show, in particular, no signature of an increase in interface state density towards the conduction band edge of 4H–SiC. The improved leakage current with higher breakdown field of 11MV∕cm makes TiO2∕SiO2 stacks a potential gate insulator for high-power SiC devices.

Impact of H2/N2 annealing on interface defect densities in Si(100)/SiO2/HfO2/TiN gate stacks

This paper reports on the influence of forming gas annealing (5%H2/95%N2) over the temperature range 350 °C-550 °C on the density of electrically active interface states in Si(100)/SiO2/HfO2/TiN gate stacks. Prior to forming gas annealing the distribution of interface states across the energy gap exhibits the electrical signature of the Pb0 dangling bond centre for the hydrogen free Si(100)/SiO2 interface. Forming gas annealing at 350 °C and 400 °C results in a reduction of the interface state density, with an increase in interface state density for forming gas anneals in the range 450 °C-550 °C. The effect of the cooling ambient for the forming gas anneal (N2 or H2/N2) is also reported.

Interface trap density in amorphous La2Hf2O7/SiO2 high-κ gate stacks on Si

The present paper investigates the interface trap density of a new high-κ gate dielectric stack, La2Hf2O7/SiO2 on Silicon. Amorphous La2Hf2O7 thin films are deposited by metal evaporation in the presence of atomic oxygen beams on an ultra-thin SiO2 layer (1.5 nm) grown by rapid thermal oxidation on a p-type Si substrate. A combination of electrical (C–V) and cross sectional TEM measurements indicates a value of the dielectric constant κ of about 19±2.2. The interface states density (Dit) was measured using the conductance method for different La2Hf2O7 thicknesses ranging from 3 nm to 14 nm. Dit ranges from 3.4×1010 eV-1 cm-2 to 4.8×1012 eV-1 cm-2 and shows a quasi-linear dependence on the La2Hf2O7 layer thickness. The interface state density increase with film thickness could have different explanations, such as oxygen de-passivation and/or defect generation at the Si-SiO2 interface, formation of a new Si-SiO2 interface by Si oxidation or alternatively, the SiO2 interfacial layer reduction by oxygen vacancies.

Thickness dependence of structural and electrical characteristics of ZrO2 thin films as grown on Si by chemical-vapor deposition

Microstructural and electrical characteristics of as grown ZrO2 thin films having different thicknesses of 1.2–10 nm were investigated. The films were grown on a p-Si substrate by chemical-vapor deposition at 275 °C using zirconium t-butoxide as the precursor. The structural characterization showed that the ZrO2 films had a microstructure that changed from amorphous to polycrystalline with increased film thickness over 3.2 nm, along with a SiOx interfacial layer ∼1.5 nm thick, irrespective of the film thickness. From the hysteresis in the capacitance–voltage (C–V) relation of the Al/ZrO2/SiOx/p-Si metal–oxide–semiconductor capacitors, it was found that the density of the oxide-trapped charge drastically increased from 2.22×1010 to 3.54×1012 cm−2 as the films change from amorphous to polycrystalline. Furthermore, the shift of flatband voltage in the C–V curves revealed that the fixed charges changed sign from negative to positive. An increase of interface-state density was also found from the stretch-out of the C–V curves and the increase of turnaround voltage in the current–voltage (I–V) relation. In addition, an analysis of the I–V relation indicated that the negatively biased leakage current in the ultrathin stacked dielectrics followed the direct tunneling of holes from substrate to gate before hard breakdown. However, for the thicker films, the leakage current changed to Fowler–Nordheim tunneling of electrons from the gate to the substrate.

Comparison of degradation modes in 1.2–2.1 nm thick SiO 2 oxides submitted to uniform and hot carrier injections in NMOSFETS

In this work, we have studied the evolution of the electrical properties of 1.2–2.5 nm-thick SiO 2 oxides in N-channel metal–oxide–semiconductor field effect transistors submitted to either uniform electron injections in the direct tunneling regime or localized channel hot carrier injections. The degradation of the oxide is investigated through the classical electrical parameter set of the transistor, the gate leakage current, and charge pumping measurements. Constant current stresses at J inj=34 mA/cm 2 did not induce any damage. In contrast, constant voltage stresses at V G=3.5 V led to an increase up to a factor of 10 in the gate current, I G, in the [−0.4,−1 V] range, while small variations of transistor parameters were detected. Hot carrier stresses were performed in 50/1 μm transistors at the condition of maximum of substrate current for drain voltages, V D=3.5 and 4 V, with or without a substrate bias. We find an increase in the interface state density measured by charge pumping practically independent of the oxide thickness for times >100 s, which is correlated to transconductance and drain current reduction depending on substrate bias. But no correlation is found with the evolution of the gate current, which indicates that the I G increase is not directly linked here to the increase in interface state density revealed by charge pumping. An explanation of this apparent contradiction using the different energy levels and the localization of the defects induced in both cases is proposed.

Effects of Si-cap layer thinning and Ge segregation on the characteristics of Si/SiGe/Si heterostructure pMOSFETs

We have investigated the influence of Si-cap thickness and Ge segregation on the device properties of Si/SiGe/Si heterostructure pMOSFETs to optimize the device design. It is found that the thermal gate-oxide quality is degraded abruptly during the Si-cap thinning because Ge segregation proceeds rapidly beyond a certain critical thickness. However, it is noted that the significant increase in interface state density ( D it) occurs only if the Ge concentration at the oxide interface is high enough (∼1.8×10 22 cm −3). If D it is kept low (<5.0×10 10 cm −2 eV −1), a thinner Si cap improves device’s transconductance, on-state current, threshold voltage, and subthreshold swing owing to the larger oxide-to-channel capacitance, less parallel channel effect, and higher degree of valence band bending. Finally, the Si-cap thickness should be controlled precisely to locate the buried channel as close as possible to the oxide as long as the minimum thickness for a low D it is maintained.

Preparation and characterization of SiO 2/6H–SiC metal–insulator–semiconductor structure using TEOS as source material

Insulating SiO 2 layer was deposited on 6H–SiC by chemical vapor deposition (CVD) method using tetraethyl orthosilicate (TEOS; Si(OC 2H 5) 4) as a source material. The substrate was research grade n-type 6H–SiC. The SiO 2 film was deposited at 750 °C. Metal–insulator–semiconductor (MIS) capacitor was prepared to evaluate the interface properties between SiC and SiO 2. The sample showed capacitance–voltage curves with hysteresis loops and deep depletion characteristics. Interface-state density near mid-gap was 5×10 11 cm −2 eV − 1 , and was lower than that for the sample prepared on same substrate using thermally grown oxide as an insulating layer. Post-deposition annealing at 1000 °C in wet O 2 atmosphere resulted in increase in interface-state density.

Swift heavy ion irradiation induced modification of electrical characteristics of Au/n-Si Schottky barrier diode

Modification in the electrical transport properties of Au/n-Si(1 1 1) Schottky barrier diode (SBD) by swift heavy ion (SHI) irradiation has been investigated using in situ capacitance–voltage ( C– V) and current–voltage ( I–V) measurements at various irradiation fluences ranging from 1×10 12 to 1×10 13 ions cm −2. The variations in various parameters of the Schottky diode have been systematically studied as a function of fluence during irradiation. The ionized-donor concentration decreases with the increase in fluence, while the ideality factor, reverse saturation current and reverse leakage current increases with fluence. The change in these parameters is explained in the light of basic energy loss mechanisms of the SHI at the metal–semiconductor (MS) interface. The Schottky barrier height (SBH) decreases from a value of 0.83 eV for the unirradiated diode to 0.66 eV for the diode irradiated with a fluence of 1×10 12 ions cm −2. After this fluence the SBH remains almost constant up to a fluence of 1×10 13 ions cm −2. The reduction in SBH is caused by an increase in interface state density at the MS interface induced by SHI irradiation. The role of electronic energy loss in modification of interface states has been envisaged in relation to the immunity of SBH over a wide fluence range after an initial fluence of 1×10 12 ions cm −2.

Structure of ultrathin SiO2/Si(111) interfaces studied by photoelectron spectroscopy

Device-grade ultrathin (9–22 Å) films of silicon dioxide, prepared from crystalline silicon by remote-plasma oxidation, are studied by soft x-ray photoelectron spectroscopy (SXPS). The 2p core-level spectra for silicon show evidence of five distinct states of Si, attributable to the five oxidation states of silicon between Si0 (the Si substrate) and Si4+ (the thin SiO2 film). The relative binding energy shifts for peaks Si1+ through Si4+ (with respect to Si0) are in agreement with earlier work. The relatively weaker signals found for the three intermediate states (I1, I2, and I3) are attributed to silicon atoms at the abrupt interface between the thin SiO2 film and substrate. Estimates of the interface state density from these interface signals agree with the values reported earlier of ∼2 monolayers (ML). The position and intensity of the five peaks are measured as a function of post-growth annealing temperature, crystal orientation, and exposure to He/N2 plasma. We find that annealing produces more abrupt interfaces (by reducing the suboxide interface state density), but never more abrupt than ∼1.5 monolayers. We observe a 15%–20% drop in the interface thickness (in particular the “Si2+” peak intensity) with increasing annealing temperature. Somewhat different behavior is observed with small amounts of nitrogen in the SiO2 film where an apparent increase in interface state density is seen. A quantitative analysis is presented which explores the effects of these sample preparation parameters in terms of relative interface state density and modeling of the SXPS data.

Long-term bias temperature reliability of P/sup +/ polysilicon gated FET devices

An instability was found to be associated with +BT stress for P/sup +/ poly-gated NMOSFETs (PNMOS) and PMOSFETs (PPMOS), but not with the N/sup +/ poly-gated devices (NNMOS and NPMOS). The instability with the P/sup +/ poly-gated devices, which is a decrease in threshold voltage (V/sub t/) and an increase in interface state density (D/sub it/), was significantly reduced following N/sub 2/ annealing at 400/spl deg/C. It is shown that adequate reliability for P/sup +/ poly-gated devices can be achieved for VLSI technologies.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The effects of gamma irradiation on low-pressure chemical-vapor-deposited silicon dioxide metal-oxide-silicon structures

The effects of gamma irradiation on as-deposited, oxygen-annealed, and dual-dielectric gate (undoped polysilicon/oxide) low-pressure chemical-vapor-deposited (LPCVD) silicon dioxide (SiO 2) metal-oxide-silicon (MOS) structures were investigated. As-deposited LPCVD SiO 2 MOS structures exhibit the largest shift in flatband voltage with gamma irradiation. This is most likely due to the large number of bulk oxide traps resulting from the nonstochiometric nature of as-deposited LPCVD SiO 2. Dual-dielectric (undoped polysilicon/annealed LPCVD SiO 2) MOS structures exhibit the smallest shift in flatband voltage and increase in interface state density compared to as-deposited and oxygen-annealed LPCVD SiO 2 MOS structures. The interface state density of dual-dielectric MOS structures increases from 5 × 10 10 eV cm −2 to 2–3 × 10 11 eV cm −2 after irradiation to a gamma total dose level of 1 Mrads(Si). This result suggests that the recombination of atomic hydrogen atoms with silicon dangling bonds, either along grain boundaries or in crystallites of the undoped polysilicon layer in dual-dielectric (undoped polysilicon/annealed LPCVD SiO 2) MOS structures, probably reduces the number of atomic hydrogen atoms reaching the Si/SiO 2 interface to generate interface states.