Increasing Gate Voltage Research Articles

Improved Temperature-Scalable DC model for SiC power MOSFET including Quasi-Saturation effect

In this paper, accurate temperature-dependent static model for Silicon-Carbide (SiC) power MOSFET is presented. The proposed model is formed by two equations relating to linear and saturation operating regions. In this model, new formalism of the saturation drain current is introduced to consider the peculiar features observed in the I-V static characteristics of the SiC power MOSFET: a) moderate inversion region, or region of low gate voltages and b) quasi-saturation region, region of high gate voltages at which the drain current becomes less sensitive to the increase of gate voltage. In addition, the model captures with high-precision the transition region between linear and saturation region, pinch-off region, noticed in the output characteristics of the SiC power MOSFETs. It will be shown that the model equations ensure continuity and smooth transition between all operating regions. Temperature scaling of the model is carried out by its temperature scaling parameters. The proposed compact model is simple and efficient using reduced number of technology independent parameters. Simple parameter extraction procedure is described that uses an optimizer algorithm based on good experimental initial guess. Excellent agreement is obtained by comparing model to TCAD simulation and device measurement.

Investigation of SiC MOSFET Body Diode Reverse Recovery and Snappy Recovery Conditions

This paper investigates the behavior of SiC MOSFETs body diode reverse recovery as a function of different operating conditions. The knowledge of their effects is crucial to properly designing and driving power converters based on SiC devices, in order to optimize the MOSFETs commutations aiming at improving efficiency. Indeed, reverse recovery is a part of the switching transient, but it has a significant role due to its impact on recovery energy and charge. The set of different operating conditions has been properly chosen to prevent or force the snappy recovery of the device under testing. The experimental results and specific software simulations have revealed phenomena unknown in the literature. More specifically, the analysis of the reverse recovery charge, Qrr, revealed two unexpected phenomena at high temperatures: it decreased with increasing gate voltage; the higher the device threshold, the higher the Qrr. TCAD-Silvaco (ATLAS v. 5.29.0.C) simulations have shown that this is due to a displacement current flowing in the drift region due to the output capacitance voltage variation during commutation. From the analysis of the snappy recovery, it has emerged that there is a minimum forward current slope, below which the reverse recovery cannot be snappy, even for a high current level. Once this current slope is reached, Qrr varies with the forward current only.

THz properties of grating-gate plasmonic crystals

This study reviews recent advances in the modern field of terahertz plasmonics concerning the control of resonant properties of grating-gate plasmonic crystal structures. Particularly, we conducted both experimental and theoretical investigations of AlGaN/GaN grating-gate structures with a focus on investigations of the resonant structure of transmission spectra associated with plasmon excitations in two-dimensional electron gas at different modulation degree of concentration profiles. Two distinct resonant phases of the plasmonic crystal structure were analyzed. The first one, the delocalized phase, is observed in the case of a small modulation degree of electron gas. In this phase, we found that plasmonic resonant absorption of incident radiation occurs across the entire grating-gate structure, with domination in the gated regions of the electron gas. In contrast, the second phase, the localized one, is realized at a strong modulation of the electron concentration profiles when the gated regions of the electron gas are completely depleted. Here, plasmon resonances are characterized by the spatial localization of absorption of incident radiation exclusively within the ungated regions of the electron gas. Moreover, in the localized phase, we observed the unexpected blue shift of plasmon resonant frequency with an increase of gate voltage. This observation was explained by the result of ‘edge gating effect’ and additional shrinking of the concentration profile of the electron gas in the ungated region. We demonstrate that the correct description of both phases requires rigorous electrodynamic simulations and cannot be achieved solely in the frameworks of simplified single-mode or single-cavity models.

Giant quantum oscillations of acoustoelectric current in narrow graphene nanoribbons

A theory is presented for the acoustoelectric (AE) effect in narrow graphene nanoribbons (GNRs) deposited on a piezoelectric substrate when a surface acoustic wave (SAW) is launched onto the surface of the piezoelectric. It is assumed that the electron density in such GNRs can be controlled by applying an external gate voltage, and the acoustic wavelength is much smaller than the mean free path of electrons, so that the quantum mode of interaction of those electrons with the SAW in realized. Using the kinetic theory approach, we calculate the AE current flowing through the GNR sample and arising as a result of momentum transfer from coherent SAW phonons to conduction electrons. It is shown that size quantization of the electron energy spectrum in narrow GNRs leads to giant periodic oscillations of the AE current with a change in the gate voltage. AE current surges occur whenever the Fermi level, rising with increasing gate voltage, crosses in turn the bottom of each of the successive size-quantized electron energy subbands. The oscillations predicted are giant in the sense that the maximum values of the current exceed its minimum values by at least an order of magnitude, and they can be observed in narrow GNRs ∼10 nm wide even at room temperature.

Local mapping of surface potential in pentacene thin film under gate bias voltage obtained by scanning kelvin probe microscopy.

We report the local surface potential mapping of pentacene film prepared by physical vapor deposition with scanning kelvin probe microscopy where the sample is scanned under different gate voltages. Surface topography and the corresponding potential maps were obtained simultaneously. Spatial distribution of the surface potential at a low gate voltage is clearly correlated with topographic features. A lower electrostatic potential was measured at the grain boundaries (GBs), suggesting that GBs behave as hole traps. This observation is bolstered by conductive atomic force microscopy (C-AFM) data, which reveals a higher conductivity within the grains as opposed to the GBs. An increase in gate voltage minimizes the potential differences at the grain and GBs, suggesting a modification in trap occupancy. We expect that these experimental results, along with existing theories, will provide a better understanding of the microstructural-electrical properties of pentacene film. RESEARCH HIGHLIGHTS: Local surface potential mapping of pentacene film with scanning kelvin probe microscopy. Correlation between the surface potential map and topography at a low gate voltage. Decrease of the potential distribution inhomogeneity by the gate voltage increasement. Higher conductivity at inner grain than grain boundary in conductive atomic force microscopy.

Study of Al/a-Si:H/SiO2/n-Si/Al based bottom gate thin film transistor using RPCVD SiO2 and PECVD a-Si:H thin films: probably needed focus for bio-sensing application

In the present study Al/a-Si:H/SiO2/n-Si/Al based bottom gate thin film transistor (BGTFT) was fabricated using remote plasma enhanced chemical vapor deposited (RPCVD) SiO2 and PECVD a-Si:H. The Al/a-Si:H/SiO2/n-Si/Al based bottom gate thin film transistor was studied with an intension to apply it for bio-sensing application. The transfer characteristics of BGTFT were studied. The values of Gdd are 3.14 × 10−7 S, 1.38 × 10−7 S, 3.34 × 10−8 S, 4.84 × 10−9 S & 1.57 × 10−10 S for gate voltage Vg = −2, −1, 0, 1 & 2 V respectively. The Gdd values are found to decrease with the increase of gate voltage (Vg). The values of Gdg are 5.36 × 10−8 S, 5.98 × 10−9 S, 7.28 × 10−7 S, 2.40 × 10−7 & 5.00 × 10−9 respectively for Vd = −2, −1, 0, 1 & 2 V. The present current level and the conductance of BGTFT is so large that it is not possible to detect the proteins and antibody as these bio-molecules have charge of the order of nano amps. Therefore it requires a needed focus to study the ferroelectric or high k material as the active material instead of a-Si:H for BGTFT for bio-sensing application as the ferroelectric materials have low conductance and channel current. This will be our future work to use ferroelectric or high k materials as the active materials of BGTFT.

Oxide and Interface Defect Analysis of lateral 4H-SiC MOSFETs through CV Characterization and TCAD Simulations

We investigated oxide and interface defects of lateral 4H-SiC MOSFETs through capacitance-voltage (C-V) and conductance-voltage (G-V) characterization at various frequencies and temperatures. By employing consecutive up and down sweeps of the gate voltage at three different temperatures, we experimentally characterized the hysteresis width as the difference between up and down sweeps in the depletion to accumulation (d-a) and depletion to inversion (d-i) regions. We observed an increase in the hysteresis width with decreasing temperature. Although the hysteresis width is not affected by the small-signal frequency, at the same time, increasing the frequency leads to a strong stretch-out effect, especially in the d-i region.Our measurement results indicate that the hysteresis deformation of the C-V curves is dominated by three different trap types. First, interface acceptor-like defects located close to the conduction band can follow the small-signal frequency. Slower acceptor-like border traps with trap levels both close to the conduction band and in the middle of the band gap are however responsible for the increase of trapped negative charge with increasing gate voltage. Finally, we assume the presence of a fixed positive charge.

Controlled crossover of electron transport in graphene nanoconstriction: From Coulomb blockade to electron interference

The ability to control transport behaviors in nanostructure is crucial for usage as a fundamental research platform as well as a practical device. In this study, we report a gate-controlled crossover of electron transport behaviors using graphene nanoconstrictions as a platform. The observed transport properties span from Coulomb blockade-dominated single electron transmission to electron–wave interference-dominated quantum behavior. Such drastic modulation is achieved by utilizing a single back gate on a graphene nanoconstriction structure, where the size of nanostructure in the constriction and coupling strength of it to the electrodes can be tuned electrically. Our results indicate that electrostatic field by gate voltage upon the confined nanostructure defines both the size of the nanoconstriction as well as its interaction to electrodes. Increasing gate voltage raises Fermi level to cross the energy profile in the nanoconstriction, resulting in decreased energy barriers which affect the size of nanoconstriction and transmissivity of electrons. The gate-tunable nanoconstriction device can therefore become a potential platform to study quantum critical behaviors and enrich electronic and spintronic devices.

Impact of high-k metal oxide as gate dielectric on the certain electrical properties of silicon nanowire field-effect transistors: A simulation study

Standard Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) are gaining prominence in low-power nanoscale applications. This is largely attributed to their proximity to physical and thermal limits, rendering them a compelling option for energy-efficient electronic devices. In this study, we hypothesized that the high-? HfO2 in a quasi-ballistic SiNW MOSFET acts as the gate dielectric. In this case, the data from the TCAD simulation and the model demonstrated exceptional agreement. The proposed model for a SiNW MOSFET with high-? HfO2 exhibits a consistently increasing drain current, albeit with a smaller magnitude compared to a quasi-ballistic device (QBD). Additionally, it shows reduced mobility and decreased transconductance when considering the combined effects of scattering and temperature. As gate voltage increases, temperatureinduced transconductance decline in SiNW MOSFETs becomes significant. Our method is suitable for modeling scattered SiNW MOSFETs with temperature effects, as TGF values are similar in the subthreshold region for both Near Ballistic and Scattered SiNW MOSFET models.

Trion-trion annihilation in monolayer WS2

Strong Coulomb interaction in monolayer transition metal dichalcogenides can facilitate nontrivial many-body effects among excitonic complexes. Many-body effects like exciton-exciton annihilation (EEA) have been widely explored in this material system. However, a similar effect for charged excitons (or trions), that is, trion-trion annihilation (TTA), is expected to be relatively suppressed due to repulsive like-charges, and has not been hitherto observed in such layered semiconductors. By a gate-dependent tuning of the spectral overlap between the trion and the charged biexciton through an "anti-crossing"-like behaviour in monolayer WS$_2$, here we present an experimental observation of an anomalous suppression of the trion emission intensity with an increase in gate voltage. The results strongly correlate with time-resolved measurements, and are inferred as a direct evidence of a nontrivial TTA resulting from non-radiative Auger recombination of a bright trion, and the corresponding energy resonantly promoting a dark trion to a charged biexciton state. The extracted Auger coefficient for the process is found to be tunable ten-fold through a gate-dependent tuning of the spectral overlap.

Probing electron diffusion length in an accumulation layer in a ligand-free lead sulfide colloidal quantum dot monolayer

Developing an understanding of the minority carrier diffusion in the effective channel close to the gate dielectric in a field effect transistor (FET) configuration has proven to be challenging because the minority carriers are affected by the gate electric field. We, for the first time, have investigated the minority carrier (electron) diffusion length in ultrathin lead sulfide (PbS) colloidal quantum dots (CQDs) treated with ammonium sulfide ((NH4)2S) using photocurrent microscopy (PCM). With increasing gate voltage, an electron diffusion length is found to be gate-dependent, which can be explained by the increased hole occupancy in the midgap states.Using the FET mobility in the (NH4)2S-treated PbS CQDs, we calculated the electron lifetime. We present the first demonstration of the electric field -modulated electron diffusion length in a PbS CQD film treated with an atomic ligand using PCM.

Spin transport characteristics and photoelectric properties of magnetic semiconductor NiBr<sub>2</sub> monolayer

Magnetic semiconductor materials have potential applications in spintronic devices. In this work, some nano-device structures based on the magnetic semiconductor NiBr<sub>2</sub> monolayer (NiBr<sub>2</sub>-ML) are designed, their spin-resolved transport and photoelectric properties are studied by using density functional theory combined with non-equilibrium Green’s function method. The results show that both the NiBr<sub>2</sub>-ML PN-junction diodes and sub-3 nanometer PIN-junction field-effect transistors (FETs) exhibit the significant rectification and spin filtering effects in either the armchair or the zigzag direction. The gates can obviously tune the electron transmission of the PIN-junction FETs. The current is significantly suppressed with the increase of gate voltage. In addition, NiBr<sub>2</sub>-ML has a strong response to the blue and green light, thus its phototransistor can generate a strong photocurrent under the irradiation of blue and green light. The research results in this paper reveal the multifunctional characteristics of NiBr<sub>2</sub>-ML, which provides an important reference for the application of nickel-based dihalides in semiconductor spintronic devices and optoelectronic devices.

Facile preparation of a MXene-graphene oxide membrane and its voltage-gated ion transport behavior.

Two-dimensional MXenes have become a crucial topic in the field of ion transportation owing to their excellent electrochemical performance. Herein, a strategy for preparing a layered MXene-graphene oxide (GO) membrane via vacuum filtration is proposed, which endows the delaminated two-dimensional MXene-GO membrane (MGOm) with excellent electrical conductivity and chemical stability, achieving an excellent voltage-gated ion transport behavior. Owing to the presence of charges or dipoles within the membrane's channel, the movement of electrons or dipoles under the influence of membrane potential is possible. By varying the transmembrane potential, the transition between the closed and open states of the voltage-gated ion channel can be adjusted. When a negative potential is applied at osmotic pressure, the force between the charged MGOm sheet and the cation (K+) is enhanced, promoting ion permeation. Conversely, the application of positive potential attenuates electrostatic attraction, resulting in a decrease in ion permeability. In addition, the effects of MXene and GO with different modulation ratios on the voltage-gated ion transport have shown that when the modulation ratio of MXene : GO is 7 : 3, the optimal ion permeation rate is achieved. In conclusion, the conductive film with voltage-gated nanochannels is a promising alternative for ion transportation, opening up new avenues for the further exploration of MXene materials in energy storage devices.

Integration of Organic Electrochemical Transistors with Implantable Probes

AbstractOrganic electrochemical transistors (OECTs) are widely used as amplifying transducers of biological signals due to their high transconductance and biocompatibility. For implantable applications that penetrate into tissue, OECTs need to be integrated onto narrow probes. The scarcity of real estate necessitates the use of small local gate electrodes and narrow interconnects. This work shows that both of these factors lead to a decrease in the maximum transconductance and an increase in gate voltage required to attain this maximum. This work further shows that coating the gate electrode with a thick conducting polymer improves performance. These findings help guide the development of efficient OECTs on implantable probes.

Electrical tuning of the spin–orbit interaction in nanowire by transparent ZnO gate grown by atomic layer deposition

We develop an InAs nanowire gate-all-around field-effect transistor using a transparent conductive zinc oxide (ZnO) gate electrode, which is in situ atomic layer deposited after growth of a gate insulator of Al2O3. We perform magneto-transport measurements and find a crossover from the weak localization effect to the weak antilocalization effect with an increasing gate voltage, which demonstrates that the Rashba spin–orbit coupling is tuned by the gate electrode. The efficiency of the gate tuning of the spin–orbit interaction is higher than those obtained for a two-dimensional electron gas, and as high as that for a gate-all-around nanowire metal-oxide-semiconductor field-effect transistor that was previously reported. The spin–orbit interaction is discussed in line with not only a conventionally used one-dimensional model but also with a recently proposed model that considers effects of microscopic band structures of materials.

Giant circular photogalvanic effect of the surface states in an ultra-thin Bi2Se3 nanoplate grown by chemical vapor deposition

Ultra-thin Bi2Se3 nanoplates with high crystal quality are obtained by chemical vapor deposition (CVD). A giant circular photogalvanic effect (CPGE) has been observed in the ultra-thin Bi2Se3 nanoplates, which is about one order larger than that previously observed in the thick Bi2Se3 nanoplates grown by CVD and that in the thin Bi2Se3 film grown by molecular beam epitaxy. By applying an ionic liquid gate, the CPGE can be effectively tuned. As the gate voltage increases, the magnitude of the CPGE current decreases, suggesting that the CPGE current under zero gate voltage is dominated by surface states rather than the two-dimensional electron gas (2DEG). It is revealed that as the surface roughness of the Bi2Se3 nanoplates increases, the CPGE decreases and finally reverses the sign, indicating the dominant contribution of the CPGE switches from the top surface states to the 2DEG or the bottom surface states.

Hysteresis Behavior of the Donor-Acceptor-Type Ambipolar Semiconductor for Non-Volatile Memory Applications.

Donor–acceptor-type organic semiconductor molecules are of great interest for potential organic field-effect transistor applications with ambipolar characteristics and non-volatile memory applications. Here, we synthesized an organic semiconductor, PDPPT-TT, and directly utilized it in both field-effect transistor and non-volatile memory applications. As-synthesized PDPPT-TT was simply spin-coated on a substrate for the device fabrications. The PDPPT-TT based field-effect transistor showed ambipolar electrical transfer characteristics. Furthermore, a gold nanoparticle-embedded dielectric layer was used as a charge trapping layer for the non-volatile memory device applications. The non-volatile memory device showed clear memory window formation as applied gate voltage increases, and electrical stability was evaluated by performing retention and cycling tests. In summary, we demonstrate that a donor–acceptor-type organic semiconductor molecule shows great potential for ambipolar field-effect transistors and non-volatile memory device applications as an important class of materials.

AlGaN/GaN-Based Laterally Gated High-Electron-Mobility Transistors With Optimized Linearity

In this work, highly linear AlGaN/GaN laterally gated (or buried gate) high-electron-mobility transistors (HEMTs) are reported. The effect of gate dimensions on source-access resistance and the linearity of laterally gated devices are investigated experimentally in detail for the first time. Transistors with different gate dimensions and conventional planar devices are fabricated using two-step electron beam lithography (EBL). Current–voltage, source-access resistance, small-signal, and two-tone measurements are performed to evaluate the linearity of devices. Contrary to conventional planar HEMTs, the intrinsic transconductance of laterally gated devices monotonically increases with increasing gate voltage, showing a similar behavior as junction field-effect transistors (FETs). The source-access resistance shows a polynomial increase with the drain current, which can be reduced by decreasing the filling ratio of the buried gates. Through the optimization of these two competing factors, i.e., intrinsic transconductance and the source-access resistance, flat transconductance with high linearity is achieved experimentally. The laterally gated structure shows flat transconductance and small-signal power gain over a larger span of gate voltage that is 2.5 times higher than a planar device. Moreover, 6.9-dB improvement in output intercept point (OIP3)/ ${P}_{\text {DC}}$ is achieved. This approach can be used to improve the linearity of AlGaN/GaN HEMTs at the device level.

Equivalent Circuit Modeling of a Dual-Gate Graphene FET

This paper presents a simple and comprehensive model of a dual-gate graphene field effect transistor (FET). The quantum capacitance and surface potential dependence on the top-gate-to-source voltage were studied for monolayer and bilayer graphene channel by using equivalent circuit modeling. Additionally, the closed-form analytical equations for the drain current and drain-to-source voltage dependence on the drain current were investigated. The distribution of drain current with voltages in three regions (triode, unipolar saturation, and ambipolar) was plotted. The modeling results exhibited better output characteristics, transfer function, and transconductance behavior for GFET compared to FETs. The transconductance estimation as a function of gate voltage for different drain-to-source voltages depicted a proportional relationship; however, with the increase of gate voltage this value tended to decline. In the case of transit frequency response, a decrease in channel length resulted in an increase in transit frequency. The threshold voltage dependence on back-gate-source voltage for different dielectrics demonstrated an inverse relationship between the two. The analytical expressions and their implementation through graphical representation for a bilayer graphene channel will be extended to a multilayer channel in the future to improve the device performance.

Sn Doping Effects in Solid-Phase Crystallized Ge Thin-Film Transistors

Introduction Low-temperature synthesis of high carrier mobility thin films on insulating substrates is actively being conducted to dramatically improve the device performance of thin-film transistors (TFTs). Ge is one of the candidates for next-generation TFTs because of its high carrier mobility and good compatibility with Si. We recently reported that the densification of amorphous (a-) Ge precursor in solid-phase crystallization (SPC) significantly enlarged the grain size of polycrystalline (poly-) Ge and improved Hall effect hole mobility μ Hall [1]. The TFT using this Ge layer exhibited both high field effect mobility μ FE (170 cm2/Vs) and on/off current ratio I on/I off (~102) without minimizing the channel region (< 1 μm) [2]. The key technology was thinning the 100 nm thick Ge film with a large grain size (3.7 μm) enough to fully deplete the channel. Very recently, we further improved μ Hall by combining the precursor densification method with Sn incorporation in SPC [3,4]. In this study, we fabricate TFT using SPC-GeSn and further improve its performance. Experimental Procedure The a-Ge1−x Sn x (0 ≤ x ≤ 4.5%) precursors were deposited on SiO2 glass substrates using the Knudsen cell of a molecular beam deposition system (base pressure of 5 × 10−7 Pa). The deposition rate of Ge was fixed at 1.0 nm/min at room temperature, whereas that of Sn was adjusted to obtain the targeted GeSn composition. The deposition time was 100 min. The precursors were densified by heating the substrate at 125 °C during deposition [1,3,4]. The samples were then loaded into a conventional tube furnace in an N2 atmosphere annealed at 450 °C for 5 h to induce SPC. The grown layers were analyzed by the electron backscattering diffraction (EBSD) measurement and Hall effect measurement (van der Pauw method).We fabricated accumulation-mode metal source/drain (S/D) p-channel TFTs using SPC-GeSn. Pt and TiN were sequentially formed as a metal S/D and a capping layer, respectively. The PtGe/Ge contacts have low hole barrier height and are suitable for p-channel Ge-TFTs. We used Al/SiO2/Al2O3/SiO2/GeO2 for the gate stack with the equivalent oxide thickness of 17.7 nm. The channel width and length (W/L) were 55 and 5–10 μm, respectively. Here, all process including SPC were conducted below 450 °C. Results and Discussion First, we discuss the crystalline quality and electrical properties of the SPC-GeSn layer. Figure 1(a) shows that the crystal grain size dramatically varies with initial Sn concentration x and maximized at x = 1.6%. These results are roughly consistent with the solid solubility of Sn in Ge of approximately 1%–2%. We thinned x = 1.6% sample with the maximum grain size using chemical-mechanical polishing (CMP) to fabricate TFT for full depletion in poly-GeSn layer. As a reference, we also thinned x = 0% sample. Figure 1(b) shows that hole concentration p is constant in-depth direction although hole mobility μ Hall decreases by thinning. The Sn doping in Ge provides lower p.Finally, we discuss the TFT characteristics fabricated on the thinned SPC samples (55 nm for Ge and 50 nm for GeSn). Figure 2(a) shows that the typical p-channel transistor operation, i.e., drain current I D increases with increasing gate voltage V G. Figure 2(b) shows Sn doping reduces the off current I off significantly under keeping the on current I on. This reflects the electrical properties of the GeSn film obtained by the Hall effect measurement (Fig.1 (b)). Figure 3 summarizes the relationship between μ FE and I on/I off for different channel length (L = 5, 10, and 15 μm) in the same substrate. The experimental data show a clear increase in variability as the channel length decreases, which is in good agreement with the trends of poly-Si-TFTs. This is the first result showing such variability reflecting grain boundary at poly-Ge and GeSn. Furthermore, Sn doping improves I on/I off by roughly an order of magnitude although μ FE is almost identical. These results thus demonstrate the usefulness of Sn doping of polycrystalline Ge in TFT application. The current TFT performance will be further improved by the optimization of Sn concentration, film thickness, and channel dimensions (W/L). Reference [1] K. Toko, K. Moto et al., Sci. Rep. 7, 16981 (2017).[2] K. Moto et al., Appl. Phys. Lett. 114, 212107 (2019).[3] K. Moto et al., Sci. Rep. 8, 14832 (2018).[4] K. Moto et al., Appl. Phys. Lett. 114, 112110 (2019). Figure 1