Increase In Gate Leakage Current Research Articles

Collapse of MOSFET Drain Current After Soft Breakdown

Gate-oxide soft breakdown (SB) can have a severe impact on MOSFET performance even when not producing any large increase of the gate leakage current. The SB effect on the MOSFET characteristics strongly depends on the channel width W: drain saturation current and MOSFET transconductance dramatically drop in transistors with small W after SB. As W increases, the SB effect on the drain current fades. The drain saturation current and transconductance collapse is due to the formation of an oxide defective region around the SB spot, whose area is much larger than the SB conductive path. Similar degradation can be observed even in heavy ion irradiated MOSFETs where localized damaged oxide regions are generated by the impinging ions without producing any increase of gate leakage current.

Influence of doping concentration on DC and RF performance of AlGaN/GaN HEMTs on silicon substrate

AlGaN/GaN HEMTs with different carrier supply layers are fabricated on Si substrate, using MOVPE growth technique. The influence of the carrier supply doping concentration on the HEMT properties is investigated by Hall measurements and by electrical DC and RF characterisation of transistor devices. Hall mobility is found to decrease with increasing sheet concentration, while the gate leakage current increases. The device with the highest carrier supply doping concentration of 1019 cm−3 is provided with a GaN cap layer to reduce gate leakage. The transistors based on modulation doped layer structures show much higher DC performance than the undoped device. Best RF properties are obtained for a doping level of 5 × 1018 cm−3. High frequency measurements exhibit fT and fMAX values of 35 GHz and 37 GHz, respectively, for devices with 300 nm gate length. (© 2003 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Characteristics of Oxide Breakdown and Related Impact on Device of Ultrathin (2.2 nm) Silicon Dioxide

The oxide breakdown characteristics of ultrathin oxide (2.2 nm) have been studied in this paper. Light emission microscopy (EMMI) analysis shows that each breakdown has a specific failure location with a random distribution. Gate leakage current increases for all soft breakdown events are similar. After soft breakdown, the I–V curve still shows the representative direct tunneling characteristics and can be fitted using a dual direct tunneling (DDT) model. Soft breakdown has no effect on the drain current of long-channel devices. Breakdown at the polyedge appears to be of the hard-breakdown mode and results in an abrupt increase in gate current. For short-channel devices, the polyedge is always within the damaged region of an oxide because the channel is shorter than the damaged region of the oxide. Hence, only hard breakdown resulting in permanent damage is observed in short-channel devices.

Localized oxide degradation in ultrathin gate dielectric and its statistical analysis

Conventional oxide reliability studies determine oxide lifetime by measuring the time to breakdown or quasi-breakdown (QB). In ultrathin gate oxides with T/sub ox/<14 /spl Aring/, however, it is hard to observe breakdown or QB under typical stress conditions. Instead, the gate leakage current shows a continuous increase over the entire time period of electrical stress. As the magnitude of the gate current density increase eventually becomes too high to be acceptable for normal device operation, a lifetime criterion based on the increase in gate leakage current is proposed. Our paper also shows that the area-dependence of the gate leakage current density increase in 13.4 /spl Aring/ oxides is different from that in thicker oxide films, indicating a localized and discrete property of the leakage current. It has also been observed that the oxide lifetime based on the new lifetime criterion is shorter when the gate area is smaller, as opposed to the conventional area dependence of time-to-breakdown test. A simple model consisting of multiple degraded spots is proposed and it has been shown that localized gate leakage current can be described by Weibull's statistics for multiple degraded spots.

Observation of inductively coupled-plasma-induced damage on n-type GaN using deep-level transient spectroscopy

The effects of inductively coupled plasma (ICP) etching on electrical properties of n-type GaN Schottky contacts were investigated by observing ion damage using deep-level transient spectroscopy. An electron trap, not previously seen, localized near the contact, as well as a pre-existing trap, was observed in the ICP-etched sample. The ICP-etched surface was found to be N-deficient, which means that N vacancies (VN) were produced by ICP etching. From these, the origin of the ICP-induced electron trap was suggested to be VN or a VN-related complex of point defects. The ICP-induced traps provided a path for the transport of electrons, leading to the reduction of Schottky barrier height and increase of gate leakage current.

Characterization of Inductively-Coupled-Plasma Damage on n-Type GaN Using Deep-Level Transient Spectroscopy and Synchrotron Radiation Photoemission Spectroscopy

Inductively-coupled-plasma (ICP) damage on n-type GaN was characterized using deep-level transient spectroscopy and synchrotron radiation photoemission spectroscopy. A new electron trap, localized near the contact, as well as a pre-existing trap was observed in the ICP-etched sample. The ICP-etched surface was found to be N-deficient, which means that N vacancies (VN) were produced by ICP etching. The Fermi energy level shifted to the conduction band minimum due to the generation of VN. From these, the origin of T2 was suggested to be VN or VN-related complex of point defects. The ICP-induced traps provided a path for the transport of electrons, leading to the reduction of Schottky barrier height and increase of gate leakage current.

Degradation and SILC Effects of RPECVD sub-2.0nm Oxide/Nitride and Oxynitride Dielectrics Under Constant Current Stress

AbstractConstant current stress (CCS) has been used to investigate the Stress-Induced Leakage Current (SILC) to clarify the influence of boron penetration and nitrogen incorporation on the breakdown of p-channel devices with sub-2.0 nm Oxide/Nitride (O/N) and oxynitride dielectrics prepared by remote plasma enhanced CVD (RPECVD). Degradation of MOSFET characteristics correlated with soft breakdown (SBD) and hard breakdown (HBD), and attributed to the increased gate leakage current are studied. Gate voltages were gradually decreased during SBD, and a continuous increase in SILC at low gate voltages between each stress interval, is shown to be due to the generation of positive traps which are enhanced by boron penetration. Compared to thermal oxides, stacked O/N and oxynitride dielectrics with interface nitridation show reduced SILC due to the suppression of boron penetration and associated positive trap generation. Devices stressed under substrate injection show harder breakdown and more severe degradation, implying a greater amount of the stress-induced defects at SiO2/substrate interface. Stacked O/N and oxynitride devices also show less degradation in electrical performance compared to thermal oxide devices due to an improved Si/SiO2 interface, and reduced gate-to-drain overlap region.

The Effect of Surface Passivation and Illumination on the Device Properties of AlGaN/GaN HFETs

The gate current of AlGaN/GaN heterojunction field effect transistors, with and without a SiN passivation layer, has been studied as a function of temperature. At room temperature, the gate leakage current for the passivated devices is larger than for the unpassivated ones. In all of the devices anomalous behaviour of the I G -V GS characteristic occurs. For characteristics above approximately 100°C this behaviour disappears. In all of the devices, the gate leakage current increases with temperature with a smaller increase for the passivated devices than the unpassivated ones. After measurement of the device characteristics at elevated temperatures, the room temperature characteristics have changed. The gate leakage is lower. This effect is more noticeable in the region where the device is on.

The Effect of Surface Passivation and Illumination on the Device Properties of AlGaN/GaN HFETs

The gate current of AlGaN/GaN heterojunction field effect transistors, with and without a SiN passivation layer, has been studied as a function of temperature. At room temperature, the gate leakage current for the passivated devices is larger than for the unpassivated ones. In all of the devices anomalous behaviour of the I G -V GS characteristic occurs. For characteristics above approximately 100°C this behaviour disappears. In all of the devices, the gate leakage current increases with temperature with a smaller increase for the passivated devices than the unpassivated ones. After measurement of the device characteristics at elevated temperatures, the room temperature characteristics have changed. The gate leakage is lower. This effect is more noticeable in the region where the device is on.

Plasma-Process-Induced Damage in Sputtered TiN Metal-Gate Capacitors with Ultrathin Nitrided Oxides

A comprehensive study on plasma-process-induced damage (P2ID) in sputtered TiN metal-gated devices with 4 nm N2O-nitrided oxide was performed. We found that the TiN metal-gated devices exhibit a significant 8 Å reduction in the effective oxide thickness, due to physical damage caused by sputtering and/or oxide consumption during the postannealing step. We also found that the postdeposition rapid thermal annealing (RTA) temperature affects both the flat-band voltage (Vfb) and the interface state density (Dit). Furthermore, degradation in the gate-oxide integrity caused by severe charging damage by the additional plasma processes in the TiN metal gate process flow was also observed. The P2ID leads to significant degradation in the charge-to-breakdown and a gate leakage current increase, even for the genuinely robust nitrided oxide used in this study. Finally, N2 plasma posttreatment was proposed as an effective method for suppressing the gate leakage current.

Transistor characteristics with Ta/sub 2/O/sub 5/ gate dielectric

As the gate oxide thickness decreases below 2 nm, the gate leakage current increases dramatically due to direct tunneling current. This large gate leakage current will be an obstacle to reducing gate oxide thickness for the high speed operation of future devices. A MOS transistor with Ta/sub 2/O/sub 5/ gate dielectric is fabricated and characterized as a possible replacement for MOS transistors with ultra-thin gate silicon dioxide. Mobility, I/sub d/-V/sub d/, I/sub d/-V/sub g/, gate leakage current, and capacitance-voltage (C-V) characteristics of Ta/sub 2/O/sub 5/ transistors are evaluated and compared with SiO/sub 2/ transistors. The gate leakage current is three to five orders smaller for Ta/sub 2/O/sub 5/ transistors than SiO/sub 2/ transistors.

Rapid degradation of MESFETs under impact ionization and low-temperature conditions

Tests performed on power MESFETs under impact ionization and low-temperature conditions reveal a faster and higher device degradation than those at higher temperatures. Degradation produces a noticeable reduction in breakdown voltage together with an increase in gate leakage current. The same effect is exhibited in high-temperature tests, but is less severe. In this paper, the temperature effect of the degradation on the performance of high output power microwave devices under impact ionization conditions is illustrated.

Metal/intrinsic semiconductor/semiconductor field effect transistor fabricated from polycrystalline diamond films

A metal/intrinsic semiconductor/semiconductor field effect transistor (MiSFET) was successfully fabricated for the first time using polycrystalline diamond films grown by microwave plasma chemical vapor deposition. The gate length, the gate width, and the source-to-drain spacing were 10 μm, 1 mm, and 30 μm, respectively. The FET characteristics were measured with the source electrode grounded. For the range of drain voltage VD, −10 V ≤ VD≤0, the fabricated MiSFET exhibited a reduction of the drain current as the gate bias VG was increased from 0 to 6 V at room temperature. The drain current modulation was considerably enhanced at 77 K. The transconductance at VD=−10 V and VG=2 V was 5 μS/mm. For VD&amp;lt;−10 V and VG≳6 V, or at temperatures above room temperature to 398 K, the drain current modulation decreased significantly due to increased gate leakage current.

Development of cosmic ray hardened power MOSFET's

Developmental power DMOS (double-diffused metal-oxide-semiconductor) FETs were thoroughly characterized in a simulated cosmic-ray environment using heavy ions at the Brookhaven National Laboratory's tandem Van de Graaff accelerator facility. The primary failure mode encountered on FETs in this environment was susceptibility to single-event burnout. Burnout of the power DMOS FET was catastrophic. Another failure mode was single-event gate rupture. Although gate rupture is not as severe as burnout, its long-term effects are not known. Single-event gate rupture causes performance degradation due to increased gate leakage current. An increase in current can pose serious problems for applications that cannot compensate for the added performance degradation. Long-term reliability of the gate oxide may be affected, resulting in premature device failure. Numerous processing lots were fabricated to verify experimentally that each failure mode could be successfully minimized. Test results have shown that an n-channel, 150-V DMOS FET survived exposures to ions with linear energy transfers up to 80 MeV-cm/sup 2//mg. Hardening approaches are discussed, including their advantages and disadvantages in relation to the FET's performance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>