Increase In Gate Leakage Current Research Articles

The effect of Si3N4/Al2O3 stacked structure of AlGaN/GaN HEMTs

Excessive gate leakage current and current collapse effects are the critical reliability issues for GaN-based high electron mobility transistors (HEMTs). In this paper, Si3N4 passivation layers was grown separately on p-GaN gate HRCL-HEMTs with or without Al2O3 film, and the gate leakage and current collapse effects of the devices and their intrinsic mechanisms were investigated. It is found that the device with Si3N4/Al2O3 stacked structure has better performance in terms of gate reverse leakage current, breakdown voltage, etc. The Al2O3 film blocking layer can reduce the H plasma damage to the channel, decrease the gate leakage, and the passivation can effectively suppress the increase of gate leakage current. Through variable temperature characteristic test, it is verified that the dominant mechanism of the device gate reverse leakage current is the two-dimensional variable range hopping (2D-VRH) model. The interface state between Si3N4 passivation layer and Al2O3 film increases the trap activation energy of the device, which is the reason for the reduction of gate reverse leakage current, and also causes the current collapse effect of the device.

Role of AlGaN back-barrier in enhancing the robustness of ultra-thin AlN/GaN HEMT for mmWave applications

In this work, the robustness of three different AlN/GaN structures targeting high frequency applications with ultra-thin 3 nm AlN barrier and devices with different gate-to-drain spacing are evaluated. Devices were step-stress tested in off-state, semi-on-state, and on-state conditions. Different failure mechanisms were identified. Devices without AlGaN back-barrier show a fast increase of gate leakage current, leading to a significant degradation of electrical parameters such as the threshold voltage Vth, extrinsic transconductance GM, drain saturation current IDSsat and on-resistance Ron. This study reveals the role of the AlGaN back-barrier in the improvement of the device robustness presenting a good electrical parameters stability. The presence of an AlGaN back-barrier on low carbon- doped buffer leads to better gate leakage current stability, low trapping-related and self-heating mechanisms. The AlGaN back-barrier shows an extension of the operational Safe Operating Area for AlN/GaN technology.

Reliability Assessment of On-Wafer AlGaN/GaN HEMTs: The Impact of Electric Field Stress on the Mean Time to Failure.

We present the mean time to failure (MTTF) of on-wafer AlGaN/GaN HEMTs under two distinct electric field stress conditions. The channel temperature (Tch) of the devices exhibits variability contingent upon the stress voltage and power dissipation, thereby influencing the long-term reliability of the devices. The accuracy of the channel temperature assumes a pivotal role in MTTF determination, a parameter measured and simulated through TCAD Silvaco device simulation. Under low electric field stress, a gradual degradation of IDSS is noted, accompanied by a negative shift in threshold voltage (ΔVT) and a substantial increase in gate leakage current (IG). Conversely, the high electric field stress condition induces a sudden decrease in IDSS without any observed shift in threshold voltage. For the low and high electric field conditions, MTTF values of 360 h and 160 h, respectively, were determined for on-wafer AlGaN/GaN HEMTs.

Voltage-margin limiting mechanisms of AlScN-based HEMTs

In this work, the off-state characteristics of AlScN/GaN high electron mobility transistors (HEMTs) grown by metalorganic chemical vapor deposition (MOCVD) were studied and directly compared to an AlGaN- and an AlN-HEMT grown in the same MOCVD. Pinch-off instability and leaky capacitive measurements were observed for AlScN-based HEMTs, which was correlated with a higher ideality factor and lower effective potential barrier height than the AlGaN and AlN-HEMTs. However, the reverse bias characteristics exhibited a sudden drain-current increase without a significant increase in gate-leakage current. The drain-leakage current is assumed to be related to a parasitic channel across the AlScN-barrier as a result of trap-assisted carrier transport with a Poole–Frenkel characteristic. The demonstrated pinch-off instability led to significant gain expansion in load-pull measurements and early soft-breakdown, which, in turn, limits the achievable voltage-margin. The results demonstrate a key issue to reveal the full potential of AlScN-based HEMTs for mm-wave applications.

Low-Temperature Deuterium Annealing for the Recovery of Ionizing Radiation-Induced Damage in MOSFETs

Ionizing radiation generates bulk traps (Not) as well as interface traps (Nit) in the gate dielectric. These traps cause unwanted threshold voltage (VTH) shifting, subthreshold swing (SS) and increased gate leakage current (IG). In this study, we used low-deuterium annealing (LTDA) as an alternative to conventional annealing, to minimize the side effects of thermal budget. Deuterium atom absorption was confirmed using secondary ion mass spectrometry (SIMS). DC characterizations are performed to analyze the recovery of the gate dielectric damages. Our results demonstrate that the proposed LTDA enables the curing of the gate dielectric damage caused by not only fabrication processing, but also by ionizing radiation. Operating deuterium annealing under low-temperature conditions can improve device performance, reliability, and device-to-device variability.

Modeling the Effects of Threading Dislocations on Current in AlGaN/GaN HEMT

The aim of this paper is to model the effects of threading dislocations on both gate and drain currents of AlGaN/GaN high electron mobility transistors (HEMTs). The fraction of filled traps increases with the threading dislocations, while the trapping effects cause a decrease in drain current and an increase in gate leakage current. To model the drain current drop, the two simplified RC subcircuits with diodes are proposed to capture the charge trapping/detrapping characteristics. The trap voltages Vg_trap and Vd_trap generated by RC networks are fed back into the model to capture the effects of traps on drain current. Considering acceptor-decorated dislocations, we present a novel Poole-Frenkel (PF) model to precisely describe the reverse leakage gate current, which plays a dominant role in the gate leakage current. The proposed model, which uses physical parameters only, is implemented in Verilog-A. It is in excellent agreement with the experimental data.

Study on characteristics of neutron-induced leakage current increase for SiC power devices

In this paper, the displacement damage degradation characteristics of silicon carbide (SiC) Schottky barrier diode (SBD) and metal oxide semiconductor field effect transistor (MOSFET) are studied under 14-MeV neutron irradiation. The experimental results show that the neutron irradiation with a total fluence of 1.18×10<sup>11</sup> cm<sup>–2</sup> will not cause notable degradation of the forward <i>I-V</i> characteristics of the diode, but will lead to a significant increase in the reverse leakage current. A defect with energy level position of <inline-formula><tex-math id="Z-20230916130504">\begin{document}$ E_{\rm{C}} - 1.034 $\end{document}</tex-math><alternatives><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="18-20230976_Z-20230916130504.jpg"/><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="18-20230976_Z-20230916130504.png"/></alternatives></inline-formula> eV is observed after irradiation by deep level transient spectroscopy (DLTS) testing, which is corresponding to the neutron-induced defect cluster in SiC. This deep level defect may cause the Fermi level of n-type doping drift region to move toward the mid-gap level. It ultimately results in the decrease of the Schottky barrier and the increase of the reverse leakage current. In addition, neutron-induced gate leakage increase is also observed for SiC MOSFET. The gate current corresponding to <i>V</i><sub>gs</sub> = 15 V after irradiation increases nearly 3.3 times that before irradiation. The donor-type defects introduced by neutron irradiation in the oxide layer result in the difference in the conductivity mechanism of gate oxygen between before and after irradiation. The defects have an auxiliary effect on carrier crossing the gate oxide barrier, which leads to the increase of gate leakage current. The defects introduced by neutron irradiation are neutral after capturing electrons. The trapped electrons can cross a lower potential well and enter the conduction band to participate in conduction when the gate is positively biased, thus causing the gate current to increase with the electric field increasing. After electrons captured by donor-type defects enter the conduction band, positively charged defects are left from the gate oxide, leading to the negative shift of the transfer characteristics of SiC MOSFET. The results of DLTS testing indicate that the neutron irradiation can not only cause the intrinsic defect state of SiC material to change near the channel of MOSFET, but also give rise to new silicon vacancy defects. However, these defects are not the main cause of device performance degradation due to their low density relative to the intrinsic defect’s.

Degradation Behavior and Mechanism of SiC Power MOSFETs Under Repetitive Transmission Line Pulse Stress

The electrostatic discharge robustness of silicon carbide (SiC) power metal–oxide–semiconductor field-effect transistors (MOSFETs) are investigated by the transmission line pulse (TLP) method. The degradation behavior of key electrical parameters of the device under repetitive TLP stress is investigated. A decrease in threshold voltage, an increase in gate leakage current, and the degradation of gate capacitance parameters are observed compared with the prestress values. Low-frequency noise (LFN) test results show that after multiple TLP stress cycles, the typical leakage current noise of the device increases by approximately one order of magnitude compared to prestress, which means that the trap density extracted based on the McWhorter model increases by one order of magnitude after 1000 TLP stress pulses. Furthermore, sources of defects in the gate oxide dielectric of the devices after stresses are analyzed. The physical mechanism of the changes of SiC MOSFETs characteristics could be attributed to the hole trapping by oxygen vacancy defects and single carbon interstitial in the oxide layer after TLP stresses, which induces an electrostatic effect and results in the changes in the electrical properties of the devices. The results may be useful in the design and application of SiC power MOSFETs.

Molecular and Atomic Layer Deposition of Hybrid Polyimide–Al2O3 Gate Dielectrics for Flexible Electronic Devices

Modern information technologies have tremendous demands on flexible electronic devices such as thin-film transistors (TFTs). As the flexible TFT technology continues to advance, the properties of the gate dielectric become a bottleneck for the flexible TFTs to achieve fast switching speed, low operation voltage, and downscaling. The gate dielectric layer should be sufficiently thin, insulating, and flexible, and therefore, hybrid organic–inorganic dielectrics are of great promise for this purpose. In this work, we develop a scalable vapor-phase MLD/ALD technique, which combines molecular layer deposition (MLD) and atomic layer deposition (ALD), to grow a new hybrid polymer–oxide dielectric thin-film material of polyimide (PI) and Al2O3, and demonstrate that the afforded hybrid polyimide–Al2O3 (HPA) films are well suited as the bendable gate dielectrics for flexible electronic applications. We also perform mechanism investigation on the growth of PI and Al2O3 during the MLD/ALD HPA process and find that the growth of PI is strongly affected by the Al2O3 surface and therefore exhibits a two-stage behavior. We further evaluate the electrical and bending performances of the afforded HPA dielectrics and apply the HPA films as the gate dielectrics for flexible carbon-nanotube TFTs. The fabricated TFTs can well withstand 1000-time repetitive bending without an increase in the TFT gate leakage current, which shows the high promise of the HPA dielectrics for flexible electronic applications. Considering that the MLD/ALD fabrication approach is advantageous for high process reproducibility and large-scale compatibility, we envision that the MLD/ALD-prepared HPA dielectrics will have great applications in future complex flexible electronic circuits.

Study of the influence of gate etching and passivation on current dispersion, trapping and reliability in RF 0.15 μm AlGaN/GaN HEMTs

In this paper we examine the effect of passivation and gate etching processes on the current dispersion and reliability of AlGaN/GaN HEMTs for RF applications. We compared the performance of HEMTs with a standard gate etching and passivation processes (reference wafer) with the performances of HEMTs with improved etching process (etching variant wafer) and improved passivation process (passivation variant wafer). In order to study the trapping behavior, we performed dispersion measurements in off-state conditions and drain current transients (DCT) and we found that:1)The use of improved passivation process determines a decrease of current dispersion, in particular at the knee voltage, where current collapse depends on both threshold voltage and on-resistance variation,2)The trapping process linked to surface states is influenced by the gate etching and passivation processes; the use of improved passivation slows down the trapping/de-trapping kinetics, resulting in a lower impact on dynamic performance.The study of reliability is based on high-temperature reverse bias (HTRB) stresses. The gate-drain diodes are biased in the same voltage stress conditions (VGS,Stress = -7 V, VDS,Stress = 50 V) at high temperatures (175 °C) for 24 h. We demonstrated that the improved passivation limits the increase of gate leakage current during HTRB stress and prevents the belly shape effect linked to the presence of donor traps in the surface between SiN and GaN cap.We performed gate step stress increasing the negative voltage applied to the Schottky contact. The electroluminescence images performed during the stress show spots along the gate finger that are the responsible of the failure of the devices. The results presented in the paper provide information on the optimization of GaN HEMTs for RF applications.

Electrical properties and energy band alignment of SiO2/GaN metal-oxide-semiconductor structures fabricated on N-polar GaN(0001¯) substrates

The interface properties and energy band alignment of SiO2/GaN metal-oxide-semiconductor (MOS) structures fabricated on N-polar GaN(0001¯) substrates were investigated by electrical measurements and synchrotron-radiation x-ray photoelectron spectroscopy. They were then compared with those of SiO2/GaN MOS structures on Ga-polar GaN(0001). Although the SiO2/GaN(0001¯) structure was found to be more thermally unstable than that on the GaN(0001) substrate, excellent electrical properties were obtained for the SiO2/GaN(0001¯) structure by optimizing conditions for post-deposition annealing. However, the conduction band offset for SiO2/GaN(0001¯) was smaller than that for SiO2/GaN(0001), leading to increased gate leakage current. Therefore, caution is needed when using N-polar GaN(0001¯) substrates for MOS device fabrication.

Analysis of Instability Behavior and Mechanism of E-Mode GaN Power HEMT with p-GaN Gate under Off-State Gate Bias Stress

In this study, we investigate the degradation characteristics of E-mode GaN High Electron Mobility Transistors (HEMTs) with a p-GaN gate by designed pulsed and prolonged negative gate (VGS) bias stress. Device transfer and transconductance, output, and gate-leakage characteristics were studied in detail, before and after each pulsed and prolonged negative VGS bias stress. We found that the gradual degradation of electrical parameters, such as threshold voltage (VTH) shift, on-state resistance (RDS-ON) increase, transconductance max (Gm, max) decrease, and gate leakage current (IGS-Leakage) increase, is caused by negative VGS bias stress time evolution and magnitude of stress voltage. The significance of electron trapping effects was revealed from the VTH shift or instability and other parameter degradation under different stress voltages. The degradation mechanism behind the DC characteristics could be assigned to the formation of hole deficiency at p-GaN region and trapping process at the p-GaN/AlGaN hetero-interface, which induces a change in the electric potential distribution at the gate region. The design and application of E-mode GaN with p-GaN gate power devices still need such a reliability investigation for significant credibility.

Reduced Reverse Gate Leakage Current for p‐GaN Gate High‐Electron‐Mobility Transistors by a Surface‐Etching Method

Herein, the mechanism of increased gate leakage current observed in SiNx‐passivated high‐resistivity cap layer high‐electron‐mobility transistors (HRCL‐HEMTs) is investigated. The leakage is found to be correlated with the roughened morphology and deviated surface stoichiometry caused by H‐plasma treatment. An additional step of surface etching before passivation restores GaN surface and gate leakage is reduced by about two orders of magnitude, whereas the other electrical characteristics of p‐GaN HEMTs are preserved.

Effect of Atmosphere on Electrical Characteristics of AlGaN/GaN HEMTs Under Hot-Electron Stress

In this work, we demonstrate the degradation behavior and physical mechanism of AlGaN/GaN high-electron-mobility transistors (HEMTs) under hot-electron stress in hydrogen and nitrogen atmosphere. According to the monitoring results, the trends of ${I}_{\text {ds}}$ values are completely different during the same hot-electron stress in two types of atmosphere. The ${I}_{\text {ds}}$ values of the devices in pure hydrogen (the purity is 99.999%) continue decreasing at first and then remain at a fixed value, whereas the ${I}_{\text {ds}}$ values of the devices in pure nitrogen (the purity is 99.999%) recover to the initial value after the instability during the heating section and then instantaneously drop to zero 18 h after the beginning of the experiment. Comparing current–voltage ( ${I}$ – ${V}$ ) characteristics before and after the hot-electron stress experiment in hydrogen atmosphere, we find the output current decreases, the threshold voltage shifts forward, the gate leakage current increases, the current collapse enhances, and the gate-lag characteristic becomes worse. Based on our previous research, it can be concluded that hot-electron effects rather than hydrogen effects are the primary cause of device degradation. Moreover, the degradation in hydrogen atmosphere is more severe than that in nitrogen atmosphere according to the monitoring results of ${I}_{\text {ds}}$ values. We believe that the hydrogen can exacerbate the hot-electron effects through maintaining the lower junction temperature because of its higher thermal conductivity. A COMSOL finite-element simulation has been done to explain the mechanism.

Analysis of 4H-SiC MOSFET with distinct high-k/4H-SiC interfaces under high temperature and carrier-trapping conditions

In this work, the reliability of different oxide/4H-SiC interfaces under high temperature and carrier-trapping conditions are investigated carefully. In more detail, the carrier-trapping and temperature effects are considered in the electrical characterization of a low breakdown 4H-SiC-based MOSFET by using in turn SiO2, Si3N4, AlN, Al2O3, Y2O3 and HfO2 as gate dielectric. A gate oxide with a high relative permittivity notably improves the transistor performance. In addition, HfO2 assures the MOSFET best immunity behaviors. The obtained results are explained in terms of the carrier channel mobility, device on-state resistance, and oxide electric field. By using HfO2, however, an increased gate leakage current is calculated. This drawback is overcome by inserting a thin interfacial layer (2 nm-thick) in the HfO2/4H-SiC MOS structure. In particular, two alternative gate stacked dielectrics, involving either SiO2 or Al2O3, have proven their effectiveness in preserving the transistor on-state figures of merit while limiting the gate leakage current in the whole explored gate voltage range. To support the prediction capabilities of the presented modeling analysis, the simulations results are compared with experimental data from literature resulting in a good agreement. Low power MOSFETs are used in several applications for which reliability and durability are as critical as performance. For example, referring to power optimizers for photovoltaic (PV) modules, which fall under the low-load and low-voltage category of DC–DC converters, these devices significantly increase the energy generated by each single PV module operating under harsh conditions and stressing environments. In addition, they have to ensure high reliability over the long term of operation.

The Development of a New Ion Versus Log(Ig) Plot to Characterize Depletion-Mode High Electron Mobility Transistors with the Insertion of a Very Thin Evaporated Al Layer to AlGaN/GaN High Electron Mobility Transistors as an Example

Previously, we showed that the Id_on vs. log Id_off plot can be used to characterize silicon-based enhancement-mode MOS transistors for both p-channel and n-channel [1]. AlGaN/GaN high electron mobility transistors (HEMTs) have attracted world-wide interest for microwave power transistor applications. There are two kinds of AlGaN/GaN HEMTs: depletion-mode and enhancement-mode AlGaN/GaN HEMTs. In general, depletion-mode AlGaN/GaN HEMTs are more common. For depletion-mode devices with the source at 0 V, even though the gate voltage may be close to zero, the gate leakage current increases with the increase of the drain voltage and can be significant because of a large drain voltage. Thus the gate leakage current may limit the maximum drain voltage and thus the RF power output of the device. For depletion-mode high electron mobility transistors (HEMTs), it can be easily imagined that both the on current (Ion) and the gate leakage current (Ig) will be increased by using a low work function metal as gate metal. Thus the drain on current (Id_on) and the gate leakage current (Ig) alone will not be a good criterion to judge the quality of depletion-mode HEMTs. In this paper, we would like to propose the application of a new Id_on vs. log Ig plot to characterize depletion-mode HEMTs. In the literature, a lot of various approaches have been proposed to cut down the gate leakage current. Recently, Nanjo et al. proposed to use a thin Al layer inserted between AlGaN and the Schottky metal gate to reduce the gate leakage current [2]. The advantage of this approach was subsequently confirmed by Selvaraj and Egawa [3]; however, they emphasized on the increase of the drain current instead of the reduction in the gate leakage current. It is natural to wonder how Al insertion can ever increase the drain current. Hence, the physics behind this approach is not yet clear. In this paper, we will also propose our theory regarding the physics of Al gate for AlGaN/GaN HEMT’s. With the help of this new plot, the superiority of the sample with Al/Ni/Au gate compared to the control sample with Ni/Au gate can be easily seen because the on current is higher for the same gate leakage current.As shown in Fig. 1, it can be easily shown that the Al insertion significantly improves the device for the same gate leakage current. According to theory, the Schottky barrier height φb is given by φb = φm - χs, where φm and χs are the metal work function and the electron affinity of the semiconductor. It is known that the work function of Al is significantly lower than that of Ni. It can be easily predicted that AlGaN/GaN HEMT with Al gate should have much larger gate leakage current compared to that with Ni gate. In fact, this was experimentally observed by us if the Al was evaporated rapidly during sample deposition. Our explanation of the advantage of Al insertion was that there was residual water vapor present in the vacuum chamber during electron beam evaporation [4]. According to Kordos et al. [5], the electron mobility of the 2-D electron gas at the AlGaN/GaN interface can be improved by a thin layer of Al2O3 on top of AlGaN/GaN. This experimental observation was also reported by Liu et al. [6]. It can be easily imagined that the presence of a thick layer of Al2O3 on top of AlGaN/GaN will degrade the performance of AlGaN/GaN HEMT because the distance between the metal gate and the AlGaN/GaN interface becomes bigger. However, when the thickness of the Al2O3 layer is small enough, the improvement of the electron mobility will be more significant than the degradation due to the increase of the distance between the metal gate and the AlGaN/GaN interface, resulting in the improved performance of the AlGaN/GaN HEMT.

Investigation on Degradation of SiC MOSFET Under Accelerated Stress in a PFC Converter

The reliability concern of SiC MOSFETs has been extensively investigated with various accelerated stress tests. However, these conventional tests are predominantly performed in a simplified and controlled testing environment, which might or might not realistically simulate the actual device operation profiles in power converters. In this article, we report the long-term degradation phenomenon of several types of SiC MOSFETs in an actual 2-kW power factor correction (PFC) converter and provide an analysis of the degradation mechanisms. Compared to conventional dc power cycling tests, a large decrease in threshold voltage was observed due to gate oxide degradation of SiC MOSFET in a PFC converter. Online monitoring results show that the ON-state voltage drop of SiC MOSFET continuously rises with the increase of stress times. The increase in ON-state voltage is caused by the change of package resistance and channel resistance. Gate oxide degradation resulting in a large increase in drain-source leakage current and gate leakage current. Meanwhile, the variation of miller plateau voltage and threshold voltage results in a significant change of turn-on losses in SiC MOSFET. TCAD simulation, and C- V measurement indicate that the main degradation mechanism is hot holes accumulation within the gate oxide above the JFET region and channel region due to high electric field stress.

Neutron-induced displacement damage effect and mechanism of AlGaN/GaN high electron mobility transistor

In this paper, neutron-induced displacement damage effects of AlGaN/GaN High electron mobility ransistor (HEMT) device and heterostructure on the Xi’an pulse reactor are studied. The equivalent 1 MeV neutron fluence is 1 × 10<sup>14</sup> n/cm<sup>2</sup>. The direct-current characteristics and low frequency noise characteristics of the HEMT deviceare used to characterize the performances before and after being irradiated by the neutrons, and then the experimental results are analyzed theoretically. The analysis results showed that the displacement damage effect caused by the neutron irradiation will introduce the bulk defects into the device. The bulk defects at the channel cause the electrical performance of the device to degrade through trapping electrons and scattering electrons, which are mainly manifested as the drift of positive threshold voltage, the decrease of output saturation drain current, and the increase of gate leakage current. In order to further confirm the effect of neutron irradiation on the defect density of the device, we implement the low-frequency noise test and the calculation of the device, and the results show that the defect density at the channel of the device increases from 1.78 × 10<sup>12</sup> cm<sup>–3</sup>·eV<sup>–1</sup> to 1.66 × 10<sup>14</sup> cm<sup>–3</sup>·eV<sup>–1</sup>, which is consistent with the results of the electrical characteristics test, indicating that the new defects introduced by neutron irradiation do degrade the electrical performance of the device. At the same time, the capacitor-voltage test is also carried out to analyze the Schottky heterojunctions before and after neutron irradiation. It is found that the channel carrier concentration is significantly reduced after irradiation, and the flat band voltage also drifts positively. The analysis shows that after irradiating the device with neutrons, a large number of defects will be generated in the channel, and these defects will affect the concentration and mobility of the channel carriers, which in turn will influence the electrical performance of the device. These experimental results can be used for designing the AlGaN/GaN high electron mobility transistor for radiationhard reinforcement.

Total ionizing dose effects on graphene-based charge-trapping memory

This study investigates the total ionizing dose effects in graphene-based charge-trapping memory (GCTM) capacitors by using $^{60}$Co $\\gamma$-irradiation. Electrical properties including $C-V$ hysteresis window, gate leakage current, and flat band voltage shifts are evaluated with ionizing dose levels up to 1 Mrad (Si). The $C-V$ hysteresis memory window is hardly affected by the irradiation. The gate leakage current increases with the increase of ionizing dose due to the multiple-trap assisted tunneling mechanism. Significant electrical degrade of the devices in programmed and erased states has been observed with the increase of the dose levels. Mechanisms behind the degradation are attributed to the photo-emission in the graphene nanodisc charge-trapping sets, radiation-induced holes trapping in the peripheral oxides, and the recombination of the stored electrons with the radiation-induced holes.

Implications of Ageing Through Power Cycling on the Short-Circuit Robustness of 1.2-kV SiC mosfets

In this paper, the reliability performance of 1.2-kV silicon carbide (SiC) power mosfet modules is investigated through the combination of both accelerated power-cycling tests and short-circuit tests. The short-circuit robustness of SiC mosfet is investigated after stressing the dies under power-cycling tests. In this way, the implications of different levels of degradation on the short-circuit capability can be better understood. During the power-cycling tests, some electrical parameters, either related to the package or the die, may experience variations as a consequence of the device ageing (e.g., increase in bond wire resistance and increase in gate leakage current). The effect of these parameter variations on the short-circuit withstanding capability of SiC mosfets is investigated for the first time in this paper. The proposed method helps to understand which degradation effects under normal operation have a major implication on the short-circuit robustness, which gives a more realistic information about the root cause of the failures observed in the field.