Control of flat-band voltage (Vfb) in 4H-SiC gate stacks is inevitable for high-voltage power MOSFET applications, since a sufficiently large threshold voltage (Vth) is required to suppress the false turn on. However, the increase in channel doping concentration to tune Vth results in a drastic reduction of carrier mobility in the inversion channel, due to Coulomb scattering caused by SiO2/4H-SiC interface [1]. Therefore a negative shift of Vfb is not preferred in terms of channel resistance reduction. The SiC surface nitridation process by a post-oxidation annealing (POA) in NO ambient at elevated temperature is an inevitable technique to suppress the interface defects [2]. However, a serious drawback is the fact that a negative shift of Vfb is often observed by employing NO-POA.Two possible mechanisms are to be considered which cause negative Vfb shifts in SiO2/4H-SiC MOS gate stacks: the generation of positive fixed charges, and the formation of interface dipole layers. We systematically investigated the flat-band voltage of SiO2/4H-SiC (0001) n-type MOS capacitors with various oxide thickness, fabricated by conventional dry oxidation followed by NO-POA at 1150℃ for several hours. When fixed charges are existing at the interface, it is natural to observe a linear relationship between the oxide thickness and Vfb, where we can estimate the fixed charge density from the slope. As a result, we found that the fixed charge densities were quite small after sufficient nitridation processes, however, an anomalous negative shift of Vfb in several hundreds of mV irrespective of oxide thickness was observed, which was enlarged by extending NO annealing duration [3]. This anomalous shift would be explainable by assuming a dipole layer formation at the interface by SiC surface nitridation, which may be caused by polar Si3-N tetrapod structure formation with high density aligned at the interface.Next we studied the impact of additional annealing after nitridation on Vfb, since the SiC device processes in general require such additional annealing including metallization processes. We conducted an additional 1 min rapid thermal annealing in N2 after NO-POA (post-nitridation anneal; PNA) at various temperatures from 800 to 1150℃. As a result, positive interface fixed charges were generated more by the PNA at higher temperatures [4], while fixed charge generation was insignificant by the PNA at low temperature such as 800℃ [4]. Note that interface state density did not change significantly by these PNA processes.Besides the influences on the Vfb shift, the interface dipole layer formation naturally affects the SiO2/4H-SiC band alignment. The conduction band offset, which is one of the critical factors to determine the gate leakage current level, must be dependent on the dipole layer strength. The valence-band spectra analysis using x-ray photoelectron spectroscopy and the energy barrier height characterization of Fowler-Nordheim current analysis tell us that the conduction-band offset at SiO2/SiC interface monotonically becomes larger by increasing the amount of nitrogen at the interface, which is consistent with the negative shift of Vfb observed in MOS capacitors [3]. To our surprise, this trend appeared in opposite direction when the gate stacks were fabricated on 4H-SiC (1-100) wafers [5].Finally we examined another way to tune the Vfb of SiC gate stacks by the introduction of additional dipole layer, by depositing of just a few nm-thick Al2O3 layer on top of SiO2 after NO-POA, based on the concept of oxide interface dipole layers reported for various high-k/SiO2 interfaces. As a result we successfully demonstrated ~1V Vfb shift without any deterioration of interface state density only by Al2O3 deposition [6]. This technique is expected as an additional method to achieve larger Vfb.In conclusion, we found that Vfb of nitrogen passivated SiO2/4H-SiC gate stacks is significantly affected by two factors: the positive fixed charges at the interface mainly introduced by post-nitridation annealing, and the interface dipole layer formation due to the polar structures aligned at the interface, or the intentionally introduced dipole layer by depositing a few nm-thick Al2O3 on top of SiO2.[1] M. Noguchi et al., Jpn. J. Appl. Phys. 58, 031004 (2019).[2] J. Rozen et al., J. Appl. Phys. 105, 124506 (2009).[3] T. H. Kil and K. Kita, Appl. Phys. Lett. 116, 122103 (2020).[4] T. H. Kil and K. Kita, 2021 International Workshop on Dielectric Thin Films for Future Electron Devices: Science and Technology (IWDTF), Nov. 2021.[5] T. H. Kil, A. Tamura, S. Shimizu and K. Kita, Appl. Phys. Express 14, 081005 (2021).[6] T. H. Kil, M. Noguchi, H. Watanabe, and K. Kita, Solid-State Electronics 183, 108115 (2021).
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Aug 11, 2022
Fu-Song Ma + 4
Open Access