Increase In Silicon Area Research Articles

Design and Implementation of a Generic CORDIC Processor and its Application as a Waveform Generator

Background: With the advent in hand held mobile computing devices, the demand for high performance compact processors is increasing. In this work a processor is designed with hardwired instructions for elementary mathematical functions like sine, cosine, sinh, cosh, division and multiplication. Methods: The processor employs Coordinate Rotation Digital Computer (CORDIC) algorithm for efficient hardware implementation of the above mentioned instructions. The parallel and pipelined implementation of the processor is carried out. The pipelined processor is configured as waveform generator. The novelty of this work is the integration of both trigonometric and hyperbolic operations in the same processor. Findings: ASIC Implementation is carried out with 40nm technology libraries. The parallel processor so designed operates at maximum frequency of 24.23 MHz and pipelined processor operates at maximum frequency of 261.36 MHz. Conclusion: This increase in operating frequency is achieved at the cost of increased silicon area and optimal power dissipation. The waveform generator generates sine, cosine waves of 3.5 MHz and sine hyperbolic, cosine hyperbolic waves and exponential waves of 7.9 MHz. The limitation being the waveform generator generates waves of constant frequency. Additional circuit is required in generating waves of different frequencies.

Area‐ and power‐efficient DC–DC converter with on‐chip compensation

A dual-path capacitor multiplier (DPCM) technique is proposed for on-chip frequency compensation. The DPCM uses two currents to charge and discharge a compensation capacitor concurrently. Consequently, the equivalent capacitance is amplified dramatically with slight increase in silicon area and power. Thanks to the DPCM, the transient response of the DC-DC converter has improved significantly because of the small compensation capacitor. Experimental results demonstrate converter stability and transient response. The transient recovery time of a 450 mA step load change is <;30 μs. With the proposed technique, the compensation capacitor is shrunk significantly and adding the compensation resistor would have helped in improving transient response.

Power Efficient SDR Implementation of IEEE 802.11a/p Physical Layer

Software defined physical layer modems can be considered the new trend in the field of communications. Differently from dedicated hardware, software can be easily modified to implement a large variety of standards on the same platform. The use of software can significantly reduce development costs, but generally comes at the price of an increase in silicon area and power consumption. For different reasons, this price is something that is not always convenient or even possible to pay, as in the case of low-cost ICs implementing a single waveform, or even multi-mode modems embedding legacy IPs already available in hardware. In particular, power consumption overhead can be prohibitive for mobile terminals or in general for battery-powered devices. The very first challenge for a computing fabric to be competitive is to find and implement the right trade-off between flexibility and performance. This was the guideline for the design of the Block Processing Engine (BPE), a template architecture conceived for power-efficient baseband processing. The BPE core feature is a mixed-grain instruction set balancing general-purpose fine-grain instructions with more specific coarse-grain instructions wrapping custom hardware modules. To further limit the power consumption, the BPE also implements instruction-pipelining, variable-size SIMD and multi-task support. To prove the efficiency of such an approach, a dual-mode IEEE 802.11a/p receiver has been implemented.

FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture

Guarded evaluation is a power reduction technique that involves identifying subcircuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times during circuit operation, thereby reducing switching activity and lowering dynamic power. The concept is rooted in the property that under certain conditions, some signals within digital designs are not “observable” at design outputs, making the circuitry that generates such signals a candidate for guarding. Guarded evaluation has been demonstrated successfully for application-specific integrated circuits (ASICs); in this paper, we apply the technique to field-programmable gate arrays (FPGAs). In ASICs, guarded evaluation entails adding additional hardware to the design, increasing silicon area and cost. Here, we apply the technique in a way that imposes minimal area overhead by leveraging existing unused circuitry within the FPGA. The primary challenge in guarded evaluation is in determining the specific conditions under which a subcircuit's inputs can be held constant without impacting the larger circuit's functional correctness. We propose a simple solution to this problem based on discovering gating inputs using “noninverting” and “partial noninverting” paths in a circuit's AND-inverter graph representation. Experimental results show that guarded evaluation can reduce switching activity on average by as much as 32% and 25% for 6-input look-up table (6-LUT) and 4-LUT architectures, respectively. Dynamic power consumption in the FPGA interconnect is reduced on average by as much as 24% and 22% for 6-LUT and 4-LUT architectures, respectively. The impact to critical path delay ranges from 1% to 43%, depending on the guarding scenario and the desired power/delay tradeoff.

Comparative analysis of yield optimized pulsed flip-flops

In this paper, the influence of random process variations on pulsed flip-flops is analyzed. Monte Carlo simulation results demonstrate that using transistor reordering and dual threshold voltage transistors timing, energy and energy-delay-product yields of more than 1.98, 1.62 and 1.99 times higher are obtained, without requiring architectural modifications and without increasing silicon area requirement. Several flip-flops optimized as described here are compared taking into account the effects due to random process variations and to environmental variations (caused by power supply voltage and temperature fluctuations). Obtained results show that among the compared circuits the Conditional Precharge Flip-Flop achieves the highest delay, energy and energy-delay-product yields.

Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding

A new domain-specific, reconfigurable system-on-a-chip (SoC) architecture is proposed for video motion estimation. This has been designed to cover most of the common block-based video coding standards, including MPEG-2, MPEG-4, H.264, WMV-9 and AVS. The architecture exhibits simple control, high throughput and relatively low hardware cost when compared with existing circuits. It can also easily handle flexible search ranges without any increase in silicon area and can be configured prior to the start of the motion estimation process for a specific standard. The computational rates achieved make the circuit suitable for high-end video processing applications, such as HDTV. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards. Indeed, the cost/performance achieved exceeds that of existing but specific solutions and greatly exceeds that of general purpose field programmable gate array (FPGA) designs.

Modulo scheduling without overlapped lifetimes

This paper describes complementary software- and hardware-based approaches for handling overlapping register lifetimes that occur in modulo scheduled loops. Modulo scheduling takes the N-instructions in a loop body and constructs an M-stage software pipeline. The length of each stage in the software pipeline is the Initiation Interval (II), which is the rate at which new loop iterations are started. An overlapped lifetime has a live range longer than the II, and as a consequence, the current iteration writes a new value to a register before a previous loop iteration has fin-ished using the old value. Hardware and software solutions for dealing with overlapped lifetimes have been proposed by re-searchers and also implemented in commercial products. These solutions include rotating register files, register queues, modulo variable expansion, and post-scheduling live range splitting. Each of these approaches has drawbacks for embedded systems such as an increase in silicon area, power consumption, and code size. Our approach, which is an improvement to the current solutions, prevents overlapped lifetimes through a combination of hardware and software techniques. The hardware element of our approach implements a register assignment latency that allows multiple in-flight writes to be pending to the same register. The software element of our approach uses dependence analysis and a constrained modulo scheduling algorithm to prevent overlapped lifetimes. We describe how to use these hardware and software techniques during modulo scheduling. Finally, we present the results of using our approach to compile embedded application code and present results in terms of modulo schedule quality and application performance.

Systematic methodology for designing low power direct digital frequency synthesisers

The overall operation of a direct digital frequency synthesiser (DDFS) is based on a look-up table method, which performs functional mapping from phase to sine amplitude. The spectral purity of the conventional DDFS is determined by the resolution of the values stored in the sine table ROM. However, large ROM storage means higher power consumption, increased silicon area, lower reliability, lower speed and increased costs. A novel systematic design methodology for implementing a DDFS architecture with reduced memory size is introduced. Describing the proposed architecture using the hardware description language VHDL, it is possible to generate a plethora of alternative realisations in terms of the number of input and output bits, the memory size, the number of gates, the memory segmentation parameters and the spectral purity. In other words, the designer can perform extensive architecture exploration to reach an optimal solution. The experimental results prove that the new DDFS architecture can be realised with a smaller hardware complexity and total power consumption and improved performance compared to many existing approaches.

An ultra-low power operating technique for mega-pixels current-mediated CMOS imagers

A novel ultra-low power operating technique is presented for mega-pixels current-mediated CMOS imagers. In the proposed technique, the reset and read-out phases occur simultaneously: as a single pixel is being read-out another pixel is being reset. Such a strategy reduces power consumption by more than 2 orders of magnitude for current- mediated mega-pixels CMOS imagers, while still allowing for on-read-out fixed pattern noise correction. Power consumption becomes independent of both read-out speed and imager array size. Additionally, the proposed operating technique leads to improved linearity for the pixel response, increased dynamic range as well as on-chip digital shutter functionality. A single additional address decoder is required to generate the reset signals, resulting in a marginal increase in silicon area. The wiring overhead is kept to a minimum with only a single control signal required to operate the current- mediated CMOS imager.

Low-power digital neuron for SOM implementations

A digital implementation of the self-organising map (SOM) is shown to have reduced power requirements through a strategy of increasing silicon area while reducing the number of clock cycles required to process each element of an input vector. Designs requiring two clock cycles, one clock cycle, and half clock cycle per element of the input vector have been constructed and analysed. The designs offer a reduction in power of a factor of 3 for an increase in silicon area of some 33%.

Low-power CMOS digital design

Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption. >

An experiment in Smart sensor design

Abstract The greatest benefits of silicon technology occur when a total system or subsystem is placed on a single chip. Smart sensors, having integrated electronics so that they can match into a standard microprocessor bus system, are an excellent example of the latter. On the one chip all aspects of silicon technology are exploited; a silicon sensor combined with both analog and digital circuitry. While the concept is simple, implementation is still a difficult problem. The Centre set out to construct a low-cost single-chip general-purpose sensor and discovered, amongst other things, that there is a significant increase in silicon area and hence cost penalty when a microprocessor is included on the chip. Consequently the division of responsibility between the smart sensor and the main-system microprocessor becomes an important decision to make. This paper examines the experiences of the Centre in carrying out the experiment so far.

CMOS/SOS High Soft-Error Threshold Memory Cell

The five-transistor (5T) CMOS/SOS memory cell has been widely used in RCA's radiation hardness products. The p-channel devices in the memory cell are protected from the cosmic ray hit by the buried contact diodes. However, there is no protection for the n-channel devices. A configuration referred to as seven-transistor (7T) CMOS/SOS memory cell which is modified from the 5T memory cell layout by inserting a depletion mode NMOS transistor in the feedback path of enhancement NMOS drain node has been proposed. Simulations show that this configuration increases the single event upset critical charge by a factor of 25 at Vdd=5V. The increase in silicon area is only 10%.

Mechanism of silicon etching by a CF4 plasma

The mechanisms for the reactive ion etching of silicon by CF4 plasma are investigated. A model is proposed whereby silicon is etched by chemical reaction with free fluorine to produce a volatile species, and also by physical sputtering. The chemical etching is shown to be enhanced by ion bombardment of the reacting surface. This etching process, together with a model for cracking CF4 in the plasma, is evaluated by comparison to actual etch rates. Experimentally, the silicon etch rate is observed to decrease with increasing silicon area, by what is called the loading effect. The functional form of the loading effect, as predicted by the model, is fitted to experimental loading curves. The contributions of the various etching components are separated, to yield empirical values for the enhancement of the chemical reaction by physical sputtering.