Power Efficient SDR Implementation of IEEE 802.11a/p Physical Layer

Abstract

Software defined physical layer modems can be considered the new trend in the field of communications. Differently from dedicated hardware, software can be easily modified to implement a large variety of standards on the same platform. The use of software can significantly reduce development costs, but generally comes at the price of an increase in silicon area and power consumption. For different reasons, this price is something that is not always convenient or even possible to pay, as in the case of low-cost ICs implementing a single waveform, or even multi-mode modems embedding legacy IPs already available in hardware. In particular, power consumption overhead can be prohibitive for mobile terminals or in general for battery-powered devices. The very first challenge for a computing fabric to be competitive is to find and implement the right trade-off between flexibility and performance. This was the guideline for the design of the Block Processing Engine (BPE), a template architecture conceived for power-efficient baseband processing. The BPE core feature is a mixed-grain instruction set balancing general-purpose fine-grain instructions with more specific coarse-grain instructions wrapping custom hardware modules. To further limit the power consumption, the BPE also implements instruction-pipelining, variable-size SIMD and multi-task support. To prove the efficiency of such an approach, a dual-mode IEEE 802.11a/p receiver has been implemented.