Increase In Power Dissipation Research Articles

Numerical study on heat transfer and flow characteristics of symmetric Tesla-type microchannel heat sinks

This study numerically investigates the thermal performance of multi-stage Tesla valve microchannels (TVM) and a symmetric variant (SYMTVM) using single-phase deionized water, with mass flow rates ranging from 0.5459 to 1.6377 g/s. Both designs, particularly under reverse flow, exhibit lower peak temperatures and reduced temperature gradients compared to forward flow. The SYMTVM, characterized by its increased vortices and bifurcations, periodically disrupts and redevelops the thermal boundary layer, enhancing heat transfer efficiency. The TVM exhibits a significantly higher pressure drop than the SYMTVM across all flow conditions, with the reverse flow in TVM reaching up to 2.48 times that of forward flow and exceeding SYMTVM, especially at a peak flow rate of 1.6377 g/s. The performance evaluation criteria (PEC) and thermal resistance criteria (PECTR) demonstrate the superior performance of SYMTVM, with a reduced connection angle between the trunk and helix regions enhancing thermal efficiency. Furthermore, the SYMTVM-Reverse structure with a 30° interconnection angle demonstrates superior performance compared to the conventional rectangular microchannel (RM), achieving a Nusselt number (Nu) that is five times higher than that of the RM and an overall performance up to 2.59 times greater. These results indicate the SYMTVM-Reverse’s high heat transfer efficiency and its capacity to effectively balance thermo-hydraulic performance, even with increased power dissipation.

Steep Slope Field Effect Transistors Based on 2D Materials

AbstractWith field effect transistor (FET) sustained to downscale to sub‐10 nm nodes, performance degradation originates from short channel effects (SCEs) degradation and power consumption increment attributed to inhibition of supply voltage (VDD) scaling down proportionally caused by thermionic limit subthreshold swing (SS) (60 mV dec−1) pose substantial challenges for today's semiconductor industry. To further sustain the Moore's law life, incorporation of new device concepts or new materials are imperative. 2D materials are predicted to be able to combat SCEs by virtue of high carrier mobility maintainability regardless of thickness thinning down, dangling bonds free surface and atomic thickness, which contributes to super gate electrostatic controllability. To overcome increasing power dissipation problem, new device structures including negative capacitance FET (NCFET), tunnel FET (TFET), dirac source FET (DSFET) and the like, which show superiority in decreasing VDD by lowering SS below thermionic limit of 60 mV dec−1 have been brought out. The combination of 2D materials and ultralow steep slope device structures holds great promise for low power‐dissipation electronics, which encompass both suppressed SCEs and reduced VDD simultaneously, leading to improved device performance and lowered power dissipation.

Bilayer ion trap design for 2D arrays

Junctions are fundamental elements that support qubit locomotion in two-dimensional ion trap arrays and enhance connectivity in emerging trapped-ion quantum computers. In surface ion traps they have typically been implemented by shaping radio frequency (RF) electrodes in a single plane to minimize the disturbance to the pseudopotential. However, this method introduces issues related to RF lead routing that can increase power dissipation and the likelihood of voltage breakdown. Here, we propose and simulate a novel two-layer junction design incorporating two perpendicularly rotoreflected (rotated, then reflected) linear ion traps. The traps are vertically separated, and create a trapping potential between their respective planes. The orthogonal orientation of the RF electrodes of each trap relative to the other provides perpendicular axes of confinement that can be used to realize transport in two dimensions. While this design introduces manufacturing and operating challenges, as now two separate structures have to be precisely positioned relative to each other in the vertical direction and optical access from the top is obscured, it obviates the need to route RF leads below the top surface of the trap and eliminates the pseudopotential bumps that occur in typical junctions. In this paper the stability of idealized ion transfer in the new configuration is demonstrated, both by solving the Mathieu equation analytically to identify the stable regions and by numerically modeling ion dynamics. Our novel junction layout has the potential to enhance the flexibility of microfabricated ion trap control to enable large-scale trapped-ion quantum computing.

Steep slope threshold switching field‐effect transistors based on 2D heterostructure

AbstractIn dealing with the increasing power dissipation of electronic systems with increasing integration density, a field‐effect transistor (FET) with steep switching slope that overcomes the thermionic limit is vital to achieve low‐power operations. Here, we report two types of threshold switching (TS) FETs based on 2D Van der Waals heterostructures by virtue of the abrupt resistive switching of the hexagonal boron nitride (hBN) TS device. The common hBN dielectric layer functions as the switching medium for the TS device and the gate dielectric for the 2D FET enabling seamless integration of the hBN TS device and baseline 2D FET. TS FET in source configuration by connecting the TS device to the source terminal of the 2D FET offers an ultralow average subthreshold swing (SS) of 1.6 mV/dec over six decades of drain current at room temperature and suppressed leakage current. TS FET in gate configuration by connecting the TS device to the gate terminal of the 2D FET also exhibits steep switching slope with ultralow SS of 10.6 mV/dec. The proposed compact device structures integrating 2D FET and TS device provide a potential approach of monolithic integration toward next‐generation low‐power electronics.

Research on the effects of resonance tube bending in loop thermoacoustic refrigeration system

A high-power-density heat-driven loop thermoacoustic refrigeration system has the potential to meet miniaturization requirements of vehicle waste heat recovery systems. Given the strict space constraints in vehicle power compartments and the need to reduce equipment footprint, the resonance tubes need to be bent and coiled. However, the introduction of curvature may increase losses in resonance tubes. In order to evaluate the minor losses caused by bending on resonance tubes, a double-acoustic-source driven acoustic field modulation platform was constructed to experimentally investigate bent resonance tubes with different arc lengths under two common bending angles (90° and 180°) under high working pressure. Through the acoustic field reconstruction method, the acoustic field distributions of each resonance tube were obtained, and the effects of changes in bending angle and arc length on acoustic field and acoustic power dissipation were analyzed. The results indicated that the introduction of curvature leads to an increase in traveling-standing wave ratio, acoustic power, and acoustic power dissipation, with the degree of increase influenced by both curvature and arc length. Under the same bending angle, the minor loss is directly proportional to curvature, and there is an ExpAssoc function relationship between minor loss coefficient and curvature. Under the same curvature, the minor loss is not proportional to arc length, and minor loss coefficient slightly increases with the arc length doubles. The findings fill the research gap in resonance tube bending in loop thermoacoustic systems and provide guidance for the selection of resonance tube bending parameters.

New generation B-Field and RAD-tolerant DC/DC power converter for on-detector operation

The increase in the number of readout channels in new detectors, like the Micro Pattern Gas Detectors (MPGD), in the order of several millions, requires a large amount of electrical power to supply the front-end electronics, up to hundreds kW. If this power is generated at long distances from the detector, the voltage drop on the connection cables puts serious constraints to the supply current, to the wire cross-section and to the power distribution. A large amount of voltage drop on the cables, apart an increased power dissipation on wire resistance, determines regulation issues on the load in case of current transients. To mitigate these problems, a new generation DC/DC converter, working in a heavily hostile environment and with a power density greater than 200 W/dm3, was developed. It is modular, with up to four independent modules, eight channels each, collected in a water-cooled crate, and can supply the load with an adjustable 10 to 12 V output up to 170 W per channel. In this contribution, the design constraints of such a converter are analysed, taking as a basis the environmental, electrical and mechanical requirements of the ATLAS New Small Wheel (NSW) project. Thermal considerations require the converter to be water-cooled, and the dimensional constraints impose the adoption of an innovative design to convey the dissipated heat towards the heat exchanger. The control and monitoring system allows for the full remote management of the converter. Main electrical parameters were measured and are reported. The converter was also characterized in a harsh working environment, with radiation tests in the CERN CHARM facility beyond the limits estimated for ten years operation in ATLAS, and with magnetic field tests in various orientations, using different magnets at CERN up to 1.3 T. A better common mode noise filtering design improvement was implemented after the first characterization. Final performance measurements after the modifications are also reported.

Numerical investigation of the thermo-hydraulic performance of a shark denticle-inspired plate fin heat exchanger

Growing demand for increased power dissipation is fuelling the need for the design of more efficient heat exchangers. Modifying fin geometry is an effective way of improving heat transfer efficiency and of reducing flow resistance for plate fin heat exchangers. To date, fin designs have mostly revolved around classical shapes such as pins, ellipses, and rectangles, due to limitations of conventional manufacturing technologies. However, with recent advancements in metal additive manufacturing, there is an opportunity of redesigning approaches and ways of thinking to create novel fin geometries. In this study, biomimicry was used as a tool to reverse engineer a novel geometry for a plate fin heat exchanger based on a denticle, which is a mesoscopic structure on the skin of sharks. The shape of the denticle is streamlined; therefore, showing the possibility of enhancing fluid-to-solid contact if used as geometry for a plate fin heat exchanger. The thermo-hydraulic performance of the denticle was evaluated with respect to a rectangular, cylindrical and an elliptical fin (NACA 0030), using conjugate-heat-transfer simulations on ANSYS-Fluent. The numerical model was calibrated and validated based on experimental results from an additively manufactured rectangular plate fin heat exchanger. Results demonstrated that over the range of tested Reynolds Numbers, 9.8x104 < Re ≤ 22.9x104, the denticle fin had average Nusselt number improvements of 13.1 %, 5.4 % and 75.7 % with respect to the rectangular fin, the NACA 0030 and cylindrical fin, respectively. At Re = 22.9x104, a 26 % decrease in pressure drop was noted for the denticle with respect to the rectangular fin, with maximum thermal performance factors (ƞ) of 1.29, 0.81 and 1.53 as noted for the denticle fin with respect to the rectangular fin, NACA 0030 fin and cylindrical fin, respectively.

Thermal modeling of high-power satellite power cable and analysis of bundling thermal effect

With the increase of satellite power, the current-carrying and heat dissipation of power cable is increasing significantly and the thermal safety problem becomes prominent. Therefore, the need for accurate modeling and fine design of power cable becomes increasingly urgent. In this paper, the thermal analysis modeling method for high-power cable bundle is proposed based on ground test data, and the heat transfer parameters at the installation and bundling points are obtained. At the same time, the thermal effect of cable bundling is quantitatively analyzed by simulating the splitting and binding power cable bundle. The result indicates that enhancing the radiation heat transfer between cables and the surrounding environment is the most effective means to improve the heat dissipation condition of cable bundles. The thermal model of high-power satellite power cable proposed in this paper can be used as an important basis for the prediction of on-orbit temperature and fine laying design of the power cable.

Design of SRAM Cell using Modified Lector and Dual Threshold Method Based on FINFET

FinFET (Fin Field Effect Transistor) is a new technology that satisfies the demand for a superior storage system by improving transistor circuit design (SS). CMOS devices experience a wide range of issues due to the gate's diminishing ability to control the channel. Increased total production costs are a few of these disadvantages. But this store needs to dissipate less power, have a quick access time, and a low leakage current. The increased power dissipation and leakage current of traditional CMOS-based SRAM (Static RAM) architectures cause a sharp decline in performance. The nanoscale gadget called FinFET is being introduced for use in SRAM fabrication due to its 3D gate architecture. The adoption of FinFET has helped boost overall performance in terms of efficiency, power, and footprint. And because it is immune to SCEs, FinFET has become the transistor of choice. In this study, we have examined a number of FinFET-based SRAM cells and compared them with CMOS technology. We have also suggested a novel 14T SRAM design that uses the Dual Threshold Method and Modified Lector Approach with FinFET, and it is implemented for the 1bit, 4bit, and 8bit.

Hot deformation and microstructural evolution of ultrasonically fabricated as-cast Al-7.3Zn-2.2Mg-2Cu alloy

Al-7.3Zn-2.2 Mg-2Cu alloy is known for its high strength, achieved because of higher alloying concentration. However, the higher alloying concentration presents challenges during the hot deformation process. Nevertheless, hot deformation proves to be an effective method for optimizing the microstructural and mechanical properties of the material. The research presented in the study focuses on investigating the hot working response of an ultrasonically fabricated age-hardening as-cast Al-7.3Zn-2.2 Mg-2Cu alloy. The objective is to observe the attainment of a uniform and dendrite-free microstructure after a single-step hot compression. The flow stress of the deformed specimens showed a notable increase as the temperature and deformation time decreased. This increase in stress was influenced by various factors, including deformation variables and precipitate size. The accurate prediction of the hot deformation behaviour was achieved by combining the constitutive equations and a workability map. The 3-dimensional workability map revealed a gradually increasing power dissipation efficiency (PDE) from 40% to 50% with increasing strain. At the end of 50% compression, four specific optimum working regions (PDE > 40%) were identified. Through detailed microstructural analysis, the best region for hot forging of ultrasonically mixed as-cast alloy for chemical homogeneity and upgraded property is obtained in the range of (350–450 °C) & (0.1–0.001 s−1). The highest extent of recrystallization (73%) was exhibited after deformation at 450 °C-0.001 s−1. The mechanism of dynamic softening during deformation is observed due to DRV, CDRX, and PSN. The microstructural response in 0.1–0.001 s−1 and 350–450 °C indicated dynamic recrystallization, whereas strained and non-working zone was observed at low deformation temperatures (≤350 °C).

Machine Learning Techniques to Evaluate the Approximation of Utilization Power in Circuits

The need for products that are more streamlined, more useful, and have longer battery lives is rising in today's culture. More components are being integrated onto smaller, more complex chips in order to do this. The outcome is higher total power consumption as a result of increased power dissipation brought on by dynamic and static currents in integrated circuits (ICs). For effective power planning and the precise application of power pads and strips by floor plan engineers, estimating power dissipation at an early stage is essential. With more information about the design attributes, power estimation accuracy increases. For a variety of applications, including function approximation, regularization, noisy interpolation, classification, and density estimation, they offer a coherent framework. RBFNN training is also quicker than training multi-layer perceptron networks. RBFNN learning typically comprises of a linear supervised phase for computing weights, followed by an unsupervised phase for determining the centers and widths of the Gaussian basis functions. This study investigates several learning techniques for estimating the synaptic weights, widths, and centers of RBFNNs. In this study, RBF networks—a traditional family of supervised learning algorithms—are examined. Using centers found using k-means clustering and the square norm of the network coefficients, respectively, two popular regularization techniques are examined. It is demonstrated that each of these RBF techniques are capable of being rewritten as data-dependent kernels. Due to their adaptability and quicker training time when compared to multi-layer perceptron networks, RBFNNs present a compelling option to conventional neural network models. Along with experimental data, the research offers a theoretical analysis of these techniques, indicating competitive performance and a few advantages over traditional kernel techniques in terms of adaptability (ability to take into account unlabeled data) and computing complexity. The research also discusses current achievements in using soft k-means features for image identification and other tasks.

Cluster-based test vector re-ordering for reduced power dissipation in digital circuits

Optimizing testing power is a paramount concern in modern digital circuit design, particularly as the intricacy of circuits continues to rise. This issue becomes even more pronounced with the scaling down of feature sizes due to advancements in process technology. The increase in testing power dissipation, beyond the regular operational state, raises red flags for both designers and test engineers. This paper introduces a novel cluster-based approach, shedding light on the efficient reordering of test vectors to mitigate the heightened switching activity. This technique aims to reduce the power consumption during testing, while still ensuring efficient error detection, maintaining the test period, and preserving the original order of the scan chain. Importantly, this reordering method does not introduce any additional area or test time overhead, minimizing the risks associated with these factors. The potential impact of this approach is demonstrated through concrete examples drawn from ISCAS’89 benchmark circuits. The results showcase a notable 11% reduction in switching activity, all while preserving fault coverage levels.

A Review of Techniques to Enhance an Amplifier’s Performance Using Resistive Local Common Mode Feedback

A review of some of the most common applications of the resistive local common mode feedback technique to enhance amplifier’s performance is presented. It is shown that this simple technique offers essential improvement in open loop gain, gain-bandwidth product, slew rate, common mode rejection ratio, power supply rejection ratio, etc. This is achieved without increasing power dissipation or supply voltage requirements and with small additional silicon area and circuit complexity. It is also shown that it is especially appropriate to improve amplifiers’ performance in current fine-line submicrometer CMOS technology. Some of the applications discussed are GB enhanced, class AB and super class AB operational amplifiers, gain boosted op-amps, bulk-driven circuits, sample and hold circuits and power management circuits, among others.

Performance Analysis of Various Complementary Metaloxide Semiconductor Logics for High Speed Very Large Scale Integration Circuits

The demand for VLSI low voltage high-performance low power systems are increasing significantly. Today's deviceapplications necessitate a system that consumes little power and conserves performance. Recent battery-powered lowvoltagedevices optimize power and high-speed constraints. Aside from that, there is a design constraint with burst-modetype integrated circuits for small devices to scale down. Low voltage low power static CMOS logic integrated circuitsoperate at a slower rate and cannot be used in high performance circuits. As a result, dynamic CMOS logic is used inintegrated circuits because it requires fewer transistors, has lower parasitic capacitance, is faster, and enables pipelinedsystem architecture with glitch-free circuits. It has, however, increased power dissipation. Both types of CMOS circuits withlow power dissipation overcome their own shortcomings.This paper discusses dynamic CMOS logic circuits and their structures. Various logics are also discussed and on the basisof the results obtained, logic which is best suited for designing CMOS logic circuit will be found out. The logic on the basisof structure layout and design which gives best results for high-speed VLSI circuits, is found out.

LCINDEP: a novel technique for leakage reduction in FinFET based circuits

Due to the continuous downsizing of metal oxide semi-conductor field effect transistor devices, power dissipation is one of the vital issues for the integrated circuit design. As a result of voltage scaling at lower technology nodes, threshold voltage decreases which results in increase in leakage current, hence leads to increase in leakage power dissipation. In this paper, a novel low leakage technique called LCINDEP (leakage control input DEPendent) is proposed for nano-scaled circuits. The device characteristics and hence overall performance gets affected due to increased power dissipation. Proposed LCINDEP technique is extensively demonstrated for low power operation and reliability analysis. Various short gate (SG) fin type field effect transistor (FinFET) logic circuits are simulated using LCINDEP technique and comparative analysis is performed with the already available leakage reduction techniques. The proposed LCINDEP technique provides reduced leakage power by 89.71% and 91.92% in LCINDEP SG FinFET NAND and NOR gates respectively with respect to the conventional SG FinFET NAND and NOR gates. Besides this benchmark circuits like ring oscillator and ISCAS-85 C17 show decrease in power dissipation by 24.75% and 35.5% respectively with LCINDEP technique in respect to the conventional FinFET circuits. Reliability analysis in terms of process voltage and temperature variations is performed using Monte Carlo Approach for 5000 samples, which also depicts that proposed LCINDEP technique is more reliable than the available low power techniques. The normalized standard deviations (σ/µ)% is improved by 54.68% and 43.93% for power delay product metric in the proposed technique compared to the conventional one for SG FinFET NAND and NOR gates respectively. All the simulations are performed at 16 nm technology node for FinFET logic devices using predictive technology model multigate based on BSIM-CMG on HSPICE tool.

Low Power ALU using Wave Shaping Diode Adiabatic Logic

The evolution of portable electronic devices and their widespread application has led to an increased focus on power dissipation as one of the critical parameters. An increase in functionality requirement and design complexity on a single chip has resulted in increased power dissipation. High power dissipation has motivated study and innovation on low power circuit design techniques. Adiabatic logic has been studied as one of the design techniques to reduce power dissipation by reusing the power that was getting dissipated in conventional designs. This paper presents the application of Wave Shaping Diode Adiabatic Logic (WSDAL) to implement an ALU and analyse the improvement in power dissipation as compared to the conventional CMOS design. The WSDAL design uses a slow and time-fluctuating 2-phase sinusoidal Power Clock (PC), which supplies power as well as a clock to the designs. WSDAL uses an Ultra-Low Power Diode (ULPD) structure that operates as a wave shaping device and reduces glitches at the output. The design has been implemented in OrCAD Capture and simulated using Pspice in TSMC 180nm technology. The simulations were performed at 200MHz PC frequency and power dissipation was studied over a range of voltages from 1.4V to 2.2V. The simulations show that WSDAL ALU dissipates less power than the CMOS design. This study indicates that WSDAL-based designs have the potential to be deployed for power dissipation reduction in portable devices.

A Novel Design of Symmetric Daub-4 Wavelet Filter Bank for Image Analysis

The orthogonal wavelet filter banks (FBs) consume large resources for hardware implementation due to their irrational coefficients. This results in reduction in speed of operation, huge memory requirement and increased power dissipation. In order to solve these issues, a low complex symmetric Daub-4 (8-tap) orthogonal wavelet FB is proposed in this brief. This is achieved by slightly altering the perfect reconstruction (PR) condition to make proposed FB symmetric and to obtain dyadic filter coefficients. The proposed wavelet FB is multiplier free and achieves considerably reduction in hardware and dynamic power consumption by reducing number of adders and shifters. This is verified by implementing the proposed wavelet FB on Kintex-7 field programmable gate array (FPGA) using vivado 2019.2 software from Xilinx. The proposed FB is tested for its suitability in applications such as image compression and medical image retrieval. Simulations results prove that the designed wavelet FB gives better performances in terms of PSNR for image compression and retrieval accuracy (ARP, ARR) for medical image retrieval on the benchmark images as compared to state-of-art methods.

X-ray diffraction imaging of fully packaged n-p-n transistors under accelerated ageing conditions.

X-ray diffraction imaging was used to monitor the local strains that developed around individual n-p-n bipolar transistors within fully encapsulated packages under conditions of extremely high forward bias to simulate accelerated ageing. Die warpage associated with the packaging was observed to relax systematically as the polymer became viscous due to the temperature rise associated with the dissipation of heat in the transistor. The direct image size and intensity from the individual transistors were interpreted in terms of a model in which local thermal expansion is treated as a cylindrical inclusion of distorted material, contrast arising principally from lattice tilt. The extension of the thermal strain image along the emitter with increasing power dissipation was ascribed to the effect of current crowding in the emitter region. Weaker large-area contrast associated with the base-collector region was interpreted as arising from the smaller change in effective misorientation at the high X-ray energy of thermal lattice dilation in the base region.

Toward Higher Integration Density in Femtosecond-Laser-Written Programmable Photonic Circuits.

Programmability in femtosecond-laser-written integrated circuits is commonly achieved with the implementation of thermal phase shifters. Recent work has shown how such phase shifters display significantly reduced power dissipation and thermal crosstalk with the implementation of thermal isolation structures. However, the aforementioned phase shifter technology is based on a single gold film, which poses severe limitations on integration density and circuit complexity due to intrinsic geometrical constraints. To increase the compactness, we propose two improvements to this technology. Firstly, we fabricated thermal phase shifters with a photolithography process based on two different metal films, namely (1) chromium for microheaters and (2) copper for contact pads and interconnections. Secondly, we developed a novel curved isolation trench design that, along with a state-of-the-art curvature radius, allows for a significant reduction in the optical length of integrated circuits. As a result, curved Cr-Cu phase shifters provide a compact footprint with low parasitic series resistance and no significant increase in power dissipation (∼38 mW) and thermal crosstalk (∼20%). These results pave the way toward the fabrication of femtosecond-laser-written photonic circuits with a steep increase in terms of layout complexity.

Timing performance of the Timepix4 front-end

A characterisation of the Timepix4 pixel front-end with a strong focus on timing performance is presented. Externally generated test pulses were used to probe the per-pixel time-to-digital converter (TDC) and measure the time-bin sizes by precisely controlling the test-pulse arrival time in steps of 10 ps. The results indicate that the TDC can achieve a time resolution of 60 ps, provided that a calibration is performed to compensate for frequency variation in the voltage controlled oscillators of the pixel TDCs. The internal clock distribution system of Timepix4 was used to control the arrival time of internally generated analog test pulses in steps of about 20 ps. The analog test pulse mechanism injects a controlled amount of charge directly into the analog front-end (AFE) of the pixel, and was used to measure the time resolution as a function of signal charge, independently of the TDC. It was shown that for the default configuration, the AFE time resolution in the hole-collecting mode is limited to 105 ps. However, this can be improved up to about 60 ps by increasing the preamplifier bias-current at the cost of increased power dissipation. For the electron-collecting mode, an AFE time resolution of 47 ps was measured for a bare Timepix4 device at a signal charge of 21 ke. It was observed that additional input capacitance from a bonded sensor reduces this figure to 62 ps.