Increase In On-state Resistance Research Articles

Reliable operation of Cr2O3:Mg/β-Ga2O3 p–n heterojunction diodes at 600 °C

Beta gallium oxide (β-Ga2O3)-based semiconductor heterojunctions have recently demonstrated improved performance at high voltages and elevated temperatures and are, thus, promising for applications in power electronic devices and harsh environment sensors. However, the long-term reliability of these ultra-wideband gap (UWBG) semiconductor devices remains barely addressed and may be strongly influenced by chemical reactions at the p–n heterojunction interface. Here, we experimentally demonstrate operation and evaluate the reliability of Cr2O3:Mg/β-Ga2O3 p–n heterojunction diodes during extended operation at 600 °C, as well as after 30 repeated cycles between 25 and 550 °C. The calculated pO2-temperature phase stability diagram of the Ga-Cr-O material system predicts that Ga2O3 and Cr2O3 should remain thermodynamically stable in contact with each other over a wide range of oxygen pressures and operating temperatures. The fabricated Cr2O3:Mg/β-Ga2O3 p–n heterojunction diodes show room-temperature on/off ratios >104 at ±5 V and a breakdown voltage (VBr) of −390 V. The leakage current increases with increasing temperature up to 600 °C, which is attributed to Poole–Frenkel emission with a trap barrier height of 0.19 eV. Over the course of a 140-h thermal soak at 600 °C, both the device turn-on voltage and on-state resistance increase from 1.08 V and 5.34 mΩ cm2 to 1.59 V and 7.1 mΩ cm2, respectively. This increase is attributed to the accumulation of Mg and MgO at the Cr2O3/Ga2O3 interface as observed from the time-of-flight secondary ion mass spectrometry analysis. These findings inform future design strategies of UWBG semiconductor devices for harsh environment operation and underscore the need for further reliability assessments for β-Ga2O3-based devices.

15 MeV proton damage in NiO/β-Ga2O3 vertical rectifiers

15 MeV proton irradiation of vertical geometry NiO/β-Ga2O3 heterojunction rectifiers produced reductions in reverse breakdown voltage from 4.3 kV to 3.7 kV for a fluence of 1013ions·cm−2 and 1.93 kV for 1014 ions·cm−2. The forward current density was also decreased by 1–2 orders of magnitude under these conditions, with associated increase in on-state resistance R ON. These changes are due to a reduction in carrier density and mobility in the drift region. The reverse leakage current increased by a factor of ∼2 for the higher fluence. Subsequent annealing up to 400 °C further increased reverse leakage due to deterioration of the contacts, but the initial carrier density of 2.2 × 1016 cm−3 was almost fully restored by this annealing in the lower fluence samples and by more than 50% in the 1014 cm−2 irradiated devices. Carrier removal rates in the Ga2O3 were in the range 190–1200 for the fluence range employed, similar to Schottky rectifiers without the NiO.

A Simple Edge Termination Design for Vertical GaN P-N Diodes

Vertical power devices require significant attention to their edge termination designs to obtain higher breakdown voltages without substantial increase in ON-state resistance. A simple edge termination structure for a GaN p-n diode is proposed, comprising a full layer lightly doped p-type GaN region underneath the higher doped <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p} +\!+$ </tex-math></inline-formula> contact layer. A TCAD model of the device is developed, and removal of the portions of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> ++ cap outside of the device active area in simulations is shown to increase the device blocking voltage capability. It causes the depletion width to increase in the lightly doped p-type layer and allows it to act similar to a junction termination extension (JTE). These predictions are validated empirically, resulting in a 52% measured increase in breakdown capability after selective removal of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> ++ cap. This simple edge termination technique can be formed with only a single low-energy nitrogen implant or etching procedure, greatly increasing its manufacturability over more complex structures. Design optimization studies are pursued in TCAD to determine optimal parameter values for further improving breakdown performance. It is shown that the proposed edge termination technique can be employed to produce future high voltage vertical GaN devices without a significant gain in ON-state resistance and with wide tolerance to process variations.

Early detection of photovoltaic system inverter faults

Photovoltaic (PV) systems are increasingly adopted as a source of green energy. The reliability of PV systems mainly depends on the reliability of the power MOSFETs of their inverter(s). It has been shown that short and open faults are the most frequent power MOSFET faults. They may compromise the inverter reliability, with consequent significant impact on the PV system energy efficiency. It has been proven that the likelihood of such faults is related to the value of the MOSFET ON-state resistance, which may increase over time due to aging mechanisms. When the value of such a resistance reaches a critical value, the likelihood of the MOSFETs subsequently failing as open or short becomes very high. In this paper, we first evaluate the effects of the MOSFETs' ON-state resistance increase on the harmonic components of the inverter input and output currents. Then, based on the obtained results, we propose an innovative strategy for the early detection (also referred to as condition monitoring [1]) of inverter faults, which enables to generate an alarm message when the ON-state resistance of any inverter MOSFET reaches the critical value. Upon the generation of such an alarm message, proper recovery strategies can be activated, to enable the online replacement of the affected transistors before they actually become faulty. Our detection strategy does not require to interrupt the inverter normal operation in the field and can be implemented using the microcontroller typically embedded within the control circuitry of PV systems.

Hot electron effects in AlGaN/GaN HEMTs during hard-switching events

This work contains an investigation of hot-electrons effects in GaN transistors during a hard-switching event by means of wafer-level measurements and TCAD mixed-mode hydrodynamic simulations. The latter reveals the presence of hot electrons at the passivation/barrier interface during commutation. Trapping in this location can explain the measured on-state resistance increase during switching operation and leads to a redistribution of the lateral electric field in the two-dimensional electron gas, which in return modulates the hot electron injection process.

Investigation on the Degradation Mechanism for SiC Power MOSFETs Under Repetitive Switching Stress

The degradation of electrical parameters for SiC power metal-oxide-semiconductor field-effect transistors (MOSFETs) under repetitive switching stress is investigated in detail. The dominant degradation mechanism is demonstrated to be the injection of negative charges into the gate oxide interface along the channel. It results in the increase in threshold voltage ( V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) and the increase in ON-state resistance ( R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dson</sub> ) under low gate bias condition. Furthermore, the influences of different stages during an entire switching process on the degradation trend of the device are verified. It is found that the charges are mainly injected into the gate oxide during the conduction stage. Even though the turn-on stage rarely results in the injection directly, it increases the junction temperature ( T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">j</sub> ), contributing to the injection of charges during the conduction stage. However, the turn-off stage barely degrades the performance of the device. The research also proves the robustness of SiC power MOSFETs under repetitive out-of-safe operating area (SOA) switching conditions. Moreover, the degradation of switching behaviors of the device is analyzed. The increased V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> increases the Miller plateau voltage ( V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gp</sub> ), leading to the increase in turn-on time and the decrease in turn-off time. Hence, the turn-on dissipated energy ( E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ) increases, while the turn-off dissipated energy ( E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ) decreases after enduring the stress.

Theoretical Optimization of the Si GSS-DMM Device in the BaSIC Topology for SiC Power MOSFET Short-Circuit Capability Improvement

The BaSIC(DMM) topology has been experimentally demonstrated to improve the short-circuit time for a 1.2 kV SiC power MOSFET product from 4.8 μs to 7.9 μs with a 17% increase in on-state resistance by utilizing a commercially available 100 V rated Gate-Source-Shorted (GSS) Si Depletion-Mode power MOSFET (DMM). The optimization of the Si GSS-DMM is discussed in this paper to achieve even superior performance, namely larger short-circuit time with less increase in on-resistance. It is theoretically demonstrated for the first time that a highly desirable short-circuit time of 10 μs, similar to Si IGBTs, can be achieved for two SiC power MOSFET products with less than 3% increase in on-resistance. This was accomplished by reducing the breakdown voltage rating of the Si GSS-DMM from 100 V to 30 V, altering the cell design parameters, and utilizing the trench-gate design. The theoretical analysis provided in this paper provides valuable design guidelines for manufacturers of Si GSS-DMM devices to achieve optimum performance for use in the BaSIC(DMM) topology.

Dispersion effects in on‐state resistance of lateral Ga 2 O 3 MOSFETs at 300 V switching

Static characterisation and fast switching processes of lateral β-Ga2O3 metal oxide semiconductor field-effect transistors (MOSFETs) are presented. The investigated transistors with 10 mm gate width and 6 µm gate drain distance achieve on-state resistances of 5 Ω and saturation currents above 2.4 A. Hard switching in a double pulse test setup with an inductive load results in voltage slopes up to 65 V/ns at 300 V input voltage. After longer blocking times and higher DC voltages, a strong dynamic increase in on-state resistance occurs. Switching with an ohmic load and different load currents reveals only minor influence of the hot electron mechanism during the hard turn on. However, a clear influence of the turn-on gate drive voltage on the dynamic increase is observed, indicating a shift of the transfer characteristic due to charge trapping in the gate region.

Investigation on the degradation indicators of short-circuit tests in 1.2 kV SiC MOSFET power modules

This paper provides a comprehensive investigation on both static characteristics and short-circuit performance of 1.2 kV SiC MOSFET power modules with 2nd generation planar technology. The experimental approach is based on the static characteristics measurements and the short-circuit tests with gradual increase of pulse time duration. If any variation of the static characteristics appears, the time duration of next short-circuit tests would keep the same with the last pulse duration (approach 1) or increase continuously (approach 2). The results of the short-circuit waveforms show a gate degradation which is further confirmed with the measurement of the gate leakage current. Additionally, other degradation indicators, including positive shift of threshold voltage, drain leakage current and on-state resistance increase are evidenced and discussed in this paper. These can be used for early prediction of the degradation and failure in the short-circuit conditions.

Effect of short circuit aging on safe operating area of SiC MOSFET

In this paper, we study the effect of aging of SIC MOSFETs on Short Circuit Safe Operating Area and Reverse Bias Safe Operating Area of SiC MOSFETs. SCSOA and RBSOA are determined using short circuit and unclamped inductive switching tests, respectively. Aging of SiC MOSFETs are performed with repetitive short circuit tests at low dissipated energies, which allows to validate the relevance of evolution of different aging indicators measured during the aging process. The decrease in the dissipated energy leading to failure in short circuit and unclamped inductive switching tests allows to clearly link the evolution of these Safe Operating Areas to the degradation of electrical performances (drain and gate leakage currents and on-state resistance). Obtained results show that a strong increase in the drain and/or gate leakage currents after aging has a great effect on the decrease of Safe Operating Area especially on RBSOA and that on-state resistance increase due to aging process represents less impacts in the evolution of RBSOA than in the case of SCSOA. It is also clear from the obtained results that without any apparent evolution of these leakage currents, the decrease of SCSOA after aging is related to the increase in the on-state resistance.

Electron and Proton Irradiation Damage in β-Ga2O3 Vertical Rectifiers

Wide bandgap semiconductors materials have always been the interest of their ability that can withstand high radiation fluences for the military, nuclear-industry monitoring, satellites and other space-borne applications. Monoclinic β phase Ga2O3 is attracting great attention for power electronics and solar-blind photodetectors because of its large bandgap (~4.9 eV) and a critical electric field strength of 8 MV/cm.[1,2,3] Also, the large diameter bulk β- Ga2O3 is commercially available with a controllable n-type doping for its epitaxial layers. Given its high bond strength and expected high vacancy formation energy, β- Ga2O3 is likely to be very radiation hard based on the reduced density of atomic displacements expected for a given energy of non-ionizing radiation exposure.[4] The cosmic rays, trapped radiation in the Earth’s radiation belts, and solar particle events are three primary sources of space irradiation. The cosmic rays consist predominantly of protons; the radiation belts contain energetic protons and electrons while solar particle events are mostly lower energy protons and electrons, in which the average integral proton fluxes at 10 MeV are of order 1014 cm-2.[1] Thus, it is important to understand the effect of energetic proton irradiation on Ga2O3. For electron irradiation, vertical rectifiers fabricated on epi Ga2O3 (Si-doped, 10 μm) on bulk (001) β- Ga2O3 substrate (Sn-doped, 650 μm) with Ti/Au as the ohmic contact for the full back area and Ni/Au for Schottky contacts in the front. The rectifiers were subject to 1.5 MeV electron irradiation at fluences from 1.79 × 1015 to 1.43 × 1016 cm-2 at a fixed beam current of 10-3 A. The electron irradiation caused a reduction in carrier concentration in the epi Ga2O3, with a carrier removal rate of 4.9 cm-1. The electron-induced damage would cause the 2kT region of the forward current-voltage characteristics increase. For the highest electron fluence, the diode ideality factor increased around 8% along with two orders of magnitude increase in on-state resistance. There was a significant reduction in reverse bias current that scaled with electron fluence. The diode on/off ratio was measured when switching from +1 V to -40 V. At -10 V reverse bias voltage, the on/off ratio was severely degraded by electron irradiation, decreasing from ~107 in the reference diodes to ~2 × 103 for the 1.43 × 1016 cm-2 fluence. The reverse recovery characteristics showed little changes even at the highest fluence, with the reverse recovery time in the range 21-25 nsec for all rectifiers. This phenomenon can be explained by the short minority carrier lifetime. which controls the carrier storage time in Ga2O3 intrinsic layer.[3] Also, based on the diode on/off ratio, the primary cause of the degradation was introduced by the reduction of majority carrier concentration. Regarding proton irradiation, β- Ga2O3 vertical rectifiers were subject to 10 MeV proton irradiation at a fixed fluence of 1014 cm-2. The electrical performance of vertical rectifiers was measured before and after proton irradiation, as well as subsequent annealing up to 450°C. The carrier removal rate was determined to be 235.7 cm-1, which is comparable to the carrier removal rate for GaN-based heterostructures under the same proton energy. Point defects introduced by the proton damage create trap states that reduce the carrier concentration in the Ga2O3. Even annealing at 300°C produces a recovery of approximately half of the carriers in the Ga2O3, while annealing at 450°C almost restores the reverse breakdown voltage. The diode on/off ratio of the rectifiers switched from +1 V to -40 V. The diode on/off ratio was severely degraded by proton irradiation and this was only partially recovered by 450°C annealing. The minority carrier diffusion length decreased from ~340 nm for the reference diode to ~315 nm after the proton irradiation. R. Benton and E. V. Benton, Nucl. Instr. and Meth. in Phys. Res. B 184, 255 (2001).Higashiwaki, K. Sasaki, H. Murakami, Y. Kumagai, A. Koukitu, A. Kuramata, T. Masui and S. Yamakosh, Semicond. Sci. Technol., 31, 034001 (2016).Higashiwaki, K. Sasaki, A. Kuramata, T. Masui and S. Yamakoshi, Appl. Phys. Lett., 100, 013504 (2012).I. Stepanov, V.I. Nikolaev, V. E. Bougrov and A.E. Romanov, Rev. Adv. Mater. Sci., 44, 63 (2016). Figure 1

1.5 MeV electron irradiation damage in β-Ga2O3 vertical rectifiers

Vertical rectifiers fabricated on epi Ga2O3 on bulk β-Ga2O3 were subject to 1.5 MeV electron irradiation at fluences from 1.79 × 1015 to 1.43 × 1016 cm−2 at a fixed beam current of 10−3 A. The electron irradiation caused a reduction in carrier concentration in the epi Ga2O3, with a carrier removal rate of 4.9 cm−1. The 2 kT region of the forward current–voltage characteristics increased due to electron-induced damage, with an increase in diode ideality factor of ∼8% at the highest fluence and a more than 2 order of magnitude increase in on-state resistance. There was a significant reduction in reverse bias current, which scaled with electron fluence. The on/off ratio at −10 V reverse bias voltage was severely degraded by electron irradiation, decreasing from ∼107 in the reference diodes to ∼2 × 104 for the 1.43 × 1016 cm−2 fluence. The reverse recovery characteristics showed little change even at the highest fluence, with values in the range of 21–25 ns for all rectifiers.

Degradation and Reliability of Bare Dies Operated up to 300°C

In this paper, we demonstrate the degradation of commercially available 1.2kV SiC MOSFET bare dies subjected to long periods of isothermal heating at 300°C in air. Periodic electrical measurements indicated an increase in on-state resistance to different extents for three different vendor designs, and the discovery of a progressive rectifying type forward characteristic at low drain-source voltages. Subsequent investigations to determine the cause of the degraded electrical characteristics including sectioning and SEM/TEM analysis revealed some mechanical degradation within the device gate-source cross-sections and backside drain contact metal layers. While one vendor device was severely degraded after approximately 24 hours of heating, another vendor device was only just beginning to degrade after 100 hours, indicating that these devices may be used successfully in real applications at 300°C junction temperatures for relatively long periods.

Saturation Current and On-Resistance Correlation during During Repetitive Short-Circuit Conditions on SiC JFET Transistors

This letter presents a correlation between the reduction of the saturation current level and increase of on-state resistance and the top-metal ageing of normally ON SiC junction gate field effecttransistors. For this study, ageing has been obtained using repetitive short-circuit operations. Among monitored parameters during ageing, on-state resistance and short-circuit current level are those, which have the strongest evolution. The top-metal degradation has been characterized via the on-state resistance measurement during ageing. In particular, we clearly show that the top-metal restructuration due to ageing leads to an additional voltage drop between gate and source terminals and results to a lower gate-source junction voltage.

Analysis of the Degradation of MOSFETs in Switching Mode Power Supply by Characterizing Source Oscillator Signals

Switching Mode Power Supply (SMPS) has been widely applied in aeronautics, nuclear power, high-speed railways, and other areas related to national strategy and security. The degradation of MOSFET occupies a dominant position in the key factors affecting the reliability of SMPS. MOSFETs are used as low-voltage switches to regulate the DC voltage in SMPS. The studies have shown that die-attach degradation leads to an increase in on-state resistance due to its dependence on junction temperature. On-state resistance is the key indicator of the health of MOSFETs. In this paper, an online real-time method is presented for predicting the degradation of MOSFETs. First, the relationship between an oscillator signal of source and on-state resistance is introduced. Because oscillator signals change when they age, a feature is proposed to capture these changes and use them as indicators of the state of health of MOSFETs. A platform for testing characterizations is then established to monitor oscillator signals of source. Changes in oscillator signal measurement were observed with aged on-state resistance as a result of die-attach degradation. The experimental results demonstrate that the method is efficient. This study will enable a method to predict the failure of MOSFETs to be developed.

Reliability of Repetitively Avalanched Wire-Bonded Low-Voltage Discrete Power Trench n-MOSFETs

This paper, for the first time, investigates the reliability of wire-bonded low-voltage discrete power trench n-MOSFETs that have been subjected to repetitive unclamped inductive switching (RUIS). Automotive MOSFETs driving inductive loads may be subjected to RUIS; hence, there is a need to characterize the failure mechanisms in such applications. The failure mechanisms of repetitively avalanched wire-bonded MOSFETs are shown to be wire-bond lift-off and source metal degradation/fatigue due to thermomechanical stress cycling. Temperature excursions from avalanche pulses cause thermomechanical stresses on the wire-bond/source-metal interface as a result of differences in thermal expansion coefficients between silicon and aluminum. Trench MOSFETs exhibited an average of 10% increase in on-state resistance due to source metal fatigue after 100 million cycles of repetitive avalanche. The number of cycles to failure is investigated as a function of the avalanched induced temperature changes and is shown to follow the Coffin-Manson law. These results are important for designers of automotive systems since they are capable of predicting the long-term reliability of wire-bonded discrete power semiconductor components.

A numerical study of field plate configurations in RF SOI LDMOS transistors

The effect of the source field plate architecture on the static and dynamic electrical performances of SOI LDMOS transistors for RF applications is analysed in this paper. Three architectures are envisaged: source field plate SFP, extended gate field plate and independently biased field plate. Moreover, two different drift diffusion profiles are considered: shallow SDD and deep doped DDD diffusion. The resultant drift region is analytically modelled and the impact of geometrical and technological parameters on the transconductance value is determined by means of numerical simulation techniques. Finally, the dependence of the LDMOS capacitances on the field plate configuration is also studied. Simulation results show the trade-off between reliability and transconductance in each field plate configuration. In spite of the power efficiency improvement, the field plate biasing can significantly degrade the SOI LDMOS performances due to hot-carrier and self-heating effects. On the contrary, the SFP configuration leads to an enhanced reliability at the cost of the on-state resistance increase. The SFP structure with deep doped drift (DDD) diffusion provides the best performances in terms of cut-off frequency and self-heating degradation.