This paper proposes device geometry of Fin-Field-Effect-Transistor (FinFET) with a step-fin. The source region of the proposed device consists of Si1−xGexand the effects of Ge-mole fraction on various electrical parameters are premeditated. The values of electron mobility, drive current, transconductance increases, and short channel effects (SCEs) decreases as the percentage of Ge in Si1−xGexincreases. However, the energy bandgap and gate capacitance reduce with the increase of Ge mole fraction in Si1−xGex. A minimum SS being 64.77 mV/decade, lower DIBL of 35.31 mV/V, and low value of threshold voltage 0.26793 V are obtained for Lg = 40 nm at Ge mole fraction (x) = 1. A better Ion/Ioff ratio of 3.11×108 is achieved for Lg = 40 nm at mole fraction (x) = 0.3 and VDS = 0.5 V. Complementary versions of the proposed device are used in the circuit of a digital inverter (VDD = 0.5 V), and the impact of Ge content on DC and transient analysis are observed. As Ge mole fractions increases, average gate delay decreases, high noise margin (NMH) increases, and low noise margin (NML) falls off. A minimum value of average gate delay 0.9 ps, has been achieved for Lg = 40 nm at Ge content (x)= 0.2.
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