Increase In Junction Temperature Research Articles

A Thermal Impedance Model for IGBT Modules Considering the Nonlinear Thermal Characteristics of Chips and Ceramic Materials

The traditional method of calculating junction temperature does not consider the dependence of a material’s thermal conductivity on temperature, in which the thermal conductivity changes with temperature. However, with an increase in junction temperature, the temperature sensitivity (TS) will have a more significant impact on the actual temperature of chips. This study established an improved IGBT equivalent thermal impedance model that considers the nonlinear characteristics of the TS of chips and ceramic materials. The Fourier series analysis method was used to obtain the heat flux density curve, and then the heat diffusion angles of each layer were solved. Moreover, iterations were performed until the thermal conductivity and temperature of the chip and ceramic layers matched the nonlinear characteristics of the TS. When the power loss was less than 200 W, the maximum error of the junction temperature calculated by the proposed method considering TS was 3%, while the maximum error of the method without considering TS was 9.5%. Compared with the finite element simulation, the proposed method has a faster solving speed and high accuracy. The proposed method only requires the input material parameters, size parameters, and boundary conditions to solve the junction temperature, which has strong practicality and high accuracy.

The Thermal Performance of The Plate-fin Heat Sink under Natural Convection at Different Power Levels and Ambient Temperatures

The thermal performance of a flat heat sink and a plate-fin heat sink was experimentally compared under natural convection conditions at thermal powers of 16.5 W and 33 W and ambient temperatures of 30°C and 40°C. For the same heating powers, surface and junction temperatures increased as the ambient temperature rose from 30°C to 40°C, but the increase was not as much as the ambient temperature change. For the flat heat sink, the increase in junction temperature was 5°C at 16.5 W and 6.68°C at 33 W. For the plate-fin heat sink, the increase in junction temperature was 3.55°C at 16.5 W and 4.47°C at 33 W. The increase in surface temperature for the flat heat sink was 5.35°C at 16.5 W and 5.91°C at 33 W, while for the plate-fin heat sink, the surface temperature increase was 4.76°C at 16.5 W and 2.22°C at 33 W. The thermal resistance of the flat heat sink was around 4 K/W, while for the plate-fin heat sink, it ranged between 2-2.5 K/W, providing approximately twice the advantage in thermal resistance for the plate-fin model compared to the flat model. Under all conditions, the Rayleigh number (Ra) significantly decreased with the increase in ambient temperature but increased with the applied thermal power. Thus, the increase in Rayleigh number with power was more pronounced in the plate-fin model, indicating a more significant effect. In the plate-fin model, the fin efficiency slightly decreased with the increase in ambient temperature, from 0.63 to 0.62 at 16.5 W and from 0.65 to 0.64 at 33 W.

Size and temperature effects on optoelectronic properties of Micro-LED arrays for display applications

In recent years, Micro-light-emitting diode (Micro-LED) has attracted much attention in the display field, because it provides the possibility of high pixel density, etc. The implementation of high pixel density is accompanied by the reduction of size, during which the performance degradation caused by sidewall defects gradually increases. At the same time, the increase in power density and difficulty in heat dissipation caused by high pixel density can also lead to poor thermal management, resulting in an increase in junction temperature, thus affecting the display effect. In this paper, we prepared seven different sizes of Micro-LED and studied the influence of size and temperature effects on the optoelectronic properties. Smaller-sized Micro-LED could withstand higher current densities because it was not affected by the current crowding effect. However, it tends to have a larger series resistance (RS) and a lower external quantum efficiency (EQE) due to sidewall defects created during etching. The luminance of the 100 μm and 7 μm Micro-LED was 340000 cd/m2 (at 83 A/cm2) and 32000 cd/m2 (at 773 A/cm2), respectively. The peak EQE of 100 μm Micro-LED was 16.87 %. On this basis, the temperature-dependence of the optoelectronic properties of 10 μm and 50 μm Micro-LED were studied. The larger the size of Micro-LED, the better the operational stability it exhibited. From the room temperature (RT) rose to 100 ℃, the EQE of the 10 μm and 50 μm Micro-LED decreased by 16 % and 13.1 %, respectively. These experimental results provide important data for the design and preparation of Micro-LED of different sizes and for exploring the operational stability at high temperatures.

Investigations into the robustness of the peak turn-on current slope method for junction temperature sensing in p-GaN HEMTs

Abstract In this paper, the robustness of a junction temperature sensing method using the peak of the turn-on current slope for enhanced p-GaN high-electron-mobility transistors is investigated in detail. With the help of a repetitive hard-switching test platform, compared to other temperature-sensitive electrical parameters, it is found that the maximum slope of the flowing current at the turn-on transition shows no trend in degradation, regardless of the applied switching stress. This parameter decreases solely with the increase in junction temperature, showing excellent temperature-dependent linearity. Furthermore, the applicability of this method to the detection of junction temperature under different external gate resistances and drain voltages is verified. The sensed junction temperatures are carried over to calculate the thermal resistance, which is also extracted by advanced thermal characterization test equipment as a reference. Therefore, based on the versatility, convenience and accuracy, the peak of the rising drain current slope has been proven to be the preferred alternative in system applications to detect junction temperatures.

Interface Contact Thermal Resistance of Die Attach in High-Power Laser Diode Packages

The reliability of packaged laser diodes is heavily dependent on the quality of the die attach. Even a small void or delamination may result in a sudden increase in junction temperature, eventually leading to failure of the operation. The contact thermal resistance at the interface between the die attach and the heat sink plays a critical role in thermal management of high-power laser diode packages. This paper focuses on the investigation of interface contact thermal resistance of the die attach using thermal transient analysis. The structure function of the heat flow path in the T3ster thermal resistance testing experiment is utilized. By analyzing the structure function of the transient thermal characteristics, it was determined that interface thermal resistance between the chip and solder was 0.38 K/W, while the resistance between solder and heat sink was 0.36 K/W. The simulation and measurement results showed excellent agreement, indicating that it is possible to accurately predict the interface contact area of the die attach in the F-mount packaged single emitter laser diode. Additionally, the proportion of interface contact thermal resistance in the total package thermal resistance can be used to evaluate the quality of the die attach.

The effects of input power and ambient temperature on the thermal performance of conical pin fin heat sink in natural convection

In the present study, thermal performance tests of horizontally oriented HSconical, HScross-cut, and HSflat with a base plate dimensions of 80*80*5 mm3 were performed in natural convection. The effects of ambient temperature (30 and 40 °C), input power (16.5 and 33 W), and conical pin fin geometry on the thermal performance of the HSs were investigated. The thermal resistance of the heat sinks decreases while the convective heat transfer coefficient, average surface temperature, and average junction temperature increase with increasing ambient temperature and input power. However, the Nusselt number increases with increasing ambient temperature for all HSs at 16.5 W, while the Nusselt number decreases with increasing ambient temperature at 33 W. The highest convective heat transfer coefficients are 32.17, 30.68, and 19.61 W/m2K for HSconical, HSflat, and HScross-cut at 33 W and 40 °C, respectively. The lowest thermal resistances are 2.75, 2.80, and 3.81 K/W for HSconical, HScross-cut, and HSflat at 33 W and 40 °C, respectively. Thermal resistances of HSconical and HScross-cut decreased by 27.78 % and 26.44 % at maximum and 27.06 % and 24.58 at minimum, respectively, compared to HSflat. The results show that the conical fins have better thermal performance in natural convection.

Enhanced asymmetrical modulation for half‐bridge series resonant inverters in induction heating applications

AbstractThis paper presents a method that improves the reliability of half‐bridge (HB) series resonant inverters (SRI) for high‐frequency induction heating applications. Many industrial processes, like induction heat treatments, are very repetitive. This cyclical operation represents a strong limitation of the inverter's reliability, mainly due to the accelerated stress of the power semiconductors. This method consists in an enhanced asymmetrical pulse width modulation (EAPWM) that allows distributing the losses across the components, thereby reducing the cyclic increase in junction temperature of the power devices, and thus achieves a reliability that is more than twice as high as that achieved using traditional modulation methods. The work methodology includes a theoretical study of the HB inverter and a complete analysis of losses. The presented design rules have been used to implement a 25 kW, 100 kHz inverter. The use of silicon carbide (SiC) MOSFET transistors allows reaching an efficiency greater than 99%. The analytical results obtained have been experimentally validated by testing the inverter on an induction heating test bench.

A Reliability-Optimized Maximum Power Point Tracking Algorithm Utilizing Neural Networks for Long-Term Lifetime Prediction for Photovoltaic Power Converters

The reliability of power converters in photovoltaic systems is critical to the overall system reliability. This paper proposes a novel active thermal-controlled algorithm that aims to reduce the rate of junction temperature increase, therefore, increasing the reliability of the device. The algorithm works alongside a normal perturb and observe maximum power point tracking algorithm, taking control when certain temperature criteria are met. In conjunction with a neural network, the algorithm is applied to long-term real mission profile data. This would grant a better understanding of the real-world trade-offs between energy generated and lifetime improvement when using the proposed algorithm, as well as shortening study cycle times. The neural network, when applied to 365 days of data, was 28 times faster than using standard electrothermal modeling, and the lifetime consumption was predicted with greater than 96.5% accuracy. Energy generated was predicted with greater than 99.5% accuracy. The proposed algorithm resulted in a 3.3% reduction in lifetime consumption with a 1.0% reduction in the total energy generated. There is a demonstrated trade-off between lifetime consumption reduction and energy-generated reduction. The results are also split by environmental conditions. Under very variable conditions, the algorithm resulted in a 4.4% reduction in lifetime consumption with a 1.4% reduction in the total energy generated.

Delta-CHB Statcom with Reduced Capacitance Through Third Harmonic Injection

This work investigates the third harmonic circulating current injection in delta-connected Cascaded H-Bridge (Delta-CHB) STATCOM, aiming the cell capacitance volume reduction. Firstly, analytical expressions for capacitor voltage ripple are derived without and with third harmonic injection. These expressions are used to obtain the third harmonic current waveform which minimizes the sum of capacitor voltages ripple in the whole operation range. These expressions are validated in an experimental setup based on 620 VA/220 V cell. Although this approach minimizes the ripple, an increase in the semiconductors current effort is expected. This paper quantifies the increase through analytical expressions and proposes an improved third-harmonic injection scheme which injects the third harmonic in a range of operating points. The performance of the proposed strategy is evaluated for a 17 MVA/13.8 kV Delta-CHB STATCOM with 24 cells per cluster. The results indicate a reduction of 17.2% in the theoretical cell capacitance. A physical realization of cell capacitor reveals that the proposed scheme, in the best scenario, reduces the volume in 25%. Finally, if the same power module and heatsink are employed, the proposed scheme leads to an increase in junction temperature of 13◦C for IGBT and diode.

100 kA/10 kV thyristor stack design for the quench protection system in CRAFT

Thyristors have longer lifetimes, higher reliability, and very high voltage and current ratings and they require less maintenance than other high-power semiconductor devices. As a result, they are particularly suitable for quench protection systems (QPSs), which protect the superconducting magnets in large fusion devices from damage. In this paper, we propose a design for a 100 kA/10 kV thyristor stack supported by both theoretical and simulation-based analyses as well as experimental verification. Due to the ultrahigh electrical performance requirements imposed on the QPS by the Comprehensive Research Facility for Fusion Technology (CRAFT), three main issues must be considered: the voltage-balancing problem caused by multiple thyristors in a series structure, the increased junction temperature problem caused by extremely high currents, and the reverse recovery phenomenon that arises from the thyristor’s physical structure. Hence, a series of detailed theoretical analyses, simulations, and experiments, including a thyristor junction temperature prediction method and reverse recovery process modeling, were carried out to optimize the design. Finally, the reliability and stability of the thyristor stack were verified by a series of prototype experiments. The results confirmed the correctness and accuracy of the proposed thyristor stack design method and also indicated that the proposed thyristor stack can meet the application conditions of a 100 kA QPS in the CRAFT project.

Thermal Management of LEDs Packages Within Inclined Enclosures for Lighting Applications

LED lighting still suffers from its thermal problem linked mainly to the increase in junction temperature. The situation becomes more and more aggravated when it comes to decorative lighting. Indeed, this type of lighting application sometimes requires that the heat sink of the LED lamp be integrated into a narrow space, such as false or sloped ceilings, which limits the transfer of heat to the outside. In this article, the current study reports a numerical analysis of natural convection heat transfer around rectangular heat sink for LEDs lighting applications. The radiator is put in an inclined cavity with an orientation angle varying from 0° to 60°. The effects of the enclosure inclination and its length on thermal behavior, flow structure in the cavity as well as on optical properties of the light source were highlighted. The CFD simulation showed a significant effect on the heat transfer rate when varying the cavity length (presented as an aspect ratio <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">A</i> ) and its orientation. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">A</i> = 4 was determined as an optimal cavity aspect ratio, and it was found that higher orientations are more sensitive to the increase of the length of the cavity. For <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">θ</i> = 60°, the luminous efficiency is ameliorated by about 10% when increasing the cavity length from one to four. Accordingly, we proposed correlations in simple form to predict the heat transfer rate for different configurations studied.

Simplified methods for characterizing thermal parameters of high-power automotive LEDs

This study outlines a new methodology for experimental determination of the key parameters required for designing LED thermal management hardware, using a case study of the Nichia NC5W093AT Light Emitting Diode (LED), a light used in automotive headlamps. The method provides the junction temperature, the efficiency, and the package thermal resistance of the LED. For the studied LED, it was found that efficiency decreased from 36% to 25% with increasing junction temperature from 30°C to 120°C; efficiency was also insensitive to supply current. The thermal resistance, which spanned from the LED junction to the copper base, was determined to be 3.2 K/W and was insensitive to supply current and operating temperature.

Toward Class AAA LED Large Scale Solar Simulator With Active Cooling System for PV Module Tests

Solar simulators are significant in testing solar cells and photovoltaic (PV) modules since they provide spectrum and optic characteristics close to natural sunlight. This research introduces two fundamental novelties to the literature on light-emitting diode (LED) light source solar simulators. One of these innovations is designing and developing a solar simulator to achieve <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I-V</i> characterization on a PV module basis instead of cell-based contrary to the previous studies. For this purpose, a unique board with a modular structure is designed on which the LEDs are positioned. In the research, LEDs of at six different wavelengths are used. Spectral match, spatial nonuniformity, and temporal instability performance criteria tests conducted on the illuminated area is performed based on IEC 60904-9 and ASTM 927E-10 standards. Class AAA was obtained according to the large-scale solar simulator standard specified in ASTM 927E-10. The second novelty the study introduces is developing an active cooling system that can prevent an increase in LED junction temperature when the number of LEDs increases in an LED solar simulator with a wide illuminated area. In addition to the fans, this solution is suggested to prevent any damage to the LEDs during the test, as well as high temperatures from affecting the wavelengths and at the same time achieve 25 °C, one of the standard test conditions. Also, the device dimensions are optimized ergonomically for ease of use. With this system designed and devised, it becomes possible to test commercially available PV modules successfully. The active cooling system minimizes the heating problem and the impact of wavelengths that might invalidate performance criteria classes.

Implementation and characterisation of a sterilisation module consisting of novel 265 nm UVC LED packages

To efficiently fight against the COVID-19 pandemic, a sterilisation module using 265 nm UVC LED packages was developed. In this paper, the performance of the sterilisation module in terms of irradiance uniformity, junction temperature increase and sterilisation efficiency were characterised. The irradiance uniformity fluctuation across the four corners and the centre point in a 130 mm × 130 mm area was below 10%, exhibiting good uniformity. Uniform irradiance was important to achieve consistent sterilisation, which was the primary difference between the UVC LED package developed and commercial UVC LED packages. Key to achieving uniform irradiance was the structure, consisting of a stacked silicon reflector and a secondary optical lens designed by ray tracing simulation. The junction temperature increase of the 265 nm UVC LED package driving at 200 mA was only 28°C, sufficiently low to exhibit better reliability and performance. A 99.99% sterilisation efficiency on E. coli bacteria was achieved within one minute with UV dosage of 2.7 mJ/cm2 at 200 mA driving current. From the results, the novel 265 nm UVC LED package was a time-efficient solution for disinfection purposes.

A new technique to check the correct mounting of the power module heatsinks

Temperature management is a non-secondary aspect in the design of power circuits and systems. As a matter of facts, changes in the junction temperature have significant effects on the semiconductor device behavior; furthermore, a high junction temperature accelerates the failure mechanisms of power devices used in the power module and reduces their lifetime. Therefore, it is often necessary to introduce a suitable heat dissipation system able to keep the junction temperature within the device operating limits. Passive heatsinks represent the most widely used strategy. However, an incorrect mounting of the heatsink may cause an unacceptable junction temperature increase in a power module. Even though the heatsink was initially properly assembled, it may be affected by defects during its working lifetime. Thus, it is necessary to devise effective strategies for testing the heatsink mounting at the end of the printed circuit board production and during the operational phase. In this paper, a method to test the heatsink mounting on power module is discussed. The proposed solution does not require thermal measurements, but only electrical ones and can be performed both at the end of the power module production, by means of an automatic test equipment, and in mission using a dedicated test circuit included in the system. The method was experimentally assessed on a DC-DC buck converter, validating the proposed solution.

Repetitive short circuit capability of SiC MOSFET at specific low gate-source voltage bias for more robust extreme operation

This paper presents short-circuit (SC) performance of a commercial silicon-carbide (SiC) MOSFET device under repetitive SC stress at high drain source voltage. Two protocols are investigated to evaluate the impact of gate-source voltage (VGS) depolarization and SC duration (TSC) reduction. The VGS depolarisation provides a power density reduction and allows to preserve a secure failure mode (FTO: Fail To Open) with an increase of the short circuit duration TSCmax. The results demonstrate that SiC MOSFET VGS depolarization does not reduce SC cycling capability at TSCmax. However, using VGS depolarization allows to get performance close to IGBT robustness levels with almost 1000 cycles @TSC = 10 μs. The simulation of the chip temperature evolution during SC tests suggests that the degradations stay attributed to the increase of junction temperature (TJ) during the SC cycles, which leads to the fusion of the top Al inducing cracks into the thick oxide.

A Double-Side Cooled SiC MOSFET Power Module With Sintered-Silver Interposers: I-Design, Simulation, Fabrication, and Performance Characterization

Planar, double-side cooled power modules are emerging in electric-drive inverters because of their low profile, better heat extraction, and lower package parasitic inductances. However, there is still a concern about their reliability due to the rigid interconnection between the device chips and two substrates of the power module. In this article, a porous interposer made of low-temperature sintered silver is introduced to reduce the thermomechanical stresses in the module. A double-side cooled half-bridge module consisting of two 1200 V, 149 A SiC MOSFETs was designed, fabricated, and characterized. By using the sintered-Ag instead of solid copper interposers, our simulation results showed that, at a total power loss of 200 W, the thermomechanical stress at the most vulnerable interfaces (interposer-attach layer) was reduced by 42% and in the SiC MOSFET by 50% with a tradeoff of only 3.6% increase in junction temperature. The sintered-Ag interposers were readily fabricated into the desired dimensions without postmachining and did not require any surface finishing for die bonding and substrate interconnection by silver sintering. The porous interposers were also deformable under a low force or pressure, which helped to accommodate chip thickness and/or substrate-to-substrate gap variations in the planar module structure, thus simplifying module fabrication. The experimental results on the electrical performance of the fabricated SiC modules validated the success of using the porous silver interposers for fabricating planar, double-side cooled power modules.

LED 광원의 열-전기-광학 특성 관계와 최대 광선속 변화에 관한 연구

Optical power of an LED light source is directly affected by temperature. To understand and solve the degradation of light output and light efficiency due to heat generation in an LED, the relationship among thermal, electrical, and optical properties of the LED should preliminarily be investigated. This study aims to reveal the thermal, electrical, and optical relations of a single-chip LED light source and the conditions of its maximum luminous flux. First, the thermal, electrical, and optical relations based on the energy conservation law are derived to propose a dynamic multi-physical model of the LED light source. Then, the luminous efficacy, relative rate of luminous efficacy reduction with increasing junction temperature, thermal resistance of the LED junction, and heat dissipation coefficient of the LED are obtained based on its specifications and the experimental results. These parameters are implemented in the proposed model using Matlab software. Simulation results show the relationship between the power consumption of the LED and its relative luminous flux based on a quadratic function. The variations of the maximum luminous flux according to the change in the thermal resistance and power consumption of the lighting system are observed. Finally, considerations that should be taken into account to obtain the maximum luminous flux from a lighting system are discussed. This study will be helpful to design a lighting fixture using LED light sources.

Reduced dislocation growth leads to long lifetime InAs quantum dot lasers on silicon at high temperatures

We describe the effectiveness of filter layers, which displace misfit dislocation (MD) formation away from the active region, in improving high temperature reliability of epitaxially integrated InAs quantum dot lasers on on-axis silicon substrates. We find that inserting these “trapping layer (TL)” filters at either 80 nm or 180 nm from the active region substantially reduces device degradation at 60 °C. After 3000 h of continuous operation, the best trapping-layer-free device shows a 55% increase in threshold current while the best trapping layer (TL) devices each show less than a 9% increase. We explain these findings by correlating changes in individual device performance to changes in misfit dislocation (MD) structure. All MDs in devices without TLs show evidence of recombination enhanced dislocation climb (REDC); in contrast, adding trapping layers at 180 nm or 80 nm reduces the fraction of electrically active MDs to 9% and 1%, respectively. Reliability data after 3000 hours suggest that incorporating trapping layers a shorter distance from the active region (80 nm) is more effective than incorporating these layers further away. We conclude by identifying the mutually and self-reinforcing failure processes associated with REDC that TLs significantly remediate: increasing dislocation line length, increasing point defect densities, and increasing junction temperature. Overall, understanding and controlling crystal defects continues to be the most impactful avenue toward integrating light sources on photonic integrated circuits and closing the gap with native-substrate lasers.

Effect of Solder Particle Size on the Mechanical and Thermal Reliability of Au/Sn Ag Cu/Cu Solder Joints

This paper investigates the effect of solders with different grain sizes (5–15 μm, 2–15 μm, 2–11 μm) on the mechanical and thermal reliability of flip-chip LED chip Au/Sn Ag Cu/Cu solder joints during reflow soldering. The lead-free solder SAC305 was selected as the solder. The microstructure of the IMC interface and the inferred surface of the solder joint is observed, and the microstructure evolution of the solder joint is analyzed. The void ratio of the solder joints under different grain sizes is tested to characterize the influence of the contact area between the chip and the solder joints on the shear stress. In addition, the solder joints were aged for 1000 h under a relative humidity of 85 °C/85%. The photoelectric thermal performance of the FC-LED filament and the influence of high temperature and high humidity aging on the reliability of the filament were tested and analyzed. The results show that when the size of the solder paste is small and the uniformity is poor within a certain range of solder size, the voids in the flux layer are large and concentrated, and the void ratio is significantly higher, which leads to a decrease in the mechanical reliability of the solder joints. The thermal resistance test results show that the cavity will cause excessive thermal resistance, poor heat dissipation, a significant increase in junction temperature, and a decrease in thermal reliability, which in turn leads to severe light aging and ultimately changes in photoelectric performance. When the grain size is 5–15 μm, the uniformity of the particle size is good. After the filament is aged for 1000 h at high temperature and humidity, the light maintenance rate remains at 65.6%, and the filament performance is stable and reliable. It has certain reference value in the actual production process.