Increase In Functional Density Research Articles

Improving functional density of time-critical applications using hardware-based dynamic reconfiguration and bitstream specialisation


 
 
 The dynamic reconfiguration of an FPGA has many advantages, but the overhead from the process reduces the functional density of applications. Functional density is an indication of the composite benefits a reconfigured application obtains above its generic counterpart and measures the computational throughput per unit hardware resources. Typically, only quasi-static applications obtain a functional density advantage by dynamically reconfiguring its parameters. Contributing to the functional density reduction of applications with tight time constraints is the overhead to generate a new configuration, and the time it takes to load it onto the device. Normally these applications have to reuse their hardware numerous times between configurations before obtaining a functional density advantage. The most promising reconfiguration method to improve functional density with minimal hardware reuse was one that extracts certain characteristics from the bitstream and then implements a bitstream specialiser that generates new hardware at bit-level while the device is being reconfigured. While it was shown that this method allows reconfiguration of an application in real-time, its effect on functional density was not determined. This paper will show that a significant increase in functional density can be achieved for applications where reconfiguration is required before the next execution cycle of the application.
 
 

Enhanced electrostatic modulation of ionic diffusion through carbon nanotube membranes by diazonium grafting chemistry

A membrane structure consisting of an aligned array of open ended carbon nanotubes (∼7 nm i.d.) spanning across an inert polymer matrix allows the diffusive transport of aqueous ionic species through CNT cores. The plasma oxidation process that opens CNTs tips inherently introduces carboxylic acid groups at the CNT tips, which allows for a limited amount of chemical functional at the CNT pore entrance. However for numerous applications, it is important to increase the density of carboxylic acid groups at the pore entrance for effective separation processes. Aqueous diazonium-based electrochemistry significantly increases the functional density of carboxylic acid groups. pH dependent dye adsorption–desorption and interfacial capacitance measurements indicate ∼5–6 times increase in functional density. To further control the spatial location of the functional chemistry, a fast flowing inert liquid column inside the CNT core is found to restrict the diazonium grafting to the CNT tips only. This is confirmed by the increased flux of positively charged Ru ( bipy ) 3 +2 with anionic functionality. The electrostatic enhancement of ion diffusion is readily screened in 0.1 M electrolyte solution consistent with the membrane pore geometry and increased functional density.

Impact of Scaling on MOS Analog Performance

A first-order analysis of the impact of scaling on MOS analog performance under moderate scaling conditions is presented in this paper. Assuming a polysilicon gate ion-implanted MOS technology, quasi-constant voltage (QCV) scaling is shown to be the optimal scaling law, offering the best overall analog performance and resulting in an increase in functional density, gain-bandwidth product with a moderate degradation in gain, and signal-to-noise ratio. The first-order analysis agrees fairly well with computer simulation. A typical case study shows that under moderate scaling conditions, CMOS can generally offer a higher voltage gain when compared to depletion load NMOS and is the preferred technology for scaled analog implementations.

Injection-coupled synchronous logic

A novel injector structure used in conjunction with an I/SUP 2/L gate is proposed and its application to the design of current comparators and synchronous logic is described. The operation and fabrication of basic gates as well as current comparators, SR and T flip-flops are discussed. The new gate structures exhibit similar power/spl times/delay products, but lead to a considerable increase in functional density when compared to standard I/SUP 2/L in synchronous logic applications.

Realization of a multivalued integrated injection logic (MI/sup 2/L) full adder

A multivalued integrated injection logic scheme and its application to the realization of a full adder is described in this correspondence. The integrated full adder is implemented and fabricated using V-groove isolated I/SUP 2/L technology. Results obtained on the experimental structures indicate that the multivalued full adder offers an increase in functional density while retaining approximately the same area x delay product as a binary full adder at identical power levels.

Multivalued integrated-injection-logic (MI2L) full adder

A multivalued integrated-injection-logic full adder is described. Results obtained on the experimental structure indicate that the multivalued I2L full adder offers an increase in functional density while retaining approximately the same area–delay product as a binary full adder.