Impact of Scaling on MOS Analog Performance

Abstract

A first-order analysis of the impact of scaling on MOS analog performance under moderate scaling conditions is presented in this paper. Assuming a polysilicon gate ion-implanted MOS technology, quasi-constant voltage (QCV) scaling is shown to be the optimal scaling law, offering the best overall analog performance and resulting in an increase in functional density, gain-bandwidth product with a moderate degradation in gain, and signal-to-noise ratio. The first-order analysis agrees fairly well with computer simulation. A typical case study shows that under moderate scaling conditions, CMOS can generally offer a higher voltage gain when compared to depletion load NMOS and is the preferred technology for scaled analog implementations.