Including Output Buffers Research Articles

A 25-GHz emitter degenerated LC VCO

A 25-GHz emitter degenerated bipolar LC voltage-controlled oscillator (VCO) designed in IBM's SiGe 6 HP BiCMOS process (f/sub T//spl sim/47 GHz) is presented. Including output buffers, the VCO occupies an area of 435 /spl mu/m/spl times/225 /spl mu/m and consumes 22 mW at a 1.9-V power supply. The phase noise at 1 MHz offset is -93 dBc/Hz and it achieves a high f/sub OSC//f/sub T/ ratio with a figure of merit of 174 dB.

A robust 43-GHz VCO in CMOS for OC-768 SONET applications

In this paper, we present a 43-GHz LC-VCO in 0.13-/spl mu/m CMOS for use in SONET OC-768 optical networks. A tuned output buffer is used to provide 1.3 V/sub p-p/ (single-ended) into a 90-fF capacitive load as is required when the VCO is used in typical clock and data recovery (CDR) circuits. Phase noise is -90 dBc/Hz at a 1-MHz offset from the carrier; this meets SONET jitter specifications. The design has a tune range of 4.2%. The VCO, including output buffers, consumes 14 mA from a 1-V supply and occupies 0.06 mm/sup 2/ of die area. Modern CMOS process characteristics and the high center frequency of this design mean that the tank loss is not dominated by the integrated inductor, but rather by the tank capacitance. An area-efficient inductor design that does not require any optimization is used.

An 8-Bit 2-Gsample/s Folding-Interpolating Analog-to-Digital Converter in SiGe Technology

This paper deals with the design and implementation of an 8-bit 2-Gsample/s folding-interpolating analog-to-digital converter (ADC) using a SiGe technology with a unity gain cutoff frequency f/sub T/ of 47 GHz. The high-speed high-resolution ADC has applications in direct IF sampling receivers for wideband communication systems. The converter occupies an area of 3.5 mm/spl times/3.5 mm including pads and exhibits an effective resolution bandwidth of 700 MHz at a sampling rate of 2 Gsample/s. The maximum DNL and INL are 0.5 and 1 LSB, respectively. The ADC dissipates 3.5W (including output buffers) from a 3.3-V power supply.

A 10-Gb/s CDR/DEMUX with LC delay line VCO in 0.18-μm CMOS

A monolithic 10-Gb/s clock/data recovery and 1:2 demultiplexer are implemented in 0.18-/spl mu/m CMOS. The quadrature LC delay line oscillator has a tuning range of 125 MHz and a 60-MHz/V sensitivity to power supply pulling. The circuit meets SONET OC-192 jitter specifications with a measured jitter of 8 ps p-p when performing error-free recovery of PRBS 2/sup 31/-1 data. Clock and data recovery (CDR) is achieved at 10 Gb/s, demonstrating the feasibility of a half-rate early/late PD (with tri-state) based CDR on 0.18-/spl mu/m CMOS. The 1.9/spl times/1.5 mm/sup 2/ IC (not including output buffers) consumes 285 mW from a 1.8-V supply.

Highly integrated InP HBT optical receivers

This paper presents two highly integrated receiver circuits fabricated in InP heterojunction bipolar transistor (HBT) technology operating at up to 2.5 and 7.5 Gb/s, respectively. The first IC is a generic digital receiver circuit with CMOS-compatible outputs. It integrates monolithically an automatic-gain-control amplifier, a digital clock and data recovery circuit, and a 1:8 demultiplexer, and consumes an extremely low 340 mW of power at 3.3 V, including output buffers. It can realize a full optical receiver when connected to a photo detector/preamplifier front end. The second circuit is a complete multirate optical receiver application-specific integrated circuit (ASIC) that integrates a photodiode, a transimpedance amplifier, a limiting amplifier, a digital clock and data recovery circuit, a 1:10 demultiplexer, and the asynchronous-transfer-mode-compatible word synchronization logic. It is the most functionally complex InP HBT optoelectronic integrated circuit reported to date. A custom package has also been developed for this ASIC.

Selectively doped heterostructure frequency dividers

The operation of high-speed divide-by-two circuit (binary counter) composed of selectively doped heterostructure logic gates is reported for the first time. These field-effect transistor circuits utilize the enhanced transport properties of high-mobility electrons confined near a heterojunction interface in a selectively doped AlGaAs/GaAs structure. The dividers are based on a Type-D flip-flop composed of six direct-coupled NOR-gates having 1-µm gate lengths and 4-µm source-drain spacings. They are fabricated by conventional optical contact lithography on a four-layer Al .3 Ga .7 As/GaAs structure grown by molecular-beam epitaxy. Successful operation is demonstrated at 5.9 GHz at 77 K for 1.3-V bias and 30-mW total power dissipation (including output buffers) and 3.7 GHz at 300 K for 1.4-V bias and 19-mW total power dissipation. Total power dissipation values as low as 3.9 mW at 0.65-V bias were also obtained for 2.85-GHz operation at 300 K. These preliminary results illustrate the promise of SDHT logic for ultrahigh-speed low-power applications.