InAsSb Channel Research Articles

Development of noise model for InAsSb MOSFETs and their application in low noise amplifiers

In this paper, we develop the low frequency noise (LFN) model for symmetric double gate InAsSb channel n-MOSFETs and report noise performance of such devices as well as amplifier circuits built using them. Our noise model relies on the drain current Id which is obtained from the carrier concentration and Pao-Sah’s current formulation taking into account field dependent electron mobility and interface trapped-charge density Dit. The drain current model is calibrated with reported experimental data. The calculated values of Id and transconductance gm are utilized to find power spectral density of drain current as a function of drain and gate bias voltages, channel length, channel thickness, equivalent oxide thickness and also Dit. Moreover, we have studied the performance of low noise amplifiers (LNAs) with simultaneous noise and input matching (SNIM) topology using both InAsSb and Si channel devices, and computed the minimum noise figure and output noise power density and compared the results. Our investigation reveals that InAsSb MOSFETs exhibit better low noise performance in the strong inversion region of operation at which devices are biased to operate usually for analog circuit applications. Furthermore, the LNA with InAsSb channel MOSFET exhibits noise figure of 1.38 dB in strong inversion region enabling the amplifier suitable for many applications.

Threading dislocation degradation of InSb to InAsSb subchannel double heterostructures

In this paper, we report the transport properties of an InAsSb quantum well channel double heterostructure. We propose a structure of the InAsSb quantum well with an AlInSb/AlInSb double matrix barrier. The quantum well is investigated for an Al x In1−x Sb/Al0.24In0.76Sb/In y As1−y Sb/Al0.24In0.76Sb composition over a variable interpolation range (y = 0–0.3) of the InAsSb channel region. With the smallest threading density of 1.4 × 108 cm−2 and the highest electron mobility of 43000 cm2/Vs at 15 nm quantum well thickness, a small lattice mismatch is shown between the double matrix AlInSb barrier and the InAsSb channel. This is the lowest threading dislocation density and the highest mobility among those reported for all InSb-based heterostructure devices. This device is further proven to be defec-free due to better lattice match with the InAsSb channel quantum well. Therefore, this device could be used for a wide range of ultra-low power applications. Open image in new window

Device characteristics of InAlSb/InAs and InAlSb/InAsSb HFETs

The successful fabrication of InAlSb/InAs and InAlSb/InAsSb HFETs using recessed gate technology is reported. Epitaxial growth, device fabrication and characterisation are discussed in this Letter. A comparison of the two kinds of HFETs shows that the use of Sb in the InAs channel layer can effectively reduce the gate leakage resulting from the band-to-band tunnelling. This improvement is primarily because of increased separation between the conduction band edge of the InAsSb channel layer and the valence band edge of the InAlSb top barrier layer. An InAlSb/InAsSb HFET with 2 μm gate length and 50 μm gate width shows ID = 596 mA/mm and gm = 1 S/mm.

Growth of InAsSb-channel high electron mobility transistor structures

We discuss the molecular beam epitaxial growth of the random alloy InAsSb for use as the channel in high electron mobility transistors (HEMTs). Room-temperature mobilities of 22000cm2∕Vs have been achieved at a sheet carrier density of 1.4×1012∕cm2. This is a marked improvement over the mobility of 13000cm2∕Vs at the same carrier density obtained in previous attempts to grow the InAsSb channel using a digital alloy procedure [J. B. Boos, M. J. Yang, B. R. Bennett, D. Park, W. Kruppa, R. Bass, Electron. Lett. 35, 847 (1999)]. We have also implemented different barriers and buffer layers to enhance the transport properties and overall performance of the HEMT structure.

Increased electron mobility of InAsSb channel heterostructures grown on GaAs substrates by molecular beam epitaxy

We have designed and grown high-electron-mobility heterostructures that use InAsySb1−y group V alloys as a channel material and that can be used in high-speed transistors and magnetic field sensors. The group V alloys were formed by modulating As2 and Sb2 beams during growth. The composition was controlled by changing the group V shutter cycle. The electron mobility in the InAsySb1−y channel, which is only 20–30 nm thick and is sandwiched between Al0.15In0.85Sb high-resistivity barrier layers, was increased to 28 000 cm2 V−1 s−1 at room temperature by reducing the lattice mismatch between the channel layer and the barrier layer. This mobility is an order of magnitude greater than that of the strained Al0.15In0.85Sb/InSb/Al0.15In0.85Sb heterostructure grown as a reference. The electron mobility in the InAsySb1−y channel sandwiched between Al0.5Ga0.5Sb barrier layers was also increased from 19 500 cm2 V−1 s−1 (y=1.0) to 24 500 cm2 V−1 s−1 (y=0.86) at room temperature by reducing the lattice mismatch between the channel layer and the barrier layer. These increases in mobility indicate that the lattice mismatch must be reduced in order to achieve a high electron mobility of such heterostructures grown mismatched on GaAs substrates.

Low-voltage, high-speed AlSb/InAsSb HEMTs

Antimonide-based HEMTs have been fabricated with an InAsSb channel. Infra-red photoluminescence measurements at 5 K confirm that the addition of Sb changes the band structure from a staggered type II heterojunction lineup to a type I. These HEMTs with 0.1 /spl mu/m gate length exhibit decreased output conductance and improved voltage gain. At V/sub DS/=0.6 V, a microwave transconductance of 700 mS/mm and an output conductance of 110 mS/mm were obtained corresponding to a voltage gain of 6.