Improvement In Power Consumption Research Articles

Exploitation of wavelength, hardware, and path redundancies in fault-tolerant all-optical DCNs

Abstract Data center performance is affected by three main factors; bandwidth, latency, and reliability of intra-data center interconnection network. Bandwidth and latency are definitely improved by adopting optical technology for intra-data center communication, but fault tolerance of the corresponding optical networks has been raised less. Recently, we introduced two Torus-based, all-optical, and non-blocking networks, i.e. O-TF and O-FTF, addressing reliability of optical networks, and now, in this paper, to address the scalability problem, we propose a novel Optical Clos-based architecture which reduces minimum number of required wavelength channels, as well as, the switch size in each node. Moreover, we examine three different types of redundancies; including (a) wavelength (adopted in O-TF network), (b) hardware (adopted in O-FTF network), and (c) path (adopted Optical Clos)) redundancies, in terms of throughput drop under failures, implementation cost, optical power loss, electrical power, latency, topology, and wiring complexity. In addition to simulating networks utilizing generated traffic based on Microsoft data, realistic traffic has also been considered. Our simulation results confirm that in addition to improving power consumption and latency, O-TF, O-FTF, and O-Clos architectures lead to throughput increment up to 80%, 90%, and 70%, respectively, comparing to WaveCube at the presence of network failure, as result of adopting our proposed fault-tolerant method, named as RAOP.

Long-Range Fast Nanopositioner Using Nonlinearities of Hybrid Reluctance Actuator for Energy Efficiency

While nanopositioners often use flexures for high quality motion avoiding nonlinearities, the achievable motion range and energy efficiency are limited, due to the force required for positioning against the flexures. To overcome the problem, this paper proposes a flexure-guided nanopositioner with a nonlinear hybrid reluctance actuator for a large range and energy efficiency. The actuator has nonlinear negative stiffness that partially cancels the flexures' stiffness. Consequently, the nonlinearities reduce the required current by up to 67%. To compensate them for high-precision motion in the entire range of 2 mm, a feedback controller is designed, achieving a closed-loop bandwidth of 640 Hz and positioning resolution of 2.48 nm(rms). The mechatronic system is designed such that the stiffness nonlinearity has no influence on the closed-loop stability and bandwidth. Additionally for accurate periodic scanning motion, modeling-free inversion-based iterative control is combined to decrease the tracking error by a factor of 396 at most. The achieved error is 10 nm(rms) for a 1 Hz triangular motion of 1.6 mm range and for a 100 Hz triangular motion of 10 μm range. The results demonstrate that the proposed nanopositioner can play a role of both long-stroke and highspeed scanners with the improved power consumption.

A meta heuristic-based task scheduling and mapping method to optimize main design challenges of heterogeneous multiprocessor embedded systems

In this paper, we proposed a meta heuristic-based task scheduling method to optimize lifetime reliability, performance and power consumption of heterogeneous MPSoCs. Lifetime reliability is affected by several failure mechanisms with different behaviors which are mainly dependent on temperature and its variation pattern. To improve lifetime reliability of multiprocessor systems, it is required to consider the effect of all potential failures and their distinct impact during the optimization process. Moreover, improving power consumption and execution time makes the optimization process more complicated due to the existing trade offs among these parameters. Our proposed task scheduling method optimizes lifetime reliability by considering the effect of all failure mechanisms, power consumption and execution time of heterogeneous MPSoCs. It employs a design space exploration engine based on the Non-dominated Sorting Genetic Algorithm (NSGA-II) to make the exploration process more efficient. To demonstrate the effectiveness of our proposed task scheduling and mapping method and compare it to the related studies, several experiments are performed. Moreover, the importance of thermal cycling (TC), as an emerging thermal concern in computing the lifetime reliability of MPSoCs, and also the capability of our proposed method in controlling it are studied and compared to related research. Experimental results show that employing our proposed scheduling method improves performance, lifetime reliability and power consumption about 24%, 30% and 3.6% respectively on average compared to two selected related studies. Furthermore, our proposed approach decreases the occurrence rate of all failure mechanisms compared to related studies and outperforms them in term of the thermal cycling rate about 48% on average.

A spill data aware memory assignment technique for improving power consumption of multimedia memory systems

As embedded memory technology evolves, the traditional Static Random Access Memory (SRAM) technology has reached the end of development. For deepening the manufacturing process technology, the next generation memory technology is highly required because of the exponentially increasing leakage current of SRAM. Non-volatile memories such as STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory), PCM (Phase Change Memory) are good candidates for replacing SRAM technology in embedded memory systems. They have many advanced characteristics in the perspective of power consumption, leakage power, size (density) and latency. Nonetheless, nonvolatile memories have two major problems that hinder their use it the next-generation memory. First, the lifetime of the nonvolatile memory cell is limited by the number of write operations. Next, the write operation consumes more latency and power than the same size of the read operation. This study describes a compiler optimization technique to overcome such disadvantages of a nonvolatile memory component in hybrid cache memories. A hybrid cache is proposed to overcome the disadvantages using a compiler. Specifically, to minimize the number of write operations for nonvolatile memory, we present a data replacement technique that considers the locations of the register spill data. Many portions of the memory accesses are yielded by the spill data of a register allocator in an optimizing compiler. Such spill data can be partially removed using a recalculation method. Thus, we implemented an optimization technique that rearranges the data placement with recalculation to minimize the write instructions on the nonvolatile memory. Our experimental results show that the proposed technique can reduce the average number of spill codes by 20%, and improves the energy consumption by 20.2% on average.

Graphene-based integrated photonics for next-generation datacom and telecom

Graphene is an ideal material for optoelectronic applications. Its photonic properties give several advantages and complementarities over Si photonics. For example, graphene enables both electro-absorption and electro-refraction modulation with an electro-optical index change exceeding 10$^{-3}$. It can be used for optical add-drop multiplexing with voltage control, eliminating the current dissipation used for the thermal detuning of microresonators, and for thermoelectric-based ultrafast optical detectors that generate a voltage without transimpedance amplifiers. Here, we present our vision for grapheme-based integrated photonics. We review graphene-based transceivers and compare them with existing technologies. Strategies for improving power consumption, manufacturability and wafer-scale integration are addressed. We outline a roadmap of the technological requirements to meet the demands of the datacom and telecom markets. We show that graphene based integrated photonics could enable ultrahigh spatial bandwidth density , low power consumption for board connectivity and connectivity between data centres, access networks and metropolitan, core, regional and long-haul optical communications.

Modelling EMS Maglev systems to develop control algorithms

Electromagnetic suspension (EMS) system for magnetically levitated vehicles can utilize different types of magnets, such as room temperature electromagnets, superconducting magnets as well as permanent magnets. In the course of the study the trichotomy has been applied to the electromagnetic suspension system. The EMS configuration considered in this paper has been treated as a combination of these three types of magnets modelled individually. Results of computations were compared to measurements on a working prototype that provided stable levitation of a platform weighing above 190 kg. A good agreement between the simulated and measured parameters enabled verification of the computational models for separate magnets, selection of efficient control algorithms for a combined EMS system, validation of numerical procedures for payload scaling for practical maglev applications. The combined EMS under study has demonstrated improved power consumption as compared to the conventional EMS. Optimal control algorithms for a combined EMS should factor in various criteria, including rapidity, stability, power consumption, weight, reliability, etc. Different types of magnets can be integrated into a single module to reach the desired performance. Hence, the optimum solution for the EMS design and relevant control algorithms should be searched within a common procedure using detailed computational models.

A liquid lens switching-based motionless variable fiber-optic delay line

Abstract We present a Variable Fiber-Optic Delay Line (VFODL) module capable of imparting long variable delays by switching an input optical/RF signal between Single Mode Fiber (SMF) patch cords of different lengths through a pair of Electronically Controlled Tunable Lenses (ECTLs) resulting in a polarization-independent operation. Depending on intended application, the lengths of the SMFs can be chosen accordingly to achieve the desired VFODL operation dynamic range. If so desired, the state of the input signal polarization can be preserved with the use of commercially available polarization-independent ECTLs along with polarization-maintaining SMFs (PM-SMFs), resulting in an output polarization that is identical to the input. An ECTL-based design also improves power consumption and repeatability. The delay switching mechanism is electronically-controlled, involves no bulk moving parts, and can be fully-automated. The VFODL module is compact due to the use of small optical components and SMFs that can be packaged compactly.

Energy-Efficient Fast Configuration of Flexible Transponders and Grooming Switches in OFDM-Based Elastic Optical Networks

We investigate the problem of energy-efficient resource allocation constrained to quality of service and physical requirements in orthogonal frequency division multiplexing (OFDM)-based elastic optical networks and propose a fast two-stage algorithm to solve it. The first stage of the proposed algorithm deals with routing, traffic grooming, and traffic ordering and mainly aims at minimization of the number of deployed optical amplifiers and transponders. We provide an integer linear program for routing and traffic grooming and propose a heuristic procedure, which yields its near-optimum solution in a shorter runtime. In the second stage, we optimize transponder parameters to minimize total transponder power consumption. We show how signal-to-noise ratio and transponder power consumption are represented by convex expressions and use the results to provide a convex formulation for optimizing transponder parameters. Unlike the conventional formulations, we consider transmitted optical power as an optimization variable tuned for each lightpath and show how this improves power consumption of different network elements. Simulation results demonstrate that the proposed algorithm for routing and traffic grooming is around 2 orders of magnitude faster than its equivalent integer linear formulation and reduces network power consumption more than 9% compared with the scenario in which no traffic grooming is applied. It is also shown that our convex formulation for transponder parameter assignment is 1 order of magnitude faster than its mixed-integer nonlinear counterpart and reduces total transponder power consumption more than 13% compared with a fixed transponder configuration scheme. Furthermore, we investigate the effect of adaptive modulation assignment on power consumption and show it is not necessary to have complex transponders supporting a high number of modulation formats. We also analyze the impact of transponder capacity on traffic grooming and investigate the inherent trade-off between capital expenditures and operational expenditures in terms of the capacity and design complexity of the transponders.

A Study on the Quality Improvment of PCB by Improving Power Consumption for Radar

A Study on the Quality Improvment of PCB by Improving Power Consumption for Radar

(Invited) Non Volatile Resistive and Magnetic Memories: Materials, Integration Challenges and Opportunities

Demand for on chip memories has increased due to the need for more data storage and the increasing gap between processor and off chip memory speed. One of the solutions proposed to improve power consumption and to fill the memory gap is to introduce non volatility at different levels of the memory hierarchy (storage class, main memory, cache memory). Several disruptive technologies have been proposed in the last decades for non-volatile memory (NVM) applications. The more investigated ones are Phase-Change Memories (PCM), Conducting-Bridge RAM (CBRAM), Oxide-based Resistive RAM (OxRAM), and Perpendicular Spin Transfer Torque Magnetic Memories (pSTTMRAM). Intensive studies and demonstrations have being carried out in order to develop and improve those emerging memory concepts. Some memory stacks have shown promising results in term of high speed, good endurance or retention but not necessarily all of the above. A survey of published results [1] as well as internal studies carried out at LETI [2, 3] using a memory test vehicle developed to evaluate various memory concepts using the same 130nm CMOS logic have led us to infirm that the universal memory ie an optimized memory stack that fits all requests of memory hierarchy does not exist. However, because requirements for cache memories (ie high speed, endurance, but low data retention) are completely different from requirements for embedded memories (ie high temperature or long data retention), different technology or optimized memory stacks can be targeted to fulfill specific applications. It will be shown that despite very different physical concepts, universal signatures can be extracted unifying the characteristics of different technologies and thus drawing conclusions on their behaviors and tradeoffs (such as programming window vs endurance, programming window vs data retention, and endurance vs data retention). This is illustrated in Fig 1 where the relation between the programming window and the endurance capabilities of the different technologies is presented. It is shown that high programming window is typically associated to poor endurance capabilities, (as shown by some classes of chalco-based CBRAM or non-polar OxRAM). For these technologies the overall filament is believed to participate to the creation and the dissolution events. On the contrary, displacing very few atoms/ions, or spins, during the write or erase event allows to guarantee a long-lasting endurance (examples are certain class of polar OxRAM and STT MRAMs). Data also show that a universal tradeoff exists between the endurance and data retention itself. The better the performances in endurance, the lower the data retention capabilities at high temperature. Write latency speed will be discussed and ultra fast (<1ns) writing MRAM technology based on a recently discovered effect Spin Orbit torque (SOT MRAM) will be discussed. The characteristics and performances of the different emerging will be presented (materials, integration, speed, endurance, consumption and scalability) in regards of the needed specifications required for potential applications. [1] ] H.-S. P. Wong, C. Ahn, J. Cao, et al., “Stanford Memory Trends,” https://nano.stanford.edu/stanford-memory-trends, accessed Nov 11, 2015 [2] C. Nail; G. Molas; P. Blaise et al “ Understanding RRAM endurance, retention and window margin trade-off using experimental results and simulations”: IEDM 2016 Pages: 4.5.1 - 4.5.4, DOI: 10.1109/IEDM.2016.7838346[3] V. Sousa, G. Navarro, N. Castellani et al., “Operation Fundamentals in 12Mb Phase Change Memory Based on Innovative Ge-rich GST Materials Featuring High Reliability Performance”, VLSI Tech. Symp., pp.98-99, 2015 Figure 1

Energy-Efficient BBU Allocation for Green C-RAN

Cloud radio access network (C-RAN) separates the baseband processing from the radio transmissions in the base station. The baseband processing is done at the baseband unit (BBU), centrally for a huge number of remote radio head (RRH). The BBU pool works virtually and significantly to reduce power consumption in the cellular networks. Efficient coordination among these BBUs can improve network performance in terms of resource utilization and power consumption. In this letter, we propose a BBU and RRH association scheme based on graph partitioning and rejoining to minimize the power consumption due to communication overhead. Simulation results show that the proposed algorithm improves power consumption up to 20% and reduces handover overhead up to 30% compared with the traditional approach.

Sustainable lifestyle factors influencing industries' electric consumption patterns using Fuzzy logic and DEMATEL: The Nigerian perspective

The methods applied in the attempt to minimize electricity consumption waste as result of consumer's consumption patterns is of crucial concern for government, investors and even consumers. There is a need to identify the potential factors influencing electricity consumption pattern in order to encourage sustainable practices. To examine the electricity consumption pattern and their influencing factors, this study applied Fuzzy-DEMATEL model to examine the sustainable lifestyle factors of electricity consumption pattern in Nigeria. The originality of this paper lies in the proposed approach that integrates fuzzy logic and DEMATEL to evaluate sustainable lifestyles factors that influence industries electric consumption patterns for the first time in Nigeria. Firstly, 24 sustainable lifestyle factors were sourced from literature sources and grouped into 4 clusters of economic, political, environmental and socio-cultural criteria. Two sets of questionnaires were distributed to 30 experts who comprise of managers and senior technicians in Nigerian Power Industry. The results show that the critical factors which influence industries electric consumption patterns are corruption, inadequate planning and design, electricity theft, literacy level, population demography and lifestyle attitude. The implication for decision makers is that in improving power consumption pattern in the Nigerian industries; emphasis should be placed on the critical sustainable lifestyle factors. Thus, corruption should be minimized, planning and design adequately implemented, theft of electricity curbed while improving literacy level and lifestyles of the masses to improve electric consumption patterns.

Singularity-Tolerant Inverse Kinematics for Bipedal Robots: An Efficient Use of Computational Power to Reduce Energy Consumption

We propose a nonlinear inverse kinematics formulation which solves for positions directly. Compared to various other popular methods that integrate velocities, this formulation can better handle fast, asymmetric, and singular-postured balancing tasks for humanoid robots. We also introduce joint position and velocity boundaries as inequality constraints in the optimization to ensure feasibility. Such boundaries provide safety when approaching or getting away from joint limits or singularities. Besides, mixing positions and velocities in our proposed algorithm facilitates recovery from singularities, which is very difficult for conventional inverse kinematics methods. Extensive demonstrations on the real robot prove the applicability of the proposed algorithm while improving power consumption. Our formulation automatically handles different numerical and behavioral difficulties rising from singularities, which makes it a reliable low-level conversion block for different Cartesian planners.

An efficient numerical-based crosstalk avoidance codec design for NoCs

With technology scaling, crosstalk fault has become a serious problem in reliable data transfer through Network on Chip (NoC) channels. The effects of crosstalk fault depend on transition patterns appearing on the wires of NoC channels. Among these patterns, Triplet Opposite Direction (TOD) imposes the worst crosstalk effects. Crosstalk Avoidance Codes (CACs) are the overhead-efficient mechanisms to tackle TODs. The main problem of CACs is their high imposed overheads to NoC routers. To solve this problem, this paper proposes an overhead-efficient coding mechanism called Penultimate-Subtracted Fibonacci (PS-Fibo) to alleviate crosstalk faults in NoC wires. PS-Fibo coding mechanism benefits the novel numerical system that not only completely removes TODs but also, is applicable to a wide range of NoC channel widths. The PS-Fibo coding mechanism is evaluated using BookSim-2 and VHDL-based simulations in the terms of codec efficiency on the crosstalk fault reduction, codec power consumption, codec area occupation and network performance. Evaluation results, carried out for a wide range of NoC channel widths indicate that PS-Fibo can improve power consumption and area occupations of codec and NoC performance with respect to the other state-of-the-art coding mechanisms.

An energy-aware load balancing algorithm to perform computation type application processes in a cluster of servers

A cluster of servers is getting scalable and widely used in various types of applications. It is critical to reduce the electric energy consumed by servers in a cluster to realise eco society. In this paper, we newly propose an improved delay time based (IDTB) algorithm to reduce the total electric energy consumption of a cluster and to more efficiently utilise the computation resources for performing application processes in a cluster. In the IDTB algorithm, a load balancer estimates the state of each server just by using responses from processes and without additionally communicating with servers to collect states of the servers. We evaluate the IDTB algorithm compared with the basic round-robin (RR), improved power consumption laxity based (IPCLB), and delay time based (DTB) algorithms. We show the total electric energy consumption of a cluster and response time of each process can be reduced in the IDTB algorithm.

An energy-aware load balancing algorithm to perform computation type application processes in a cluster of servers

A cluster of servers is getting scalable and widely used in various types of applications. It is critical to reduce the electric energy consumed by servers in a cluster to realise eco society. In this paper, we newly propose an improved delay time based (IDTB) algorithm to reduce the total electric energy consumption of a cluster and to more efficiently utilise the computation resources for performing application processes in a cluster. In the IDTB algorithm, a load balancer estimates the state of each server just by using responses from processes and without additionally communicating with servers to collect states of the servers. We evaluate the IDTB algorithm compared with the basic round-robin (RR), improved power consumption laxity based (IPCLB), and delay time based (DTB) algorithms. We show the total electric energy consumption of a cluster and response time of each process can be reduced in the IDTB algorithm.

Multi-objective optimization for efficient motion of underwater snake robots

Underwater snake robots constitute a bio-inspired solution within underwater robotics. Increasing the motion efficiency in terms of the forward speed by improving the locomotion methods is a key issue for underwater robots. Furthermore, the energy efficiency is one of the main challenges for long-term autonomy of these systems. In this study, we will consider both these aspects of efficiency, which in some cases can be conflicting. To this end, we formulate a multi-objective optimization problem to minimize power consumption and maximize forward velocity. In particular, the optimal values of the gait parameters for different motion patterns are calculated in the presence of trade-offs between power consumption and velocity. As is the case with all multi-objective optimization problems, the solution is not a single point but rather a set of points. We present a weighted-sum method to combine power consumption and forward velocity optimization problems. Particle swarm optimization is applied to obtain optimal gait parameters for different weighting factors. Trade-off curves or Pareto fronts are illustrated in a power consumption---forward velocity plane for both lateral and eel-like motion pattern. They give information on objective trade-offs and can show how improving power consumption is related to deteriorating the forward velocity along the trade-off curve. Therefore, decision makers can specify the preferred Pareto optimal point along the trade-off curve. Moreover, we address some interesting questions regarding the optimal gait parameters, which is a significant issue for the control of underwater snake robots in the future.

GPUrpc

Graphics processing units (GPUs) are increasingly used for high-performance computing. Programming frameworks for general-purpose computing on GPUs (GPGPU), such as CUDA and OpenCL, are also maturing. Driving this trend is the recent proliferation of mobile devices such as smartphones and wearable computers. These devices are increasingly incorporating computationally intensive applications that involve some form of environmental recognition such as augmented reality (AR) or voice recognition. However, devices with low computational power cannot satisfy such demanding computing requirements. The CPU load of these devices could be reduced by offloading computation onto GPUs on the cloud. This paper presents GPUrpc, a remote procedure call (RPC) extension to Gdev, which is a rich set of runtime libraries and device drivers for achieving first-class GPU resource management. GPUrpc allows developers to use CUDA for GPGPU development work. Existing research uses RPCs based on the CUDA application programming interfaces (APIs); hence, all CUDA APIs require communication. To reduce communication overhead, we use an RPC based on a low-level API than CUDA API and reduced API that does not require communication. Our evaluation conducted on Linux and NVIDIA GPUs shows that the basic performance of our prototype implementation is reliable in comparison with the existing method. Evaluation using the Rodinia benchmark suite designed for research in heterogeneous parallel computing showed that GPUrpc is effective for applications such as image processing and data mining. GPUrpc also can improve power consumption to approximately 1/6 that of CPU processing for performing 512 × 512 matrix multiplication.

Micro‐architectural approach to the efficient employment of STTRAM cells in a microprocessor register file

In this paper, the authors propose two approaches that employ spin transfer torque random access memory (STTRAM) in the design of the register file, an important part of embedded processors. However, STTRAM suffers from both endurance and latency in the write operation. Consequently, employing STTRAM in the register file entails two challenges: (i) the lifetime significantly decreases as data are frequently written into a register file; (ii) the delay of the critical path increases as a result of the slow write operation. They have proposed using two well-known micro-architectural approaches: the last-write-update (LWU) and the value locality (VL), to minimize the number of write operations into a register. The main observation behind LWU is that only the last write operations of certain registers in the re-order buffer should be considered. VL exploits the fact that a limited number of values are more likely to be written into a register file. Their simulation shows that by employing the LWU and VL approaches, the lifetime of the STTRAM-based register file, compared with the lifetime of traditional static RAM-based register file architecture, extends to about 40 years on average and around 3.5 years in the worst case while improving power consumption by 30%.

A dynamic data source selection system for smartwatch platform.

A novel data source selection algorithm is proposed for ambulatory activity tracking of elderly people. The algorithm introduces the concept of dynamic switching between the data collection modules (a smartwatch and a smartphone) to improve accuracy and battery life using contextual information. We show that by making offloading decisions as a function of activity, the proposed algorithm improves power consumption and accuracy of the previous work by 7 hours and 5% respectively compared to the baseline.