Improved Cell Stability Research Articles

FinFET-based 6T SRAM cell design: analysis of performance metric, process variation and temperature effect

In this paper, we have proposed a FinFET-based 6T Static Random Access Memory (SRAM) cell. The proposed FinFET-based 6T SRAM cell offers better stability in terms of Static Noise Margin (SNM) and Read Noise Margin (RNM). During the read operations, SRAM cell stability analysis is based on the SNM because many memory errors may occur. Since SNM changes with each cell operation, a complete analysis of SNM in read mode is required. In this paper, we have looked into the SRAM cell SNM during read mode analysing various options to improve cell stability. These techniques are based on the transistor width, word-line, bit-line and supply voltage modulations. We showed that it is possible to improve the stability of SRAM cell during read operations, while reducing word-line voltage which reduces the leakage current. We have also analysed the temperature effect on SNM, leakage current and leakage power for FinFET-based SRAM cell.

Interfacial degradation effects of aqueous solution-processed molybdenum trioxides on the stability of organic solar cells evaluated by a differential method

The authors investigate the influence of two hole interfacial materials poly (3,4-ethylenedioxythiophene):poly (styrenesulfonate) (PEDOT:PSS) and aqueous solution-processed MoO3 (sMoO3) on cell stability. sMoO3-based device demonstrated obviously improved stability compared to PEDOT:PSS-based one. Current-voltage characteristics analysis is carried out to investigate the effect of the hole interfacial layers on the cell stability. The formation of additional trap states at the interfaces between the hole interfacial layer and the active layer in degraded devices is verified by a differential method. Improved cell stability is attributed to a relatively stable sMoO3 interfacial layer compared to PEDOT:PSS by comparing their different trap states distributions.

Adaptive static and dynamic noise margin improvement in minimum-sized 6T-SRAM cells

We present a novel SRAM technique for simultaneously enhancing the static and dynamic noise margins in six transistor cells implemented with minimum size devices using a design for manufacturability constrained layout. During each access, the word-line voltage (VWL) is internally reduced with respect to the cell and bit-line voltages that are maintained at nominal VDD. A specific VWL can be determined for each memory region, thus allowing for an adaptive approach. The benefits and drawbacks of the technique on the overall memory performance are thoroughly investigated through both simulations and experimental data. Simulations results show that this technique expands the read margin without an appreciable increase of memory area. Specifically, an improvement of 52.6% in static noise margin and a 24.5% in critical charge (parameter used to account for the dynamic stability) has been achieved with a VWL reduction of 20%. The impact of variability on SNM is reduced, while both read and write delay increase by a specific amount that should be considered as a tradeoff when setting the word-line voltage value. A 16Kbit SRAM test chip including the proposed technique has been fabricated in a 65nm CMOS technology. Silicon measurements confirm that the proposed technique improves cell stability during READ, which allows operating at relatively low values of VWL with a small impact on read time.

Characterization of Cu1.4Te Thin Films for CdTe Solar Cells

The copper telluride thin films were prepared by a coevaporation technique. The single-phase Cu1.4Te thin films could be obtained after annealing, and annealing temperature higher than 220°C could induce the presence of cuprous telluride coexisting phase. Cu1.4Te thin films also demonstrate the high carrier concentration and high reflectance for potential photovoltaic applications from the UV-visible-IR transmittance and reflectance spectra, and Hall measurements. With contacts such as Cu1.4Te and Cu1.4Te/CuTe, cell efficiencies comparable to those with conventional back contacts have been achieved. Temperature cycle tests show that the Cu1.4Te contact buffer has also improved cell stability.

High performance Bi-layered electrolytes via atomic layer deposition for solid oxide fuel cells

This study investigates the functionality of bi-layered electrolytes in intermediate temperature solid oxide fuel cells. A thin yttria-stabilized zirconia (YSZ) layer is expected to protect the underlying gadolinia doped ceria (GDC) electrolyte from being chemically reduced and significantly improve cell stability and durability. Although a thinner YSZ layer is preferable to minimize ohmic loss, there are limitations as to how thin the YSZ film can be and still serves as a valid protection layer. The limitation is partially attributed to the inter-diffusion and significant morphological changes during the high temperature sintering processes. In this study, a stable operation was demonstrated for extended duration (>80 h) with only a 28 nm YSZ layer (corresponding to a YSZ/GDC thickness ratio of 6.5 × 10−5) when limitations in both fabrication (<∼800 °C) and operating conditions (<∼600 °C, dry H2) were imposed. Furthermore, the functionality of a protection layer with a given thickness was found to strongly depend on the method of depositing the protective layer. Protective layers deposited by atomic layer deposition (ALD) can be much thinner than those prepared by physical vapor deposition; the YSZ/GDC thickness ratio for a stable operation approached close to a theoretical value when the ALD was used.

Impact Analysis of NBTI/PBTI on SRAM VMINand Design Techniques for Improved SRAM VMIN

Negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) are critical circuit reliability issues in highly scaled CMOS technologies. In this paper, we analyze the impacts of NBTI and PBTI on SRAM VMIN, and present a design solution for mitigating the impact of NBTI and PBTI on SRAM VMIN. Two different types of SRAM VMIN (SNM-limited VMIN and time-limited VMIN) are explained. Simulation results show that SNM-limited VMIN is more sensitive to NBTI while time-limited VMIN is more prone to suffer from PBTI effect. The proposed NBTI/PBTI-aware control of wordline pulse width and woldline voltage improves cell stability, and mitigates the VMIN degradation induced by NBTI/PBTI.

Influence of the indium tin oxide/organic interface on open-circuit voltage, recombination, and cell degradation in organic small-molecule solar cells

In this paper we investigate the performance and stability of small-molecule organic solar cells with respect to the indium tin oxide (ITO)/organic interface. Different zinc-phthalocyanine (ZnPc)/fullerene (C${}_{60}$) cell architectures with and without ITO ${\mathrm{O}}_{2}$-plasma treatment are compared and tested with respect to their degradation behavior under illumination in inert atmosphere. Photoelectron spectroscopy (UPS and XPS) shows that the ${\mathrm{O}}_{2}$-plasma treatment increases the ITO work function from 4.3 eV up to 5.6 eV. We find that both the increased ITO work function as well as the introduction of an electron blocking layer between ITO and the mixed donor/acceptor layer increases the open-circuit voltage ${V}_{\text{oc}}$ by more than 200 mV. For both cases our continuum approach device simulation quantitatively relates the increase of ${V}_{\text{oc}}$ to a reduced contact recombination and thus a reduced dark current. For cells built on ozone treated ITO we find a fast cell degradation caused by the UV part of the AM 1.5 spectrum. We identify the degradation, which manifests itself in a decrease of ${V}_{\text{oc}}$ of up to 25%, as a partial reversion of the plasma induced ITO work function increase. Additionally, we demonstrate that the degradation can be reduced by structural changes in the cell architecture, leading to improved cell stability. We present a comprehensive study of the recombination at the ITO/organic interface and its influence on the open-circuit voltage and the cell stability.

A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme

To realize high-density SRAMs, we developed a four-transistor SRAM cell with a newly developed stacked vertical poly-silicon PMOS. The vertical poly-silicon PMOS has a gate surrounding a body that forms a channel and yields a drive current of 20 /spl mu/A at 25/spl deg/C. Vertical poly-silicon PMOSs are used as transfer MOSs and are stacked over the bulk NMOSs, used as driver MOSs, to reduce the size of a four-transistor SRAM cell. As a result, the size of the proposed four-transistor SRAM cell was 38% of that of a six-transistor SRAM cell. We also developed an electric-field-relaxation scheme to reduce cell leakage and a dual-word-voltage scheme to improve cell stability. By applying these two schemes to the proposed four-transistor SRAM cell, we achieved a 90% reduction in cell leakage and an improvement in cell stability.