Improvement In Delay Time Research Articles

High-Capacity Data Collection Platform for Smart Cities Using IEEE 802.11ad-Based Millimeter-Wave V2X Communication

The collection and utilization of huge sensor data from vehicles for visualizing the city is expected to realize various enhanced services for smart cities. A next-generation gigabit vehicle-to-everything (V2X) data collection platform based on 60 GHz millimeter-wave (mmWave) small cell radio access has been proposed in the previous work for enabling efficient and high-capacity data upload from vehicles to the cloud. This paper presents further analysis of the initial link setup delay to evaluate the effectiveness of the fast initial V2X link setup method proposed, which is suitable for 60 GHz communication based on IEEE 802.11ad. This paper also presents the application programming interface (API) design based on the hypertext transport protocol (HTTP) to enable the efficient upload of hundreds of files. Combined with the buffering technique at a multiaccess edge computing (MEC) server, the proposed system successfully utilizes very high bandwidth between a vehicle and a MEC server. The proposed methods achieve a 30 times improvement in delay for establishing the initial link and an 11 times higher average throughput. A prototype system installed in Marysville, Ohio, achieved a peak throughput of 2.8 Gbps and successfully demonstrates the effectiveness of city visualization based on high-capacity data collection and analytics.

Efficient Layout Design of Junctionless Transistor Based 6-T SRAM Cell Using SOI Technology

In this work novel 6-T SRAM layout has been proposed using Junctionless SOI MOS transistor. The key idea of the proposed structure is to reduce the area consumed by the device with an aim to improve its performance. The junctionless SOI n- and p-MOS transistor exhibits lower off-state current and higher Ion to Ioff ratio when compared to double gate junctionless transistor available in the literature. In the proposed 6-T SRAM cell layout formation, an arrangement of latch circuit was done and later on two n-transistors back-to-back were cascaded to form a compact SRAM layout configuration. Thus, the proposed structure utilizes nearly half the area of conventional junctionless 6-T SRAM layout. The proposed design also shows improvement in delay time in read/write operations. The proposed structures were designed and simulated using Sentaurus and Cogenda device simulator.

A Low-Power Field-Programmable Gate Array Routing Fabric

This paper describes a new programmable routing fabric for field-programmable gate arrays (FPGAs). Our results show that an FPGA using this fabric can achieve 1.57 times lower dynamic power consumption and 1.35 times lower average net delays with only 9% reduction in logic density over a baseline island-style FPGA implemented in the same 65-nm CMOS technology. These improvements in power and delay are achieved by 1) using only short interconnect segments to reduce routed net lengths, and 2) reducing interconnect segment loading due to programming overhead relative to the baseline FPGA without compromising routability. The new routing fabric is also well-suited to monolithically stacked 3-D-IC implementation. It is shown that a 3-D-FPGA using this fabric can achieve a 3.3 times improvement in logic density, a 2.51 times improvement in delay, and a 2.93 times improvement in dynamic power consumption over the same baseline 2-D-FPGA.

Near speed-of-light signaling over on-chip electrical interconnects

The propagation limits of electrical signals for systems built with conventional silicon processing are explored. A design which takes advantage of the inductance-dominated high-frequency regime of on-chip interconnect is shown capable of transmitting data at velocities near the speed of light. In a 0.18-/spl mu/m six-level aluminum CMOS technology, an overall delay of 283 ps for a 20-mm-long line, corresponding to a propagation velocity of one half the speed of light in silicon dioxide, has been demonstrated. This approach offers a five times improvement in delay over a conventional repeater-insertion strategy.

Improvement in narrow channel effect by an alternative isolation technology

An isolation technique based on simple modification of a conventional isolation technique is presented. It gives improvement in narrow channel effect. The concept is explained and applied to the development of scaled MOS transistors. The performance of field and active area transistors fabricated using the conventional technique is compared with that obtained using the new isolation technique. It is shown that the new isolation technique eliminates load current reduction of depletion transistors and increases the threshold voltage of enhancement transistors with width. Improvement in delay time produced by the proposed isolation technique compared with conventional isolation is evaluated using ring oscillators. It is shown that for near micron and submicron technologies, the delay time would be reduced with the alternative isolation technique.

A high-speed BiCMOS tristate buffer

A high-speed BiCMOS tristate buffer with a single bipolar device pull-up structure for driving a large capacitive load is presented. According to SPICE simulation results, the buffer, which occupies about an identical area, has a 2*improvement in delay time as compared to the CMOS tristate buffer. >

Power-supply voltage impact on circuit performance for half and lower submicrometer CMOS LSI

Based on theoretical understanding, the concept that the lower power supply voltage limit can be simply expressed by 1.1E/sub c/L/sub eff/, where E/sub c/ is the critical electric field necessary to cause carrier velocity saturation and L/sub eff/ is the effective channel length, is introduced. Experimental results confirmed that 1.1E/sub c/L/sub eff/ predicts a good guideline for power-supply voltage for CMOS devices over a wide range of gate oxide thickness (7-45 nm) and design rule (0.3-2.0 mu m). On the basis of theoretical models and experimental results, trends for power-supply voltage with MOS device scaling are demonstrated. It is shown that 1.1E/sub c/L/sub eff/ can be regarded as the lower power-supply voltage limit in order to maintain the improvement in delay time for below 0.6- mu m channel length at reduced power supply. The transconductance behavior for a MOSFET under high electric fields was investigated in order to explain the physical meaning of 1.1E/sub c/L/sub eff/.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>