Improvement In Cut-off Frequency Research Articles

A New Load Adaptive Identification Method Based on an Improved Sliding Mode Observer for PMSM Position Servo System

The effective identification of the load torque is one of the key methods to improve the positioning accuracy of the position servo system, and the sliding mode observer (SMO) is a common identification method in the speed control system because of its advantages of insensitive parameters and easy physical realisation. However, the existing SMO cannot achieve high precision and high response identification of load torque in the full speed range when the motor is running at variable-speed or variable-load, which limits its application in the position servo system. Based on the analysis of the stability and the adaptive law of feedback gain coefficient, an improved SMO for adaptive identification based on adaptive control and improvement of cut-off frequency is proposed. To verify the proposed method, the dedicated simulation model and test platform are built. The results show that the proposed observer can realize the adaptive identification of the load torque under the condition of variable-speed or variable-load, and the estimation accuracy is high. The position servo system designed by the proposed observer can improve the response against load change, which is an effective method for high-precision positioning control of the position servo system with a variable-speed or variable-load.

Design and investigation of dopingless double-gate line tunneling transistor: Analog performance, linearity, and harmonic distortion analysis**Project supported by the Natural Science Research Key Project of Universities of Anhui Province, China (Grant No. KJ2017A502), the Introduced Talent Project of Anhui Science and Technology University, China (Grant No. DQYJ201603), and the Excellent Talents Supported Project of Colleges and Universities, China (Grant No.

The tunnel field-effect transistor (TFET) is proposed by using the advantages of dopingless and line-tunneling technology. The line tunneling is created due to the fact that the gate electric field is aligned with the tunneling direction, which dramatically enhances tunneling area and tunneling current. Moreover, the effects of the structure parameters such as the length between top gate and source electrode, the length between top gate and drain electrode, the distance between bottom gate and drain electrode, and the metal position on the on-state current, electric field and energy band are investigated and optimized. In addition, analog/radio-frequency performance and linearity characteristics are studied. All results demonstrate that the proposed device not only enhances the on/of current ratio and reduces the subthreshold swing, but also offers eight times improvement in cut-off frequency and gain band product as compared with the conventional point tunneling dopingless TFET, at the same time; it shows better linearity and small distortions. This proposed device greatly enhances the potential of applications in dopingless TFET.

Temperature sensitivity analysis of inner-gate engineered JL-SiNT-FET: An Analog/RF prospective

This paper explores the temperature sensitivity of Inner-gate engineered junctionless silicon nanotube FET (JL-SiNT-FET) on analog/RF performance. It is found that the reduction in the operating temperature from 400 K to 100 K improves the various analog/RF figure of merits (FOMs) of all the three configurations (DS-JL-SiNT-FET, D-JL-SiNT-FET, and S-JL-SiNT-FET) of JL-SiNT-FET by considerable expanse. The improvement in intrinsic dc gain (AV) is found to be ~1.8 dB, 2.2 dB, and 1.6 dB respectively for DS-JL-SiNT-FET, D-JL-SiNT-FET, and S-JL-SiNT-FET when the working temperature is reduced from 400 K to 100 K. Additionally, the improvement in cut-off frequency (fT), maximum oscillation frequency (fMAX), and gain-frequency product (GFP) caused by temperature variation are correspondingly significant in all the three configurations of JLSiNT-FET. It is also observed that the improvement (ΔF = FT=100 - FT=400, where F is the analog/RF FOM) caused by the reduction in temperature is almost similar in all the configurations.

Improvement in Cutoff Frequency of Microstrip Butterworth Low Pass Filter using DGS Technique

This paper presents the design, analysis and fabrication of Butterworth Low pass filter with sharp rejection response using defected ground surface technique. The work is carried out to design a low pass filter with cut-off frequency 2.5 GHz to achieved the broad frequency response; the first step is to make a rectangle of 10x10mm at ground surface and the equivalent circuit for the DGS, subsequently followed to consequent L-C parameters extraction using analysis of S parameters response (EM simulation). The designed Butterworth low pass filter is realized and optimized using DGS (Defected Ground Structure) to attain a compact size, satisfactory transition sharpness along with low insertion loss in pass band and wide rejection in the stop band. The fabricated device showed the good conformity with theoretical and VNA measured result.

Modeling of Advanced RF Bulk FinFETs

The modeling of the advanced RF bulk FinFETs is presented in this letter. Extensive S-parameter measurements, performed on the advanced RF bulk FinFETs, show 31% improvement in cutoff frequency over recent work [1] . The transistor’s characteristics are dominated by substrate parasitics at intermediate frequencies (0.1–10 GHz) and gate parasitics at high frequencies (above 10 GHz). The Berkeley short-channel IGFET model-common multi gate model is improved to account for the impact of substrate coupling on the RF parameters. The model demonstrates excellent agreement with the measured data over a broad range of frequencies. The model passes AC, DC and RF symmetry tests, demonstrating its readiness for (RF) circuit design using FinFETs.

Impact of Dielectric Pocket on Analog and High-Frequency Performances of Cylindrical Gate-All-Around Tunnel FETs

In this paper, a novel structure of cylindrical GAA-TFETs with high-k dielectric pocket is proposed to improve the analog and high-frequency performances. We have discussed the device physics of proposed structure in details with the help of 3-D TCAD simulation. Since, an optimum part of the drain region is replaced with a high-k dielectric material (HfO2), oxide-semiconductor interface formed between channel and dielectric pocket increases the tunneling width at channel-drain junction. Further, this increment in tunneling width caused by depleted drain region under dielectric pocket eventually reduces the ambipolar conduction and OFF-current without deteriorating ON-current and subthreshold slope. It is observed that device performances are improved with increasing pocket length and thickness up to a value of 30-nm and 4-nm respectively; beyond which either device performances are degraded or dependences become poor. The advantages of using a high-k dielectric material over low-k are demonstrated in terms of reduction in ambipolar conduction, and immunity against degradation in current switching ratio during device scaling. Additionally, the impact of high-k dielectric pocket on high-frequency performances is demonstrated. Unlike tunnel FETs with dielectric spacer, it is observed that drain-to-gate capacitance is reduced for our proposed device which further leads to improvement in cutoff frequency.

Impact of thin high-k dielectrics and gate metals on RF characteristics of 3D double gate junctionless transistor

RF performance of 3D double gate junctionless transistor (JLT) is investigated considering thin high-k dielectrics and gate metals. The 3D double gate junctionless transistor (JLT) with 20nm gate length is designed and simulated in order to study the RF parameters such as transconductance, transconductance generation factor, output conductance and resistance, intrinsic capacitance, cut-off frequency, early voltage, and intrinsic gain. High-k dielectric gate oxide and gate metals have effect on the DC characteristics of JLT. However, in order to evaluate the impact of high-k gate dielectrics on the RF performance of the device, SiO2, Si3N4, HfO2 dielectrics are considered and compared their performances. Furthermore, the effect of various gate metals on RF performances of the device is also discussed. Gate oxide with higher-k value improves the transconductance, output conductance, and intrinsic gain of the device. While, gate metal with lower work function exhibits better RF characteristics in JLT, application of different high-k dielectrics and gate metal have no improvement in cut-off frequency. The investigation gives an idea to optimize the RF performance of the device using suitable gate dielectric and gate metal. This investigation helps to create an opportunity for the junctionless transistor to realize high performances RF circuits.

A new RF trench-gate multi-channel laterally-diffused MOSFET on InGaAs

In this work, a new RF power trench-gate multi-channel laterally-diffused MOSFET (TGMC-LDMOS) on InGaAs is proposed. The gate-electrodes of the new structure are placed vertically in the trenches built in the drift layer. Each gate results in the formation of two channels in the p-body region of the device. The drain metal is also placed in a trench to take contact from the n+-InGaAs region located over the substrate. In a cell length of , the TGMC-LDMOS structure has seven channels, which conduct simultaneously to carry drain current in parallel. The formation of multi-channels in the proposed device increases the drive current ( leading to a large reduction in the specific on-resistance (. Due to better control of gates on the drain current, the new structure exhibits substantially higher transconductance ( resulting in significant improvement in cut-off frequency ( and oscillation frequency (. Using two-dimensional numerical simulations, a 55 V TGMC-LDMOS is demonstrated to achieve 7 times higher , 6.2 times lower , 6.3 times higher peak , 2.6 times higher , and 2.5 times increase in in comparison to a conventional device for the identical cell length.

Analog/RF performance analysis of inner gate engineered junctionless Si nanotube

This paper investigates the analog/RF performance of inner gate engineered junctionless silicon nanotube (JLSiNT) FETs. We demonstrate that the RF performance of symmetric drain/source DS-JLSiNT-FETs (inner gate extended from one end of nanotube to other end covering both drain and source region) gets improved when the inner gate of nanotube (NT) covers only either drain and channel regions (D-JLSiNT-FETs) or source and channel regions (S-JLSiNT-FETs) because of reduced total gate capacitance. The improvement in cut-off frequency (fT) in D-JLSiNT-FETs is ∼45% whereas in S-JLSiNT-FETs is ∼23% as compare to DS-JLSiNT-FETs. However, the percentage improvement in maximum oscillation frequency (fMAX) is more in S-JLSiNT-FETs. Furthermore, due to partial covering of inner gate, the gate electrostatic integrity (EI) is reduced resulting in degraded intrinsic gain (AV). However, the deterioration in AV is almost minimal (∼0.4 dB) for D-JLSiNT-FETs as compared to DS-JLSiNT-FETs but the deterioration in AV is aggravated to ∼22 dB for S-JLSiNT-FETs. The up scaling of Source/Drain extension length improves the performance of D-JLSiNT-FETs but degrade the performance of S-JLSiNT-FETs when compared to DS-JLSiNT-FETs. The improvement in fT and fMAX in D-JLSiNT-FETs as well as in S-JLSiNT-FETs are pronounced with outer gate length scaling when compared to DS-JLSiNT-FETs.

High performance multi-finger MOSFET on SOI for RF amplifiers

In this paper, we propose structural modifications in the conventional planar metal–oxide–semiconductor field-effect transistor (MOSFET) on silicon-on-insulator by utilizing trenches in the epitaxial layer. The proposed multi-finger MOSFET (MF-MOSFET) has dual vertical-gates placed in separate trenches to form multiple channels in the p-base which carry the drain current in parallel. The proposed device uses TaN as gate electrode and SiO2 as gate dielectric. Simultaneous conduction of multiple channels enhances the drain current (ID) and provides higher transconductance (gm) leading to significant improvement in cut-off frequency (ft). Two-dimensional simulations are performed to evaluate and compare the performance of the MF-MOSFET with the conventional MOSFET. At a gate length of 60 nm, the proposed device provides 4 times higher ID, 3 times improvement in gm and 1.25 times increase in ft with better control over the short channel effects as compared with the conventional device.

20 nm high performance enhancement mode InP HEMT with heavily doped S/D regions for future THz applications

The DC and RF performance of Lg = 20 nm enhancement mode (E-Mode) In0.7Ga0.3As/InAs/In0.7Ga0.3As composite channel high electron mobility transistor (HEMT) on InP substrate with heavily doped In0.52Ga0.48As source/drain regions (S/D) is compared with the performance of conventional HEMT structure. The other features of the device include the use of T-gate, thin layer of platinum sink into the barrier layer, double δ-doping technology and multilayer cap. The Sentaurus TCAD simulations performed at room temperature using physics based drift-diffusion carrier transport model shows that Lg = 20 nm, W = 2 × 10 μm device with heavily doped In0.52Ga0.48 As S/D regions exhibit a 14% improvement in transconductance (gm) and 15% improvement in drain current compared to conventional HEMT structure. Also the proposed device shows 25% improvement in cut-off frequency (fT) and 17% improvement in maximum oscillation frequency (fmax) compared to conventional HEMT structure and this excellent performance is achieved mainly due to the reduction of parasitics such as S/D resistances and also due to the low gate length.

AlN Barriers for Capacitance Reduction in Phase-Change RF Switches

We demonstrate four-terminal GeTe-based RF switches with independent thermal actuation (switching). These devices incorporate an AlN-based dielectric separating high-conductivity W micro-heaters from the RF signal path. With dc, pulsed, and RF testing, we show that an AlN barrier decreases the switch parasitic capacitance with minimal increases in the switching power. Decoupling these design variables, with the high thermal conductivity of the AlN, makes it possible to increase the electrical separation with a thicker AlN film for lower parasitic capacitance with minimal decrease in desirable thermal coupling. Increasing the AlN thickness from 105 to 170 nm results in switches with an improvement in cutoff frequency, $f_{\mathrm {CO}}$ from 5.3 to 8 THz, a $C_{\mathrm{\scriptscriptstyle OFF}}$ improvement from 15 to 10 fF, while maintaining the $R_{\mathrm{\scriptscriptstyle ON}}$ at 2 $\Omega $ . This improvement was accompanied by normalized minimum power to amorphize increases of only 14% (from 1.5 to 1.7 W) for a 100-ns heater pulse.

A nanoscale dual-channel trench (DCT) MOSFET for analog/RF applications

In this paper, we propose a dual-channel trench MOSFET (DCT-MOSFET) on SOI for high-frequency small signal analog applications. The gate of device is placed in a trench which creates two n-channels in p-base carrying drain current in parallel. Simultaneous conduction of two-channels provides substantial improvement in performance parameters. Based on two-dimensional simulations, a 60 nm DCT-MOSFET is demonstrated to achieve 92% higher drain current, twofold increase in peak transconductance, 67% rise in transconductance-to-drain current ratio, 47% higher intrinsic voltage gain, 90% improvement in cut-off frequency and 2.1 times higher maximum oscillation frequency as compared to the conventional MOSFET.

Quantum Well Saturation Effect on the Reduction of Base Transit Time in Light-Emitting Transistors

In this paper, we demonstrate the improvement of cutoff frequency of the light-emitting transistor (LET) due to quantum well (QW) band-filling phenomenon (i.e., saturation) along with the carrier capturing and escaping processes in the base region. Through microwave measurement followed by small-signal model analysis, we observe that the base transit time, τ t , of the LET is reduced evidently from 90 to 20 ps when the collector current density increases from 2.43 to 34.9 kA/cm 2 . The reduction of τ t via saturation effect can be explained by the electroluminescence spectrum and thermionic emission theory of QW.

Impact of dual-k spacer on analog performance of underlap FinFET

Multigate structures have better short channel control than conventional bulk devices due to increased gate electrostatic control. FinFET is a promising candidate among multigate structures due to its ease of manufacturability. The RF performance of FinFET is affected by gate controlled parameters such as transconductance, output conductance and total gate capacitance. In this paper we have used dual-k spacers in underlap FinFETs to improve the gate electrostatic integrity. The inner high-k spacer helps in better screening out the gate sidewall fringing fields, thereby, increasing transconductance and reducing output conductance with increase in total gate capacitance. At 16nm gate lengths, we have observed that, the intrinsic gain of dual-k spacer based FinFET can be increased by more than 100% (>6dB) without affecting cutoff frequency and maximum oscillation frequency, as compared to conventional single spacer based FinFET. Improvement in cutoff frequency by 11% and maximum oscillation frequency by 5% can be achieved, when the gate lengths are scaled down to 12nm, in addition to 2.75 times (8.8dB) increase in intrinsic gain.

AC analysis of nanoscale GME-TRC MOSFET for microwave and RF applications

In this paper, the RF performance for Gate Material Engineered-Trapezoidal Recessed Channel (GME-TRC) MOSFET has been investigated and the results so obtained are compared with Trapezoidal Recessed Channel (TRC) MOSFET and Rectangle Recessed Channel (RRC) MOSFET, using device simulators; ATLAS and DEVEDIT. Further, the impact of technology parameter variations in terms of negative junction depth (NJD), gate metal workfunction difference, substrate doping ( N A) and corner angle, on GME-TRC MOSFET has also been evaluated. The simulation study shows the increase in transconductance and decrease in parasitic capacitance, which further contributes towards a significant improvement in cut-off frequency ( f t) in GME-TRC MOSFET as compared to conventional TRC and RRC MOSFETs. Moreover, the significant enhancement in maximum available power gain ( Gma), maximum transducer power gain ( G MT), maximum unilateral power gain (MUG), maximum frequency of oscillation ( f MAX) and stern stability factor ( K) have also been observed for GME-TRC MOSFET due to reduced short channel effects (SCEs) and enhanced current driving capabilities. Further, the experimental data for grooved gate MOSFET has also been verified with the simulated data and a good agreement between their results is obtained.

GATE LENGTH SCALING AND MICROWAVE PERFORMANCE OF DOUBLE GATE NANOTRANSISTORS

A detailed analysis of static and dynamic characteristics of deep submicron double and single gate SOI MOSFETs is presented, based on 2D numerical simulations for high frequency analog applications. Results show that although DG MOSFET offers excellent performance with respect to short channel immunity and higher transconductance, it offers nearly two times the value of gate-to-source capacitance as compared to SG devices, thus limiting the cut-off frequency at higher gate voltages. At ultra short channel lengths and low gate overdrive voltages, DG devices show a significant improvement in cut-off frequency compared to SG devices, thus presenting DG nanotransistors as potential candidates for analog microwave applications.

Analysis of Static and Dynamic Performance of Short-Channel Double-Gate Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors for Improved Cutoff Frequency

A comprehensive analysis of the static and dynamic characteristics of deep submicron double-gate (DG) and single-gate (SG) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) is presented, based on two-dimensional (2D) numerical simulations for high-frequency analog applications. Results from the static analysis show that a DG MOSFET offers excellent performance with respect to short-channel immunity, drain current enhancement and improvement in transconductance, Early voltage and voltage gain. We also analyze the impact of volume inversion (VI) on the performance of DG devices under saturation conditions, and investigate, in detail, the level of current enhancement and the bias conditions under which it can be achieved. Results show that a current as high as 15 times that of single-gate (SG) MOSFETs can be achieved in DG devices at a transconductance-to-current ratio of 25 V-1. Analysis of the dynamic part shows that due to the dual-gate structure, DG devices offer nearly twice the gate-source capacitance as compared to SG devices, thus limiting the cutoff frequency at higher gate voltages and longer channel lengths. At shorter channel lengths (L≤50 nm) and low gate overdrive voltages (<400 mV), DG devices show a significant improvement in cutoff frequency compared to SG devices, thus making double-gate SOI MOSFETs potential candidates for high-frequency analog applications.

Cryogenic small-signal model for 0.55 mu m gate-length ion-implanted GaAs MESFET's

The cryogenic microwave performance of 0.5*300- mu m gate ion-implanted GaAs MESFETs is presented. The devices studied have been fabricated as part of a process control monitor chip (PCM) which uses comparable industry standard design rules. Detailed small-signal element modeling has been performed to determine the temperature dependence of important physical parameters over a lattice temperature range from 300 K to 115 K. The authors find appreciable improvement in cut-off frequency (f/sub T/) and well behaved temperature dependence of transconductance (g/sub m/) and gate-source capacitance (C/sub gs/). Empirical relations for the temperature dependence of f/sub T/, the maximum frequency of oscillation (f/sub max/), g/sub m/ and C/sub gs/, that should provide accurate temperature-dependent device and circuit models are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

New concedpts for high frequency and high power frequency multipliers and their impact on quasi-optical monolithic array design

Varactors have been extensively employed for harmonic generation, where high cut-off frequency is dependent upon small C min , which is typically achieved using small device active area. However, small area limits the output power. Furthermore, the power and frequency dependences of the series resistance in the epitaxial region degrade the efficiency and cut-off frequency as well. As a result, currently utilized varactors are only officient for relatively low power generation and limited output frequency. Herein, we describe our new approach where by epitaxially stacking single quantum barrier structures, more than an order of magnitude improvement in cut-off frequency and power handling ability may be possible. Alternatively, by combining a Schottky barrier with stacked single quantum barriers, superior performance can also be achieved. These concepts can be readily employed for quasi-optical frequency multiplier arrays, and appear to result in simplified fabrication compared to other devices. The design of high performance quasi optical arrays requires optimization of the passive (metalization) grid as well as the embedded semiconductor devices. Recent work has resulted in an improved impedance model for the standard diode-loaded strip array, including a quantitative estimate of the shunt capacitance introduced across the diode by the discontinuity of the metal strip at the diode site (“gap”). The value of this capacitance exceeds the predictedC min for these new devices. We discuss two grid design approaches that can suppress this capacitance.