Improved Interface Quality Research Articles

Morphology and Electrical Performance Improvement of NiGe/Ge Contact by P and Sb Co-implantation

In this letter, co-implantation of P and Sb dopants into NiGe film is first proposed to improve the characteristic of NiGe/Ge contact. Through this technique, obvious enhancement of NiGe thermal stability is achieved. The surface morphology of NiGe film even keeps smooth and flat after post-germanidation annealing up to 600 $^{\circ}{\rm C}$ . The current characteristics of the formed NiGe/p-Ge diodes are also improved, exhibiting better rectifying performance. It is believed that the improved interface quality and the enhanced dopant activation contribute to these improvements. Therefore, this technique shows great potential for high performance Ge device technology.

Effects of forming gas anneal on ultrathin InGaAs nanowire metal-oxide-semiconductor field-effect transistors

InGaAs gate-all-around metal-oxide-semiconductor field-effect transistors (MOSFETs) with 6 nm nanowire thickness have been experimentally demonstrated at sub-80 nm channel length. The effects of forming gas anneal (FGA) on the performance of these devices have been systematically studied. The 30 min 400 °C FGA (4% H2/96% N2) is found to improve the quality of the Al2O3/InGaAs interface, resulting in a subthreshold slope reduction over 20 mV/dec (from 117 mV/dec in average to 93 mV/dec). Moreover, the improvement of interface quality also has positive impact on the on-state device performance. A scaling metrics study has been carried out for FGA treated devices with channel lengths down to 20 nm, indicating excellent gate electrostatic control. With the FGA passivation and the ultra-thin nanowire structure, InGaAs MOSFETs are promising for future logic applications.

Surface Passivation and Interface Properties of Bulk GaAs and Epitaxial-GaAs/Ge Using Atomic Layer Deposited TiAlO Alloy Dielectric

High quality surface passivation on bulk-GaAs substrates and epitaxial-GaAs/Ge (epi-GaAs) layers were achieved by using atomic layer deposited (ALD) titanium aluminum oxide (TiAlO) alloy dielectric. The TiAlO alloy dielectric suppresses the formation of defective native oxide on GaAs layers. X-ray photoelectron spectroscopy (XPS) analysis shows interfacial arsenic oxide (As(x)O(y)) and elemental arsenic (As) were completely removed from the GaAs surface. Energy dispersive X-ray diffraction (EDX) analysis and secondary ion mass spectroscopy (SIMS) analysis showed that TiAlO dielectric is an effective barrier layer for reducing the out-diffusion of elemental atoms, enhancing the electrical properties of bulk-GaAs based metal-oxide-semiconductor (MOS) devices. Moreover, ALD TiAlO alloy dielectric on epi-GaAs with AlGaAs buffer layer realized smooth interface between epi-GaAs layers and TiAlO dielectric, yielding a high quality surface passivation on epi-GaAs layers, much sought-after for high-speed transistor applications on a silicon platform. Presence of a thin AlGaAs buffer layer between epi-GaAs and Ge substrates improved interface quality and gate dielectric quality through the reduction of interfacial layer formation (Ga(x)O(y)) and suppression of elemental out-diffusion (Ga and As). The AlGaAs buffer layer and TiAlO dielectric play a key role to suppress the roughening, interfacial layer formation, and impurity diffusion into the dielectric, which in turn largely enhances the electrical property of the epi-GaAs MOS devices.

Optical properties of SrTiO3 on silicon(100)

Epitaxial buffer layers enable the many functionalities found in perovskites to be integrated with silicon. However, epitaxial growth of SrTiO3 on silicon is tricky and has so far only been achieved by molecular beam epitaxy. Nonetheless, previous investigations of these films were limited by the amorphous layer occurring at the interface. Through a combination of improved interface quality and an improved model, we report the optical properties of SrTiO3 films on Si(100) investigated by spectroscopic ellipsometry. We find that the data are best described by a model with two different SrTiO3 layers, potentially resulting from variations in the oxygen content.

Novel Approach for Improving Interface Quality of 4H-SiC MOS Devices with UV Irradiation and Subsequent Thermal Annealing

We report on the harmful impact of ultraviolet (UV) light irradiation on thermally grown SiO2/4H-SiC(0001) structures and its use in subsequent thermal annealing for improving electrical properties of SiC-MOS devices. As we previously reported [1], significant UV-induced damage, such as positive flatband voltage shift and hysteresis in capacitance-voltage curves as well as increased interface state density, was observed for SiC-MOS devices with thermally grown oxides. Interestingly, the subsequent annealing of damaged SiO2/SiC samples resulted in superior electrical properties to those for untreated (fresh) devices. These findings imply that UV irradiation of the SiO2/SiC structure is effective for eliciting pre-existing carbon-related defects and transforming them into a simple configuration that can be easily passivated by thermal treatment.

Investigation of unusual mobile ion effects in thermally grown SiO2 on 4H-SiC(0001) at high temperatures

Generation and elimination of mobile ions in thermally grown SiO2 on 4H-SiC(0001) were systematically investigated by electrical measurements of MOS capacitors. In contrast to a SiO2/Si system, intrinsic positive mobile ions were found to exist in as-oxidized SiO2/SiC structures, leading to significant instability of SiC-MOS devices. Post-oxidation annealing in Ar ambient mostly eliminates the mobile ions, but they are generated again by subsequent high-temperature hydrogen annealing despite the improved interface quality. The density of the mobile ions was estimated to be several 1012 cm−2. Possible physical origins of the mobile ions are discussed on the basis of the experimental findings.

Improvement on Interface Quality and Reliability Properties of HfAlOx MIS Capacitor with Dual Plasma Treatment

HfO2 is considered a promising gate dielectric material for sub-45 nm CMOS technology. It has been reported that incorporate Al into HfO2 forming Hf aluminates in order to increase the crystallization temperature. However, the growth of the low-k interfacial layer at high-k/Si interface during high-k dielectric deposition would result in reliability degradation. Recently, incorporating nitrogen into HfAlOx gate dielectrics has beneficial effect on reliability performance. In addition, fluorine incorporation into high-k dielectrics also could have several improvements. In this study, dual plasma (CF4 pre-treatment and N2 post-treatment) was performed on HfAlOx MIS capacitor in order to improve interface quality and the reliability properties. According to our experimental results, dual plasma treatment could improve interface quality and enhance reliability properties of HfAlOx thin films.

Impact of scaling of dielectric thickness on mobility in top-contact pentacene organic thin film transistors

The effect of scaling of poly(methylmethacrylate) (PMMA) and cross-linkable poly(4-vinylphenol) (PVP) polymer dielectric thickness on field effect mobility in top contact pentance organic thin film transistors was investigated. Mobility at a constant gate voltage improved significantly with reduction in thickness of both dielectrics. Analysis at a constant gate electric field or identical induced accumulation charge revealed that only a part of the improvement occurs due to simple scaling of dielectric thickness, and the remaining is due to improvement in interface quality. Atomic force microscopic analysis of the dielectric surface revealed that dielectric roughness reduced with reduction in dielectric thickness. A comparison of the two dielectrics also indicates that band mobility is significantly higher in pentacene/PMMA as compared to pentacene/PVP dielectric.

Interface engineering with an MOCVD grown ZnO interface passivation layer for ZrO 2–GaAs metal–oxide–semiconductor devices

This work deals with the fabrication of a GaAs metal–oxide–semiconductor device with an unpinned interface environment. An ultrathin ( ∼ 2 nm) interface passivation layer (IPL) of ZnO on GaAs was grown by metal organic chemical vapor deposition to control the interface trap densities and to prevent the Fermi level pinning before high-k deposition. X-ray photoelectron spectroscopy and high resolution transmission electron microscopy results show that an ultra thin layer of ZnO IPL can effectively suppress the oxides formation and minimize the Fermi level pinning at the interface between the GaAs and ZrO 2. By incorporating ZnO IPL, GaAs MOS devices with improved capacitance-voltage and reduced gate leakage current were achieved. The charge trapping behavior of the ZrO 2/ZnO gate stack under constant voltage stressing exhibits an improved interface quality and high dielectric reliability.

Thin TiO2 grown by metal–organic chemical vapor deposition on (NH4)2S x -treated InP

The electrical characteristics of thin TiO2 films prepared by metal–organic chemical vapor deposition grown on a p-type InP substrate were studied. For a TiO2 film of 4.7 nm on InP without and with ammonium sulfide treatment, the leakage currents are 8.8×10−2 and 1.1×10−4 A/cm2 at +2 V bias and 1.6×10−1 and 8.3×10−4 A/cm2 at −2 V bias. The lower leakage currents of TiO2 with ammonium sulfide treatment arise from the improvement of interface quality. The dielectric constant and effective oxide charge number density are 33 and 2.5×1013 cm2, respectively. The lowest mid-gap interface state density is around 7.6×1011 cm−2 eV−1. The equivalent oxide thickness is 0.52 nm. The breakdown electric field increases with decreasing thickness in the range of 2.5 to 7.6 nm and reaches 9.3 MV/cm at 2.5 nm.

Comparison of the interfacial and electrical properties of HfAlO films on Ge with S and GeO2 passivation

We report the characteristics of HfAlO films deposited on S- and GeO2-passivated Ge substrates at 150 °C by atomic layer deposition technique using Hf(NO3)4 and Al(CH3)3 as the precursors. The x-ray photoelectron spectroscopic analyses reveal that GeO2 passivation is more effective to suppress GeOx formation than S passivation. It is demonstrated that the capacitors with GeO2 passivation exhibit better electrical properties with less hysteresis, improved interface quality, and reduced leakage current. These results indicate that using GeO2 as an interfacial layer may be a promising approach for the realization of high quality Ge-based transistor devices.

Fabrication of Ge-MOS capacitors with high quality interface by ultra-thin SiO 2/GeO 2 bi-layer passivation combined with the subsequent SiO 2-depositions using magnetron sputtering

Ge-MOS capacitors were fabricated by a novel method of ultra-thin SiO 2/GeO 2 bi-layer passivation (BLP) for Ge surface combined with the subsequent SiO 2-depositions using magnetron sputtering. For the Ge-MOS capacitors fabricated by BLP with O 2, to decrease oxygen content in the subsequent SiO 2 deposition is helpful for improving interface quality. By optimizing process parameters of the Ge surface thermal cleaning, the BLP, and the subsequent SiO 2 deposition, interface states density of 4 × 10 11 cm −2 eV −1 at around mid-gap was achieved, which is approximately three times smaller than that of non-passavited Ge-MOS capacitors. On the contrary, for the Ge-MOS capacitors fabricated by BLP without O 2, interface quality could be improved by an increase in oxygen contents during the subsequent SiO 2 deposition, but the interface quality was worse compared with BLP with O 2.

Excellent passivation effect of Cat-CVD SiN x/i-a-Si stack films on Si substrates

We have demonstrated that the surface recombination velocity can be lowered to as low as 1.3 cm/s for n-type c-Si wafers and to 9.0 cm/s for p-type wafers by using amorphous Si (a-Si) and Si nitride (SiN x ) stacked films prepared by catalytic chemical vapor deposition (Cat-CVD). These values are much lower than those of c-Si wafers passivated by same stacked structures formed by low-damage remote plasma-enhanced CVD (PECVD). It is revealed that Cat-CVD a-Si insertion layers play an important role to improve interface quality, and also SiN x films are also essential for reducing the surface recombination velocity down to such low levels.

Improvement of interface quality by post-annealing on silicon nanowire MOSFET devices with multi-wire channels

We have investigated the passivation effects of high-pressure hydrogen annealing (HPHA) on silicon nanowire (Si NW) metal oxide semiconductor field effect transistors (MOSFETs) with multi-wire channels. Compared to the conventional forming gas annealing (FGA) process, the results show that HPHA can significantly improve device performance parameters such as threshold voltage, subthreshold slope, mobility, and ION/IOFF ratio. This enhancement is attributed to the effective passivation of the interface traps between the SiO2 and the Si NW channel. Therefore, HPHA can be a promising process for the implementation of the Si NW MOSFET.

Nitrogen dependence of band alignment and electrical properties of HfTiON gate dielectrics metal-oxide-semiconductor capacitor

The effect of nitrogen incorporation on the band alignment and electrical properties of HfTiO gate dielectric complementary metal-oxide-semiconductor (MOS) capacitors has been investigated by spectroscopy ellipsometry, x-ray photoelectron spectroscopy, and electrical measurements. Reduction in optical band gap and band offsets has been detected. However, improved electrical properties have been achieved from HfTiON gate dielectric MOS capacitors attributed to the nitrogen-induced reduction in oxygen-related traps and the improved interface quality. Although there is a nitrogen-induced reduction in band gap and band offset, the sufficient barrier heights still makes HfTiON a promising high-k gate dielectric candidate for proposed near-future complementary metal-oxide-semiconductor applications.

High-Temperature Stability and Enhanced Performance of a-Si:H TFT on Flexible Substrate Due to Improved Interface Quality

We have investigated the effect of anneal time on the performance and temperature-dependent stability of low-temperature-fabricated (180°C) hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) on flexible substrates. For TFTs annealed for 48 h, the subthreshold slope and off-current were reduced by a factor of ~3 and by two orders of magnitude, respectively, when compared to unannealed TFTs. Furthermore, longer annealed TFTs showed a significant improvement in their stability when compared to unannealed TFTs. The lifetime values for the 48- and 96-h-annealed TFTs improved by a factor of ~3 compared to unannealed TFTs when the threshold voltage shift is extrapolated to 10 V. Stability at high temperatures with better lifetimes for the longer annealed TFTs is due to improvement in the a-Si:H/SiN <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</i> interface quality by the reduction of trapped charges inside the insulator. For all the TFTs at a positive gate bias, ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> follows a power law dependence with time, indicating state creation. A low β value (0.6 for unannealed TFTs to 0.37 for 96-h-annealed TFTs) indicates a good-quality a-Si:H channel and/or the a-Si:H/insulator interface after longer anneals.

Evaluation of AlGaN‐based deep ultraviolet emitter active regions by temperature dependent time‐resolved photoluminescence

AbstractTemperature dependent time‐resolved photoluminescence is used to study the development of active regions for optoelectronic devices employing AlGaN nanostructures for deep‐UV emission. The changing importance of dislocation versus point defects and their relationship to different forms of carrier localization are discussed. The results presented suggest that AlGaN nanostructure development for deep‐UV emitters require both point defect/impurity suppression for improved efficiency and lower dislocation density for improved interface quality. (© 2010 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Effective Surface Passivation by Novel $\hbox{SiH}_{4}$ –$\hbox{NH}_{3}$ Treatment and BTI Characteristics on Interface-Engineered High-Mobility $\hbox{HfO}_{2}$-Gated Ge pMOSFETs

A novel surface passivation technique using silicon nitride (SN) by - treatment has been demonstrated on -gated Ge pMOSFETs. It is found that ultrathin SN passivation is more effective to suppress the Ge out diffusion than ultrathin Si passivation. Improved interface quality and device performance were achieved for the device with the SN passivation. Fluorine (F) incorporation by postgate treatment was also implemented to further enhance the performance. Furthermore, bias temperature instability (BTI) characteristics were systematically investigated on interface engineered (Si-, SN-, or -passivated) Ge pMOSFETs by both conventional dc - and fast pulse measurement. The impact of thickness and postgate treatment processes (F incorporation) on BTI and device performance was also studied, and it is found that BTI and device performance can be improved by reducing the thickness or incorporating F.

High- k HfO 2–Ta 2O 5 mixed layers: Electrical characteristics and mechanisms of conductivity

Electrical properties of mixed HfO 2–Ta 2O 5 films (10;15 nm) deposited by rf sputtering on Si have been studied from the view point of their applications as high- k layers, by standard capacitance–voltage and temperature dependent current–voltage characteristics. The effect of HfO 2 addition to the Ta 2O 5 is thickness dependent and the thicker layers exhibit advantages over the pure Ta 2O 5 (higher dielectric constant, enhanced charge storage density and improved interface quality). The process of HfO 2 and Ta 2O 5 mixing introduces negative oxide charge, tends to creates shallow bulk traps and modifies the dominant conduction mechanisms in the stack capacitors as compared to the Ta 2O 5-based one (a contribution of tunneling processes through traps located below the conduction band of mixed layers to the leakage current in the HfO 2–Ta 2O 5 stacks is observed). The traps involved in both Poole–Frenkel and tunneling processes are identified.

Interfacial and electrical properties of SrBi2Ta2O9/ZrO2/Si heterostructures for ferroelectric memory devices

We have investigated the interfacial and frequency dependent electrical properties of metal-ferroelectric-insulator-semiconductor capacitors with SrBi2Ta2O9 (SBT) ferroelectric films grown on ZrO2 buffer layer coated Si. Heterostructure SBT and ZrO2 thin films were deposited using rf magnetron sputtering. Interfacial and surface roughness parameters of heterostructures were extracted from the simulation of specular x-ray reflectivity data. The structure exhibited clockwise capacitance-voltage hysteresis with a maximum memory window of 2.0 V at a bias voltage of ±7 V. Frequency dependent (5 kHz–1 MHz) measurements at room temperature indicated that the clockwise hysteresis originates from the ferroelectric domain reversal. A minimum leakage current density of 4×10−8 A/cm2 of fabricated capacitors at an applied voltage of ±5 V revealed that the ZrO2 buffer layer prevents the interfacial diffusion between SBT thin film and the substrate, resulting in an improvement of interface quality. The charge retention time of the ferroelectric capacitor was studied as a function of buffer layer thickness.