Improved Electromigration Performance Research Articles

Process Optimization for Electron Down-Flow Electromigration Improvement in Copper Interconnects

Due to asymmetric structure of Copper (Cu) interconnects, Cu electromigration (EM) is related to the electron flow direction. In various technological nodes, Cu EM performance with electron down-flow direction is generally worse than that with electron up-flow direction due to the presence of voiding underneath the via. This study investigates Cu EM behavior with electron down-flow. The failure modes were verified and optimized processes were provided to improve EM performance. Additionally, layout geometry effect on electron down-flow EM was discussed.

Full reliability study of advanced metallization options for 30nm ½pitch interconnects

Different metallization options that allow filling 30nm 1/2pitch interconnect trenches have been explored and their full reliability performance has been benchmarked to conventional PVD TaNTa/PVD Cu seed based metallizations. CVD Co as seed enhancement layer shows no deterioration in barrier performance and improved electromigration performance, but the activation energy for electromigration was 0.68+/-0.20eV, which is at the lower end of the expected value of 0.85-0.95eV for this parameter. When integrating our trenches in a k=3.2 non-porous SiCOH low-k material, PVD RuTa barriers with 90%Ru and 10%Ta show degraded barrier performance and significant lowering of activation energy for electromigration (0.59+/-0.05eV) while when using SiO2 as intermetal dielectric, no significant reliability deterioration is observed. Finally, it is shown that, using an optimized PVD Cu seed, standard PVD TaNTa-barriers give excellent barrier performance and that typical electromigration lifetime specs can be met with this metallization scheme down to 30nm 1/2pitch.

Comparison of Process Options for Improving Backend-of-Line Reliability in 28 nm Node Technologies and Beyond

This paper compares the most encouraging process options for improving electromigration performance in advanced technology nodes. Metal capping yields the best electromigration performance; however, this process is most challenging with respect to integration and may also suffer from significantly decreasing grain sizes in trench bottoms for future technologies. Alloying or silicidation techniques are less challenging to implement but can result in unacceptably high resistance increases. We analyze the respective results for each option and compare the performance on 45, 32, and 28 nm technology nodes. In addition, the impact of the various process options on stressmigration and time-dependent dielectric breakdown are discussed.

Comparison of Process Options for Improving Backend-of-Line Reliability in 28 nm Node Technologies and Beyond

This paper compares the most encouraging process options for improving electromigration performance in advanced technology nodes. Metal capping yields the best electromigration performance; however, this process is most challenging with respect to integration and may also suffer from significantly decreasing grain sizes in trench bottoms for future technologies. Alloying or silicidation techniques are less challenging to implement but can result in unacceptably high resistance increases. We analyze the respective results for each option and compare the performance on 45, 32, and 28 nm technology nodes. In addition, the impact of the various process options on stressmigration and time-dependent dielectric breakdown are discussed.

Current Challenges with Copper Interconnects

In the integrated circuit industry, aluminum-based interconnects and oxide interlayer dielectrics have been replaced with copper interconnects in a dual inlaid architecture and with low-K dielectrics. Inlaid Cu lines offer higher conductivity, improved electromigration performance and a reduced cost of manufacturing. In this manuscript, the current challenges with integrating Cu in high-performance integrated circuits are detailed. As technologies scale, the many steps in the integrated process flow cannot be viewed as independent. The interactions between process steps (module interactions) that must be considered will be discussed. The development of a reliable and manufacturable technology requires a fundamental understanding of these interactions. A process-oriented finite element model (FEM) will be presented to capture the effect of individual process steps on the stress evolution during processing. Finally, the future trends for Cu interconnect will be suggested.

Improved electromigration failure in Al based interconnects

AbstractElectromigration (EM) failure in Al interconnects is significantly improved by inserting a WN film between Al and the interlayer dielectric: over 90% of test samples failed with the Al/TiN/Ti interconnects, whereas the failure rate of the Al film on WN is reduced to less than 13% under the stress con‐ ditions of 9 MA/cm2 and 225 °C, and the EM lifetime is also much extended at the same conditions. Experimental results suggest that higher activation energy, no hillocks and compressive stress are responsible for the improved electromigration performance in the Al/WN interconnect. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Effect of surface treatment on electromigration in sub-micron Cu damascene interconnects

In sub-micron damascene Cu interconnects, electromigration is mainly due to diffusion at the interfaces of Cu with liner or dielectric cap layer. Many reports have shown Cu/dielectric cap as the dominant diffusion interface. Cu surface treatment after chemical mechanical polishing (CMP) can be a viable solution to improve electromigration performance of Cu damascene interconnects. In this study, NH 3 and H 2 plasma surface treatments were employed after CMP. These surface treatments can alter the Cu/dielectric interface and consequently influence the dominant Cu/dielectric cap interfacial electromigration. Cu damascene electromigration test structures, with sub-micron line-width, were employed in this investigation. Electromigration performance was assessed by package level electromigration tests and H 2 plasma surface treatment was found to significantly reduce electromigration.

Electromigration study of Al/low dielectric constant polymer and Al/SiO2 dioxide line structures

Electromigration reliability is a key concern for implementation of low dielectric constant (low κ) materials for on-chip interconnects. To address this problem, we have carried out a comparative study of electromigration performance for Al(0.5 wt% Cu) line structures formed with tetraethylorthosilicate (TEOS)-based SiO2 and a low κ polymeric dielectric, poly(arylene ether) (PAE). The test structures consisted of 800 μm long single-level line structures with adjacent extrusion monitor lines. Resistometric measurements were performed to measure electromigration lifetime. To supplement lifetime measurements, x-ray diffraction and transmission electron microscopy were used to measure overall grain size and grain orientation distributions, and electron backscattering diffraction was applied to determine local grain orientation and grain boundary characteristics. In addition, scanning electron microscopy was used to examine void morphology. Microstructural analysis has revealed a larger grain size and enhanced 〈111〉 texture in the PAE passivated Al lines compared to TEOS SiO2 passivated lines. The difference in microstructure is attributed to a high temperature process used to cure the PAE which is absent from the processing of the TEOS SiO2 samples. The improved electromigration performance can be attributed to the larger grain size and decreased grain misorientation in the PAE passivated lines.

Effect of TiN Anneal Ambient on The Microstructure and Electromigration Performance Of Al-Based Alloys

AbstractA strong correlation has been established between TiN substrate anneal ambient and electromigration performance of Al-based alloys. Excellent electromigration lifetimes were measured for AlSiCu (and AlCu) films on sputtered TiN substrates annealed in N2 and slowly cooled down in furnace. The films annealed in N2-O2 and N2-H2 showed poorer electromigration performance, in that order. Stronger Al (111) texture, larger median grain size and uniform grain size distribution have been responsible for the improved electromigration performance of the N2-annealed (furnace-cooled) films. On the contrary, Al alloy films on TiN substrates annealed in N2 (but air-cooled), N2-O2, or N2-H2 ambient showed weaker Al (111) textures and smaller median grain sizes.