Improve Device Reliability Research Articles

Evaluation of a Self-Administered Oral Glucose Tolerance Test

OBJECTIVETo assess the feasibility of using a disposable, self-administered, capillary blood sampling oral glucose tolerance test (OGTT) device in a community setting.RESEARCH DESIGN AND METHODSEighteen healthy and 12 type 2 diabetic volunteers underwent six 75-g OGTTs using a prototype device in the following three settings: unaided at home (twice); unaided but observed in clinic (twice); and performed by a nurse with simultaneous laboratory glucose assays of 0- and 120-min venous plasma samples (twice). The device displayed no results. A detachable data recorder returned to the clinic provided plasma-equivalent 0- and 120-min glucose values and key parameters, including test date, start and end times, and time taken to consume the glucose drink.RESULTSThe device was universally popular with participants and was perceived as easy to use, and the ability to test at home was well liked. Device failures meant that 0- and 120-min glucose values were obtained for only 141 (78%) of the 180 OGTTs performed, independent of setting. Device glucose measurements showed a mean bias compared with laboratory-measured values of +0.9 at 5.0 mmol/L increasing to +4.4 at 15.0 mmol/L. Paired device glucose values were equally reproducible across settings, with repeat testing showing no training effect regardless of setting order.CONCLUSIONSSelf-administered OGTTs can be performed successfully by untrained individuals in a community setting. With improved device reliability and appropriate calibration, this novel technology could be used in routine practice to screen people who might need a formal OGTT to confirm the presence of impaired glucose tolerance or diabetes.

DropBot: An open-source digital microfluidic control system with precise control of electrostatic driving force and instantaneous drop velocity measurement

We introduce DropBot: an open-source instrument for digital microfluidics (http://microfluidics.utoronto.ca/dropbot). DropBot features two key functionalities for digital microfluidics: (1) real-time monitoring of instantaneous drop velocity (which we propose is a proxy for resistive forces), and (2) application of constant electrostatic driving forces through compensation for amplifier-loading and device capacitance. We anticipate that this system will enhance insight into failure modes and lead to new strategies for improved device reliability, and will be useful for the growing number of users who are adopting digital microfluidics for automated, miniaturized laboratory operation.

Defect reduction in photon-accelerated negative bias instability of InGaZnO thin-film transistors by high-pressure water vapor annealing

We investigated the effects of high-pressure water vapor annealing (WHPA) under negative bias temperature illumination stress and light incidence on amorphous InGaZnO thin-film transistors. WHPA could improve device reliability and reduce the hump occurrence. It was attributed to the effective reduction and passivation in oxygen vacancies under WHPA. By comparing the experimental and technology computer-aided design simulation, we could confirm that the low-density of deep-donor-like oxygen vacancy (Vo) states near the valance band maximum contributed to the reduction of photo-excited single ionized oxygen vacancies (Vo+) and double ionized oxygen vacancies (Vo2+) as shallow-donor states near the conduction band minimum.

Physics of GaN-based Power Field Effect Transistors

Unique properties of GaN/AlN/InN heterostructures make them superior for high power applications. The key issues in the device designs are achieving normally-off operation, controlling the electric field distribution in the device channel to prevent breakdown, eliminating or reducing non-ideal effects causing reliability issues, and providing for efficient heat dissipation. High electric fields at the gate edges lead to an additional strain and hot electron effects causing the current collapse and gate lag. Quantum well designs (e.g. incorporating an InGaN or GaN quantum well between the wide band gap AlGaN barrier layer and GaN or AlGaN buffer) might control the wave function penetration and the real space transfer and increase the breakdown voltage. Insulated gate heterostructure HFETs (MOSHFETs) demonstrated superior performance and reliability. Field plates, recessed and double recessed gates, drain field controlled electrodes have been used to control current collapse and improve device reliability. An emerging approach is Frequency Configurable Electronics that enables better electric field uniformity.

Study Based on TMS320F2812 Synchronous Generator Field Regulator

This paper introduces the research on the Excitation Regulator of the Synchronous Generator with dual CPUs, based on Digital Signal Processor (TMS320LF2812). With the multiple functions of monitoring, analysis, controlling and protection, it overcomes the shortage of the domestic excitation device in terms of self-monitoring and self-protection，which effectively improves device reliability. By analyzing the allocation of reactive load of the interconnected Synchronous Motor group, the modeling and simulation of the digital excitation regulator in the power system are illustrated in the paper. The results of the simulation show that the proposed regulation model are feasible, satisfying various running demands of the Synchronous Motor and Power System.

Reduction of Power Consumption in FPGAs - An Overview

Field Programmable Gate Arrays FPGAs are highly desirable for implementation of digital systems due to their flexibility, programmability and low end product life cycle. In more than 20 years since the introduction of FPGA, research and development has produced dramatic improvements in FPGA speed and area efficiency, narrowing the gap between FPGAs and ASICs and making FPGAs the platform of choice for implementing digital circuits. FPGAs hold significant promise as a fast to market replacement. Unfortunately, the advantages of FPGAs are offset in many cases by their high power consumption and area. The goal is to reduce the power consumption without sacrificing much performance or incurring a large chip area so that the territories of FPGAs applications can expand more effectively. Reducing the power of FPGAs is the key to lowering packaging and cooling costs, improving device reliability, and opening the door to new markets such as mobile electronics. This paper presents the tips to lower down the static and dynamic power dissipation in FPGAs. It gives an overview of various techniques at system, device, and circuit and architecture level used for reduction of power consumption of FPGAs and their outcomes.

Field plate related reliability improvements in GaN-on-Si HEMTs

State of the art GaN on Silicon HEMTs fabricated with and without a field-plate structure have been tested by means of DC and RF reliability tests. The introduction of the field-plate structure greatly improves device reliability both during DC as well as RF testing. Results are thus suggesting that reliability in NOFP and FP devices is mainly limited by the high electric fields within the device structure causing an increase in traps concentration.

제조 공정의 개선을 통한 백색 LED 칩의 성능 개선

LED는 저 전력, 긴 수명, 고 휘도, 빠른 응답, 친환경적인 특성의 여러 장점을 갖고 있기 때문에 청색과 녹색 LED는 교통신호, 옥외 디스플레이, 백색 LED는 LCD 후면광 등의 응용 제품에 사용되고 있다. 여기서 LED의 성능을 향상하기 위하여 출력전력과 소자의 신뢰성을 높이고, 동작전압을 낮추어야 LED 칩의 고효율화가 이루어져야 하는데, 이는 에피택셜층, 표면요철, 패턴이 있는 사파이어 기판, 칩 설계의 최적화, 특수 공정의 개선 등의 기술이 우수해야 한다. 본 연구에서는 측면 에칭 기술과 절연층 삽입기술을 이용하여 사파이어 에피 웨이퍼 위에 GaN-기반 백색 LED 칩을 제작하여 그 성능을 조사하였다. LED 칩의 성능을 개선하기 위한 최적화 설계와 CBL(current blocking layer) 삽입 기술의 개선된 공정을 통하여 LED 칩 성능의 향상을 확인할 수 있었으며, 출력 전력은 광 출력 7cd, 순방향 인가전압 3.2V의 값을 얻었다. 현재의 LCD 후면광원으로 사용되고 있는 LED 칩의 출력에 비하여 성능이 개선되었으며, 의료기기 및 LCD LED TV의 후면광원으로 사용할 수 있을 것으로 기대된다. LEDs are using widely in a field of illumination, LCD LED backlight, mobile signals because they have several merits, such as low power consumption, long lifetime, high brightness, fast response, environment friendly. To achieve high performance LEDs, one needs to enhance output power, reduce operation voltage, and improve device reliability. In this paper, we have proposed that the optimum design and specialized process could improve the performance of LED chip. It was showed an output power of 7cd and input supplied voltage of 3.2V by the insertion technique of current blocking layer. In this paper, GaN-based LED chip which is built on the sapphire epi-wafer by selective MOCVD were designed and developed. After that, their performances were measured. It showed the output power of 7cd more than conventional GaN-based chip. It will be used the lighting source of a medical equipment and LCD LED TV with GaN-based LED chip.

A Darlington-Enhanced CMOS Oscillator Architecture

A fully differential CMOS oscillator using Darlington composite pMOS transistors is presented. The composite transistor structure increases gain of the negative-Gm stage for a reliable startup and improves device reliability due to use of high-voltage transistors. To achieve good phase noise available with large voltages and the speed of small active devices in a modern CMOS process, a higher (2.8 V) power supply requiring a combination of low- and high-voltage transistors is used. In addition, the oscillator uses negative feedback to reduce amplitude variation due to <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$LC$</tex></formula> -tank loading. Circuit functionality is confirmed with a test circuit fabricated in a standard 130-nm CMOS process. The oscillator reaches a phase noise better than <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex></formula> 121.2 dBc/Hz at 1-MHz offset across a tuning range of 3015 to 5298 MHz while consuming a less than 10.6-mA current from a 2.8-V power supply.

Investigation of the Origin of $V_{T}/V_{\rm FB}$ Modulation by $\hbox{La}_{2}\hbox{O}_{3}$ Capping Layer Approaches for NMOS Application: Role of La Diffusion, Effect of Host High- $k$ Layer, and Interface Properties

The role of La <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> capping in the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</sub> shift with various high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> and metal gate electrodes was systematically investigated. It was found that the La concentration at the high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface is mainly responsible for the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</sub> modulation in NMOS devices, whereas the effect of the host high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> and gate electrodes on <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</sub> is minimal. A 400-mV shift in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</i> from the control HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> device with minimal degradation in mobility was obtained when a La <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> layer was inserted between the high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> and SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layers. It was also found that the incorporation of La <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> in the dielectric stack improves device reliability in terms of breakdown and positive-bias temperature instability characteristics. The main key for the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</sub> shift is the ability of La diffusion through the host high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> material.

Fabrication of Capacitive Micromachined Ultrasonic Transducers via Local Oxidation and Direct Wafer Bonding

We present the successful fabrication of capacitive micromachined ultrasonic transducers (CMUTs) with an improved insulation layer structure. The goal is to improve device reliability (electrical breakdown) and device performance (reduced parasitic capacitance). The fabrication is based on consecutive thermal oxidation steps, on local oxidation of silicon (LOCOS), and on direct wafer bonding. No chemical-mechanical polishing step is required during the device fabrication. Aside from the advantages associated with direct wafer bonding for CMUT fabrication (simple fabrication, cell shape flexibility, wide gap height range, good uniformity, well-known material properties of single-crystal materials, and low intrinsic stress), the main vertical dimension (electrode separation) is determined by thermal oxidation only, which provides excellent vertical tolerance control ( <;10 nm) and unprecedented uniformity across the wafer. Thus, we successfully fabricated CMUTs with gap heights as small as 40 nm with a uniformity of ±2 nm over the entire wafer. This paper demonstrates that reliable parallel-plate electrostatic actuators and sensors with gap heights in the tens of nanometer range can be realized via consecutive thermal oxidation steps, LOCOS, and direct wafer bonding without chemical-mechanical polishing steps.

The impact of SiNx gate insulators on amorphous indium-gallium-zinc oxide thin film transistors under bias-temperature-illumination stress

The threshold voltage instability (Vth) in indium-gallium-zinc oxide thin film transistor was investigated with disparate SiNx gate insulators under bias-temperature-illumination stress. As SiNx film stress became more tensile, the negative shift in Vth decreased significantly from −14.34 to −6.37 V. The compressive films exhibit a nitrogen-rich phase, higher hydrogen contents, and higher N–H bonds than tensile films. This suggests that the higher N–H related traps may play a dominant role in the degradation of the devices, which may provide and/or generate charge trapping sites in interfaces and/or SiNx insulators. It is anticipated that the appropriate optimization of gate insulator properties will help to improve device reliability.

69.2: Highly Reliable Oxide‐Semiconductor TFT for AM‐OLED Display

AbstractWe developed highly reliable oxide semiconductor TFT for AM‐ OLED displays. Passivating films, source/drain metals, and the TFT structure were optimized with an eye to improving device reliability to provide a lifetime over 10 years. An 11.7‐inch diagonal qHD AM‐OLED display was demonstrated to provide applicable solution for a large size OLED and an ultra‐high definition LCD TV mass‐production.

Software Assisted Digital RF Processor (DRP™) for Single-Chip GSM Radio in 90 nm CMOS

This paper proposes and describes a new software and application programming interface view of an RF transceiver. It demonstrates benefits of using highly programmable digital control logic in an RF wireless system realized in a digital nanoscale CMOS process technology. It also describes a microprocessor architecture design in Digital RF Processor (DRP <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TM</sup> ) and how it controls calibration and compensation for process, temperature and voltage variations of the analog and RF circuits to meet the required RF performance. A few calibration examples to reduce a DCO bias current and improve device reliability, as well as to optimize transmit modulation and receive performance, are given. The presented circuits and techniques have enabled successful implementation of a commercial single-chip GSM radio in 90 nm CMOS.

Effects of Contacting Surfaces on MEMS Device Reliability

A multi-asperity contact model with adhesion is presented to analyze the real contact of microdevices, including contact force, contact area, and pull-off force. Since the macroscopic contact of two contacting surfaces is the statistical average of many individual micro/nano contacts, the key point is to include an accurate analysis of the discrete contacts. A finite element model which is applicable to a wide range of material properties was developed to study adhesion and plasticity of a single contact during both loading and unloading cycles in a previous investigation. The best fits of the results by comparing with the existing models are introduced in this work for both the loading and unloading (pull-off force) analyses. Pearson Type distributions which can independently adjust the skewness and kurtosis of surface heights are used to study the multi-asperity contact. The significance of this work is not only to predict adhesion of the existing devices, but to provide an optimal design of surface characteristics and material properties to improve device reliability. An overview of the status of surface roughening indicates that various techniques exist to tailor surface morphological properties, but that these techniques mainly target the mean and root-mean-square (rms) values of the roughness. This approach insufficiently utilizes all available techniques to minimize adhesion force between surfaces. New approaches that include surface roughness process development should include a range of skewness and kurtosis values of the resulting surface as a design consideration in addition to the mean and rms values of the roughness.

Donation of explanted pacemakers for reuse in underserved nations

Some charitable organizations and physicians are willing to assist in the compassionate donation of explanted pacemakers for reuse in medically underserved nations. However, healthcare organizations must recognize that the Food and Drug Administration (FDA), device manufacturers, professional societies and many physicians advocate return of explanted pacemakers to the manufacturer to ensure an accurate performance database promoting improved device reliability and safety for the patient.

A three-terminal spin-torque-driven magnetic switch

A three-terminal spin-torque-driven magnetic switch is experimentally demonstrated. The device uses nonlocal spin current and spin accumulation as the main mechanism for current-driven magnetic switching. It separates the current-induced write operation from that of a magnetic tunnel junction based read. The write current only passes through metallic structures, improving device reliability. The device structure makes efficient use of lithography capabilities, important for robust process integration.

Reliability of InP-based HBTs at High Current Density

AbstractInP-based HBTs for ultrahigh speed optical communications systems operation at over 40 GHz require a long-term stability under high current injection conditions, such as current densities of 2 or 5 mA/μm2. We achieved high reliability by suppressing surface recombination and emitter-metal-related crystalline degradation.Changes in the electric properties of devices due to temperature and bias stress were evaluated. The reduction in DC current gain due to surface recombination had the activation energy of 1.7 eV without current density dependence, and the lifetime of HBTs for this degradation mode is predicted to be over 1×108 hours at 125°C. The emitter metal diffusion and disruption of uniformity of the atomic composition were observed by transmission electron microscopy and energy dispersive X-ray spectroscopy in HBTs with the conventional Ti/Pt/Au emitter, whereas suppression of those degradations was observed in HBTs with refractory metal of Mo and W. The emitter resistance was estimated to evaluate the contact layer degradation. The critical time was one order larger for HBTs with refractory metal than for HBTs with conventional metal. The activation energies for resistance increases were 2.0 and 1.65 eV for the current density of 2 and 5 mA/μm2, respectively, for all types of emitter electrodes.The effectiveness of the refractory metal electrode for improving device reliability was confirmed, especially in high-current-density operation, which is essential for applying InP HBTs in high-speed ICs.

Improved electrical properties of Ge metal-oxide-semiconductor capacitor with HfTa-based gate dielectric by using TaOxNy interlayer

HfTa-based oxide and oxynitride with or without TaOxNy interlayer are fabricated on Ge substrate to form metal-oxide-semiconductor (MOS) capacitors. Their electrical properties and reliabilities are measured and compared. The results show that the MOS capacitor with a gate stack of HfTa-based oxynitride and thin TaOxNy interlayer exhibits low interface-state/oxide-charge densities, low gate leakage, small hysteresis, small capacitance equivalent thickness (∼0.94nm), and high dielectric constant (∼24). All these should be attributed to the blocking role of the TaOxNy interlayer against penetration of O into the Ge substrate and interdiffusions of Hf, Ge, and Ta, thus effectively suppressing the formation of unstable low-k GeOx and giving a superior TaOxNy∕Ge interface. Moreover, incorporation of N into both the interlayer and high-k dielectric greatly improves device reliability through the formation of strong N-related bonds.

Short-Channel Characteristics of Self-Aligned $\Pi$-Shaped Source/Drain Ultrathin SOI MOSFETs

A novel device architecture-the self-aligned pi-shaped source/drain (S/D) ultrathin silicon-on-insulator (UTSOI) FET-is presented for the first time in the field of silicon-on-insulator (SOI) technology; this new device demonstrates how to decrease the self-heating effects in the SOI-based devices. Two-dimensional simulations show that the cost of building an S/D tie into the UTSOI-FET is a modest degradation of the short-channel characteristics including drain-induced barrier lowering (DIBL) and subthreshold swing (SS), when compared with a traditional UTSOI-FET. This degradation occurs because the S/D-tied scheme introduces two additional pathways between the S/D regions and the silicon substrate, thereby reducing the gate's ability to control the channel. Yet, the results presented here show these negative effects to be reasonably small (e.g., DIBL ang 90 mV/V and SS ang 100 mV/dec), whereas the positive effect of reduced self-induced heating is substantial and significantly improves device reliability.