Improve Application Performance Research Articles

Detecting Bogus Information Attack in Vehicular Ad Hoc Network: A Context-Aware Approach

Most of Vehicular Ad Hoc Network’s (VANET) and Fly Ad Hoc Network (FANET) applications, protocols, and service rely on cooperativeness among network participants. Vehicles, could be unmanned aerial vehicles (e.g. drones), share their sensors’ information to improve network performance and provide safety, traffic efficiency, and entertainments. The accuracy and reliability of this information are vital for VANET performance. However, misbehaving (or faulty) vehicles, which exploit the cooperativeness feature by sharing bogus information, can disrupt the fundamental operations of any potential application and cause loss of people lives and properties. Unfortunately, existing detection approaches cannot effectively thwart such attacks. The highly dynamic vehicular context has been vastly neglected as well as they rely on predefined and static security perimeters to differentiate between false and correct information. In this paper, a context-aware detection approach is proposed to improve the detection accuracy and reduce the false alarm rate. Firstly, the features that well represent the vehicular context has been extracted. Then, an online unsupervised learning method namely the hierarchical clustering algorithm is used to classify the received messages into either genuine or spurious. Finally, Bayesian-based hypothesis testing has been used to confirm the validity of the classification. Results show that the proposed detection approach is promising in effectively detect bogus information attack and improve applications performance.

Application Partitioning for Offloading in Mobile Pervasive Environments

In this work, we proposed an algorithm to partition an application for offloading into exactly two clusters. One for local execution on the resource constraint mobile device and other one for remote execution on another device such as smartphone, laptop, desktop and so on. The aim is to reduce energy usage on the source mobile device and improve response time. The evaluation results show an overall application performance improvement, in terms of response time and energy consumption, of the proposed algorithm compared to a no offloading and full offloading strategy. We note that high bandwidth and remote devices with higher computational speed benefits offloading while in low connectivity, a no offloading approach is better.

An experimental evaluation of garbage collectors on big data applications

Popular big data frameworks, ranging from Hadoop MapReduce to Spark, rely on garbage-collected languages, such as Java and Scala. Big data applications are especially sensitive to the effectiveness of garbage collection (i.e., GC), because they usually process a large volume of data objects that lead to heavy GC overhead. Lacking in-depth understanding of GC performance has impeded performance improvement in big data applications. In this paper, we conduct the first comprehensive evaluation on three popular garbage collectors, i.e., Parallel, CMS, and G1, using four representative Spark applications. By thoroughly investigating the correlation between these big data applications' memory usage patterns and the collectors' GC patterns, we obtain many findings about GC inefficiencies. We further propose empirical guidelines for application developers, and insightful optimization strategies for designing big-data-friendly garbage collectors.

Characterizing Dynamic Load Balancing in Cloud Environments Using Virtual Machine Deployment Models

The ever growing computational demands of users call for efficient cloud resource management to avoid service-level agreement (SLA) violation. Virtualization co-locates multiple virtual machines (VMs) on a single physical server to share the underlying resources for efficient resource management. However, the decision about “what” and “where” to place workloads significantly impacts performance of hosted workloads. Existing cloud schedulers consider a single resource (RAM) to co-locate workloads that as a result lead to SLA violation due to non-optimal VM placement. To handle this issue, current study has updated nova scheduler to propose a multi-resource based VM placement approach to improve application performance in terms of central processing unit (CPU) utilization and execution time. Experimentally we have shown that our proposed method has lessened application execution time by 50% when compared with one of the well-known technique.

Integrating blocking and non-blocking MPI primitives with task-based programming models

In this paper we present the Task-Aware MPI library (TAMPI) that integrates both blocking and non-blocking MPI primitives with task-based programming models. The TAMPI library leverages two new runtime APIs to improve both programmability and performance of hybrid applications. The first API allows to pause and resume the execution of a task depending on external events. This API is used to improve the interoperability between blocking MPI communication primitives and tasks. When an MPI operation executed inside a task blocks, the task running is paused so that the runtime system can schedule a new task on the core that became idle. Once the blocked MPI operation is completed, the paused task is put again on the runtime system’s ready queue, so eventually it will be scheduled again and its execution will be resumed.The second API defers the release of dependencies associated with a task completion until some external events are fulfilled. This API is composed only of two functions, one to bind external events to a running task and another function to notify about the completion of external events previously bound. TAMPI leverages this API to bind non-blocking MPI operations with tasks, deferring the release of their task dependencies until both task execution and all its bound MPI operations are completed.Our experiments reveal that the enhanced features of TAMPI not only simplify the development of hybrid MPI+OpenMP applications that use blocking or non-blocking MPI primitives but they also naturally overlap computation and communication phases, which improves application performance and scalability by removing artificial dependencies across communication tasks.

Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip

Dark silicon is the phenomenon that a fraction of many-core chip has to be turned off or run in a low-power state in order to maintain the safe chip temperature. System-level thermal management techniques normally map application on non-adjacent cores, while communication efficiency among these cores will be oppositely affected over conventional network-on-chip (NoC). Recently, SMART NoC architecture is proposed, enabling single-cycle multi-hop bypass channels to be built between distant cores at runtime, to reduce communication latency. However, communication efficiency of SMART NoC will be diminished by communication contention, which will in turn decrease system performance. In this paper, we first propose an Integer-Linear Programming (ILP) model to properly address communication problem, which generates the optimal solutions with the consideration of inter-processor communication. We further present a novel heuristic algorithm for task mapping in dark silicon many-core systems, called TopoMap , on top of SMART architecture, which can effectively solve communication contention problem in polynomial time. With fine-grained consideration of chip thermal reliability and inter-processor communication, presented approaches are able to control the reconfigurability of NoC communication topology in task mapping and scheduling. Thermal-safe system is guaranteed by physically decentralized active cores, and communication overhead is reduced by the minimized communication contention and maximized bypass routing. Performance evaluation on PARSEC shows the applicability and effectiveness of the proposed techniques, which achieve on average 42.5 and 32.4 percent improvement in communication and application performance, and 32.3 percent reduction in system energy consumption, compared with state-of-the-art techniques. TopoMap only introduces 1.8 percent performance difference compared to ILP model and is more scalable to large-size NoCs.

A Raster Data Framework Based on Distributed Heterogeneous Cluster

Advancements in satellite imaging and sensor technologies result in capturing of large amount of spatial data. Many parallel processing techniques based on data or control parallelism have been attempted during the past 2 decades to provide performance improvement in image processing applications such as urban sprawl, weather prediction and crop estimation. These techniques have used block-based distributed file processing or the more modern MapReduce-based programming for implementation which still have gaps between optimal and best processing in terms of resource scheduling, data distribution and ease of programming. In this paper, we present a layered framework for parallel data processing to improve storage, retrieval and processing performance of spatial data on an underlying distributed file system. The paper presents a data placement strategy across a distributed HDFS cluster in a way to optimize spatial data retrieval and processing. The presence of neighborhood pixels local to the processing node in a distributed environment reduces network latencies and improves the efficiency of applications such as object recognition, change detection and site selection. We evaluate the data placement strategy on a four-node HDFS cluster and show that it can deliver good performance benefits by way of reading blocks of data at almost 10–12 times the default, which contributes to the improvement in efficiency of the various applications that use region growing methods.

RAPID: Memory-Aware NoC for Latency Optimized GPGPU Architectures

The growing parallelism in most of today's applications has led to an increased demand for parallel computing in processors. General Purpose Graphics Processing Units (GPGPUs) have been used extensively to support highly parallel applications in recent years. Such GPGPUs generate huge volumes of network traffic between memory controllers (MCs) and shader cores. As a result, the network-on-chip (NoC) fabric can become a performance bottleneck, especially for memory intensive applications running on GPGPUs. Traditional mesh-based NoC topologies are not suitable for GPGPUs as they possess high network latency that leads to congestion at MCs and an increase in application execution time. In this article, we propose a novel memory-aware NoC that has two (request and reply) planes tailored to exploit the traffic characteristics in GPGPUs. The request layer consists of low power, and low latency routers that are optimized for the many-to-few traffic pattern. In the reply layer, flits are sent on fast overlay circuits to reach their destinations in just three cycles (at 1 GHz). In addition, as traditional memory controllers are not aware of the application memory intensity that leads to higher waiting time for applications on the shader cores, we propose an enhanced memory controller that prioritizes burst packets to improve application performance on GPGPUs. Experimental results indicate that our framework yields an improvement of ${\mathrm{4}}-{\mathrm{10}}\times$ in NoC latency, up to 63 percent in execution time, and up to 4× in total energy consumption compared to the state-of-the-art.

The unexpected virtue of almost: Exploiting MPI collective operations to approximately coordinate checkpoints

SummaryCoordinated checkpoint/restart is currently the dominant approach to mitigating the impact of failures on important scientific applications running on large‐scale distributed systems. However, there is widespread evidence that coordinated checkpointing may no longer be viable on next‐generation systems. Uncoordinated checkpoint/restart attempts to address the shortcomings of coordinated checkpoint/restart by allowing application processes to checkpoint their state independently. However, eliminating coordination may significantly degrade application performance. In this paper, we propose an approach that leverages existing coordination in important scientific applications to approximately coordinate checkpoints. Specifically, we propose to extend MPI implementations to force checkpoints to occur immediately after the completion of a collective operation. We evaluate the performance implications of this approach using an existing validated simulation framework. Our results demonstrate that approximately coordinated checkpointing can significantly improve application performance relative to totally uncoordinated checkpointing. We also show that forcing checkpoints to occur following a collective operation has a small impact on the nominal checkpoint interval for several important workloads. As a whole, the results presented in this paper demonstrate that approximately coordinated checkpointing may provide significant performance benefits without significantly increasing the cost of failure recovery.

NeMo

Neuromorphic computing is a broad category of non–von Neumann architectures that mimic biological nervous systems using hardware. Current research shows that this class of computing can execute data classification algorithms using only a tiny fraction of the power conventional CPUs require. This raises the larger research question: How might neuromorphic computing be used to improve application performance, power consumption, and overall system reliability of future supercomputers? To address this question, an open-source neuromorphic processor architecture simulator called NeMo is being developed. This effort will enable the design space exploration of potential heterogeneous compute systems that combine traditional CPUs, GPUs, and neuromorphic hardware. This article examines the design, implementation, and performance of NeMo . Demonstration of NeMo ’s efficient execution using 2,048 nodes of an IBM Blue Gene/Q system, modeling 8,388,608 neuromorphic processing cores is reported. The peak performance of NeMo is just over ten billion events-per-second when operating at this scale.

Morpheus

In modern computing systems, object deserialization can become a surprisingly important bottleneck-in our test, a set of generalpurpose, highly parallelized applications spends 64% of total execution time deserializing data into objects. This paper presents the Morpheus model, which allows applications to move such computations to a storage device and bypass the overhead on the host system. We use this model to deserialize data into application objects inside storage devices, rather than in the host CPU. Using the Morpheus model for object deserialization avoids unnecessary system overheads, frees up scarce CPU and main memory resources for compute-intensive workloads, saves I/O bandwidth, and reduces power consumption. In heterogeneous, coprocessor- equipped systems, Morpheus allows application objects to be sent directly from a storage device to a co-processor (e.g., a GPU) by peer-to-peer transfer, further improving application performance as well as reducing the CPU and main memory utilizations. This paper implements Morpheus-SSD, an SSD supporting the Morpheus model. Morpheus-SSD improves the performance of object deserialization by 1.66x, reduces power consumption by 7%, uses 42% less energy, and speeds up the total execution time by 1.32x. By using NVMe-P2P that realizes peer-to-peer communication between Morpheus-SSD and a GPU, Morpheus-SSD can speed up the total execution time by 1.39x in a heterogeneous computing platform.

Hardware topology management in MPI applications through hierarchical communicators

The MPI standard is a major contribution in the landscape of parallel programming. Since its inception in the mid 90s it has ensured portability and performance for parallel applications on a wide spectrum of machines and architectures. With the advent of multicore machines, understanding and taking into account the underlying physical topology and memory hierarchy have become of paramount importance. On the other hand, providing abstract mechanisms to manipulate the hardware topology is also fundamental. The MPI standard in its current state, however, and despite recent evolutions is still unable to offer mechanisms to achieve this. In this paper, we detail several additions to the standard for building new MPI communicators corresponding to hardware hierarchy levels. It provides the user with tools to address hardware topology and locality issues while improving application performance.

STRATEGI PEMANFAATAN APLIKASI DESA APPS DALAM LITERASI INFORMASI PERTANIAN

Information literacy is one part of community empowerment activities, especially in the information field. Information literacy is the ability to search, evaluate, and use information needed effectively. Basically information literacy is not a new ability or skill, but in the era of information disclosure, information literacy is a must-have skill requirement. The problems faced today, there is still an imbalance between the pace of information available and the level of agricultural information literacy at the farm level. The development of agricultural information through the internet has led to cyber extensions, information is available quickly and varied, but not all farmers are able to access and use it. The Faculty of Agriculture UGM has developed an application with the name DesaApps. DesaApps stands for Digital Extension Society for Agriculture Application which aims to be an application platform that provides agricultural counseling and develops a digital farming community. The existence of DesaApps can be useful for users of the application to provide information to one another, interact and transact in agriculture. The features in the DesaApps application consist of Frequently Asked Questions, Articles, Price Information, Farm Notes, Weather Information. Shop Information, Office Information, and Selling Items. Utilization of the features provided by Desa Apps provides an opportunity for farmers to obtain the information needed, as well as a means of improving the skills of managing information obtained. Therefore, the presence of Desa Apps empowers farmers to be independently informed. However, the performance of Desa Apps as one of the sources of information still needs to be improved. In order to be able to optimize the use of Village Apps, the utilization strategy is to improve application performance, promote and promote Village Apps, responsiveness of experts, and optimize the use of Desa Apps as a marketing place.

Multi-model ensemble hydrological simulation using a BP Neural Network for the upper Yalongjiang River Basin, China

Abstract. Hydrological models are important and effective tools for detecting complex hydrological processes. Different models have different strengths when capturing the various aspects of hydrological processes. Relying on a single model usually leads to simulation uncertainties. Ensemble approaches, based on multi-model hydrological simulations, can improve application performance over single models. In this study, the upper Yalongjiang River Basin was selected for a case study. Three commonly used hydrological models (SWAT, VIC, and BTOPMC) were selected and used for independent simulations with the same input and initial values. Then, the BP neural network method was employed to combine the results from the three models. The results show that the accuracy of BP ensemble simulation is better than that of the single models.

DarkCache

The Last Level Cache (LLC) is a key element to improve application performance in multi-cores. To handle the worst case, the main design trend employs tiled architectures with a large LLC organized in banks, which goes underutilized in several realistic scenarios. Our proposal, named DarkCache , aims at properly powering off such unused banks to optimize the Energy-Delay Product (EDP) through an adaptive cache reconfiguration, thus aggressively reducing the leakage energy. The implemented solution is general and it can recognize and skip the activation of the DarkCache policy for the few strong memory intensive applications that actually require the use of the entire LLC. The validation has been carried out on 16- and 64-core architectures also accounting for two state-of-the-art methodologies. Compared to the baseline solution, DarkCache exhibits a performance overhead within 2% and an average EDP improvement of 32.58% and 36.41% considering 16 and 64 cores, respectively. Moreover, DarkCache shows an average EDP gain between 16.15% (16 cores) and 21.05% (64 cores) compared to the best state-of-the-art we evaluated, and it confirms a good scalability since the gain improves with the size of the architecture.

A Stochastic Control Approach to Maximize Profit on Service Provisioning for Mobile Cloudlet Platforms

The recent emergence of mobile cloud computing has enabled mobile users to offload computing tasks from mobile devices to nearby cloudlets, so as to reduce energy consumption and improve application performance. In this paper, we consider the problem of maximizing the profit of the cloudlets’ managing platform that receives computing requests from mobile users and fulfils these requests by leveraging computing service of participating cloudlets. However, it is very challenging to maximize the operating profit for such a managing platform, due to unpredictable arrival of user requests, dynamic participation of mobile cloudlets, and complexity in computing resource allocations. Based on the Lyapunov optimization technique combined with the technique of weight perturbation, we introduce a new stochastic control algorithm that makes online decisions on computing request admission and dispatching, computing service purchasing, and computing resource allocation. Different from traditional techniques, this algorithm does not require any statistical knowledge of relevant system dynamics, and is efficient for implementation in practice. Theoretical analysis and simulation results have demonstrated both the profit optimality and the system stability achieved by the proposed control algorithm.

Making Huge Pages Actually Useful

The virtual-to-physical address translation overhead, a major performance bottleneck for modern workloads, can be effectively alleviated with huge pages. However, since huge pages must be mapped contiguously, OSs have not been able to use them well because of the memory fragmentation problem despite hardware support for huge pages being available for nearly two decades. This paper presents a comprehensive study of the interaction of fragmentation with huge pages in the Linux kernel. We observe that when huge pages are used, problems such as high CPU utilization and latency spikes occur because of unnecessary work (e.g., useless page migration) performed by memory management related subsystems due to the poor handling of unmovable (i.e., kernel) pages. This behavior is even more harmful in virtualized systems where unnecessary work may be performed in both guest and host OSs. We present Illuminator, an efficient memory manager that provides various subsystems, such as the page allocator, the ability to track all unmovable pages. It allows subsystems to make informed decisions and eliminate unnecessary work which in turn leads to cost-effective huge page allocations. Illuminator reduces the cost of compaction (up to 99%), improves application performance (up to 2.3x) and reduces the maximum latency of MySQL database server (by 30x). Importantly, this work shows the effectiveness of a simple solution for long-standing huge page related problems.

IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs

GPGPU accelerated computing has revolutionized a broad range of applications. To serve between the ever-growing computing capability and external memory, the on-chip memory is becoming increasingly important to GPGPU performance for general-purpose computing. Inherited from the traditional CPUs, however, the contemporary GPGPU on-chip memory design is suboptimal to the SIMT (single instruction, multiple threads) execution. In particular, the on-chip first-level data (L1D) cache thrashing, resulting from insufficient capacity and imbalanced usage, leads to a low hit rate and limits the overall performance. In this study, we reform the contemporary on-chip memory design and propose an integrated and balanced on-chip memory (IBOM) architecture for high-performance GPGPUs. It first virtually enlarges the L1D cache size by an integrated architecture that exploits the under-utilized register file (RF) with lightweight ISA, compiler and microarchitecture supports. Then with sufficient capacity, it is able to improve the cache usage by a set balancing technique that exploits the under-utilized set resources. In our proposed IBOM design, the register and cache accesses are amenable to normal pipeline operations with simple changes. It adequately exploits the size inversion in GPGPU on-chip memory, and enables optimized utilization of the precious resources for higher performance and energy efficiency with even smaller on-chip memory size. The experiment results demonstrate that the proposed IBOM design can offer an average of 29.6 percent increase in L1D hit rate and in turn 3X performance improvement for the cache-sensitive applications.

Improving Application Performance of in situ Polymerization and Crosslinking System of Maleic Acid/Itaconic Acid for Cotton Fabric

Maleic acid (MA) and itaconic acid (IA) used as crosslinking agents for cotton fabrics are more cost-effective than the most efficient nonformaldehyde crosslinker 1,2,3,4-butanetetracarboxylic acid (BTCA), but poor stability of finishing bath and fabric yellowing are the main disadvantage of MA/IA in situ polymerization and crosslinking system. In this research, the application performance improvement of MA/IA crosslinking system for cotton fabrics was studied. Replacement of the widely used sodium hypophosphite (SHP) with potassium hypophosphite (PHP) as catalyst allowed for obtaining a stable finishing bath under ambient temperature and led to improved final durable press (DP) performance of the treated fabrics. The influences of PHP concentration, curing temperature, and curing time on the performance of finished fabrics were investigated. Cotton fabrics treated by MA/IA/PHP crosslinking system exhibited comparable DP performance and laundering durability to that finished with BTCA. To address the fabric yellowing problem, the residual MA and IA attached on the treated fabrics by single-ended ester linkage was determined by HPLC. The data indicated that the degree of fabric yellowing was linearly related to the unpolymerized carboxylic acid MA and IA concentration on the treated fabrics. Several approaches were explored to improve the whiteness of MA/IA/PHP crosslinked fabrics. It was found that steam drying with 30-50 % humidity could effectively improve fabric whiteness. The findings of this study have significant implications for better application of unsaturated polycarboxylic acids in crosslinking of cellulose.

Reordering Transaction Execution to Boost High-Frequency Trading Applications

High-frequency trading (HFT) has always been welcomed because it benefits not only personal benefits but also the whole social welfare. While the recent advance of portfolio selection in HFT market enables to bring about more profit, it yields much contended OLTP workloads. Featuring exploiting the abundant parallelism, transaction pipeline, the state-of-the-art concurrency control (CC) mechanism, however, suffers from limited concurrency confronted with HFT workloads. Its variants that enable more parallel execution by leveraging fine-grained contention information also take little effect. To solve this problem, we for the first time observe and formulate the source of restricted concurrency as harmful ordering of transaction statements. To resolve harmful ordering, we propose PARE, a pipeline-aware reordered execution, to improve application performance by rearranging statements in order of their degrees of contention. In concrete, two mechanisms are devised to ensure the correctness of statement rearrangement and identify the degrees of contention of statements, respectively. We also study the off-line reordering problem. We prove that this problem is NP-hard and present an off-line reordering approach to approximate the optimal reordering strategy. Experiment results show that PARE can improve transaction throughput and reduce transaction latency on HFT applications by up to an order of magnitude than the state-of-the-art CC mechanism.