Implementation Of Image Processing Algorithms Research Articles

Real-time disparity map computation using the cell broadband engine

In this paper, we present what we believe to be the first implementation of a disparity map computation algorithm, using a local block-based matching technique, on the Cell Broadband Engine, a new processor released by Sony, Toshiba and IBM. The paper discusses the architecture of the Cell Broadband Engine from an image processing perspective. The results of the implementation are also presented and compared to the results obtained using desktop processing devices such as CPUs and GPUs, and shows that the computational power of the Cell Broadband Engine can be used to implement image processing algorithms in real-time.

Fast Implementation of Image Processing Algorithm Based on DSP

In this article, the image processing algorithm can quickly become a DSP execution program and run immediately by using Model-Based Design method. As an example, it shows how to design and implement a vehicle detecting and tracking algorithm on TDS642EVM. The experiment proves that this method realizes the integration from design to implementing, and shortens the developing period of image processing algorithm greatly.

Towards Vision-Based Autonomous Landing for Small Unmanned Air Vehicles: Image Processing Hardware Development

This paper describes the development of intelligent vision capabilities for small-unmanned aerial vehicles as part of the program CAROLO at the Technische Universitat Braunschweig, Germany. The development’s objective is to create appropriate hardware that suits the requirements of small- unmanned aerial vehicles (5 kg maximum takeoff weight). Enabling vision-based flight guidance during landing was chosen as the first task and acts as a technology demonstrator for future payload-driven vision capabilities. The paper describes the developed image processing hardware and its capabilities.Attention is also paid to implementing image processing algorithms for detecting a known landing point marker and computing its relative position and attitude.

Remarks on Hardware Implementation of Image Processing Algorithms

Remarks on Hardware Implementation of Image Processing AlgorithmsImage processing in industrial vision systems requires both real-time speed and robustness. Modern computers, which fulfill the first demand, are sensitive to hard industrial environment conditions and require considerable amounts of energy. Programmable logic chips are available, which can realize many simple, still time-consuming operations in a parallel or a pipelined manner. The paper discusses particular features of the pipelined architecture and presents selected techniques of implementing early image processing procedures in hardware.

Book Review [review of "Embedded Image Processing on the TMS320C6000 DSP: Examples in Code Composer Studio and MATLAB" by S. Qureshi (2005)

This book focuses on embedded image processing and, more specifically, on the efficient implementation of image processing algorithms on the TMS320C6000 family of digital signal processors (DSPs) from Texas Instruments (TI). The text is divided into six chapters: "Introduction," "Tools," "Spatial Processing Techniques," "Image Filtering," "Edge Detection and Segmentation," and "Wavelets." The text is supported by two appendices, as well as a CD-ROM. The CD-ROM includes all source code and project files as well as many test images and one text video clip. There is no better way to learn than by example, and the book offers plenty of them. While the book is intended for signal and image processing practitioners or software developers that plan to use a TI DSP, most of the programming techniques demonstrated in the book can easily be applied to other embedded platforms. The book is well written and succeeds in filling a big void in image processing literature, tackling how to efficiently implement signal and image processing algorithms using embedded processors.

3D shape measurement of automotive glass by using a fringe reflection technique

In automotive and glass making industries, there is a need for accurately measuring the 3D shapes of reflective surfaces to speed up and ensure product development and manufacturing quality by using non-contact techniques. This paper describes a technique for the measurement of non-full-field reflective surfaces of automotive glass by using a fringe reflection technique. Physical properties of the measurement surfaces do not allow us to apply optical geometries used in existing techniques for surface measurement based upon direct fringe pattern illumination. However, this property of surface reflectivity can be used to implement similar ideas from existing techniques in a new improved method. In other words, the reflective surface can be used as a mirror to reflect illuminated fringe patterns onto a screen behind. It has been found that in the case of implementing the reflective fringe technique, the phase-shift distribution depends not only on the height of the object but also on the slope at each measurement point. This requires the solving of differential equations to find the surface slope and height distributions in the x and y directions and development of the additional height reconstruction algorithms. The main focus has been made on developing a mathematical model of the optical sub-system and discussing ways for its practical implementation including calibration procedures. A number of implemented image processing algorithms for system calibration and data analysis are discussed and two experimental results are given for automotive glass surfaces with different shapes and defects. The proposed technique showed the ability to provide accurate non-destructive measurement of 3D shapes of the reflective automotive glass surfaces and can be used as a key element for a glass shape quality control system on-line or in a laboratory environment.

A reconfigurable architecture for autonomous visual-navigation

This paper describes the design of a reconfigurable architecture for implementing image processing algorithms. This architecture is a pipeline of small identical processing elements that contain a programmable logic device (FPGA) and double port memories. This processing system has been adapted to accelerate the computation of differential algorithms. The log-polar vision selectively reduces the amount of data to be processed and simplifies several vision algorithms, making possible their implementation using few hard-ware resources. The reconfigurable architecture design has been devoted to implementation, and has been employed in an autonomous platform, which has power consumption, size and weight restrictions. Two different vision algorithms have been implemented in the reconfigurable pipeline, for which some experimental results are shown.

SPIRE: a digital library for scientific information

In this paper we describe the architecture and implementation of a digital library framework for scientific data, particularly imagery, with a focus on support for content-based search. Content is specified by the user at one or more of the following abstraction levels: pixel, feature, and semantic. An object-definition mechanism has been developed that supports example-based and constraint-based specification of both simple and complex query targets.This framework incorporates a methodology yielding a computationally efficient implementation of image processing algorithms, thus allowing the interactive, real-time extraction and manipulation of user-specified features and content during the execution of queries. The framework is well-suited for searching scientific databases, including satellite imagery, and medical and seismic data repositories, where the richness of the information does not allow the a priori generation of exhaustive indexes.

QUALITY AND COMPLEXITY BOUNDS OF LOAD BALANCING ALGORITHMS FOR PARALLEL IMAGE PROCESSING

The parallel implementation of image processing algorithms implies an important choice of data distribution strategy. In order to handle the specific constraints associated with images, data distribution must take into account not only the locality of the data and its geometrical regularity but also the possible irregular computation costs associated with different image elements. A widely studied field to tackle this problem is the family of methods related to rectilinear partitioning. We introduce two fully parallel heuristics that compute suboptimal partitions, with a better complexity than the best known algorithms that compute optimal partitions. In this paper, we compare our heuristics to an optimal partitioning, both in terms of execution time and accuracy of the partition. We give some theoretical bounds on the quality of these heuristics that are corroborated by results of random numerical experiments and real applications.

Architecture and applications of the HiPAR video signal processor

We propose the architecture of a highly parallel DSP (HiPAR-DSP) as a flexible and programmable processor for image and video processing. The design is based on an analysis of image processing algorithms in terms of available parallelization resources, demands on program control, and required data access mechanisms. This led to a very long instruction word (VLIW)-controlled ASIMD RISC-architecture with four or sixteen data paths, employing data-level parallelism, parallel instructions, micro-instruction pipelining, and data transfer concurrently to data processing. Common data access patterns for image processing algorithms are supported by use of a shared on-chip memory with parallel matrix type access patterns and a separate data-cache per data path. By properly balancing processing and controlling capabilities as internal and external memory bandwidth, this approach is optimized to make the best use of currently available silicon resources. A high clock frequency is achieved by implementation of classic RISC features. The architecture fully supports high level language programming. With the 16 data path version and a 100 MHz clock, a sustained performance of more than 2 billion arithmetic operations per second (GOPS) is achieved for a wide range of algorithms. The examples show the parallel implementation of image processing algorithms like histogramming, Hough transform, or search in a sorted list with efficient use of the processor resources. A prototype of the architecture with four parallel data paths is available, using a 0.6 /spl mu/m CMOS technology.

Pipelined implementation of the multiresolution Hough transform in a pyramid multiprocessor

The Hough transform is used to detect patterns in images. Its advantage is the ability to detect discontinuous patterns in noisy images. The drawback is its demand for a large amount of computing power. Efficient algorithms and their implementations in multiprocessor systems have been proposed to overcome the computational requirements. The ability to efficiently map two-dimensional (2D) images into 2D meshes makes the pyramid computer a very attractive candidate for implementation of image processing algorithms. Several implementations of the Hough transform in pyramid machines can be found in the literature. The implementations are geared towards the analysis of a single image. Moreover, the implementations do not consider the balancing of the computational load uniformly among the processor elements in the pyramid. The objective of this paper is to propose an efficient pipelined implementation of the multiresolution Hough transform in a pyramid machine. The proposed implementation considers task scheduling to ensure balanced computational load among the processor elements in the pyramid. It is shown that the proposed pipelined implementation is suitable for efficiently analyzing a continuous sequence of images, as found in a typical industrial inspection system. The multiresolution images and accumulator arrays used in the multiresolution Hough transform (MHT) mirrors the variable sized 2D processor arrays in the pyramid layers. The MHT has therefore, been used for implementation in the pyramid machine.

Computer-generated noise images for the evaluation of image processing algorithms

Effective implementation of image processing algorithms for enhancement and restoration often assumes that the images are degraded by known statistical noise. Depending on the application, the type of noise present may vary. The noise distributions that are commonly encountered in image processing are the Gaussian, Rayleigh, negative exponential, and gamma. Typically, when computer-generated noise images are used for algorithm development they are spatially uncorrelated. It is the purpose of this paper to present various types of computer-generated two-dimensional correlated and uncorrelated noise images along with suggestions of several applications.

An interdisciplinary course in digital image processing

This paper documents the development and first offering of an interdisciplinary undergraduate course in Digital Image Processing at the University of Wyoming. The course itself was designed to serve majors from a wide range of academic disciplines, although in its initial offering, it was attented mainly by students majoring in Computre Science and Electrical Engineering. National Foundation funding for equipment for the course was used to purchase a high speed image processing system and six state-of-the-art graphics workstations with software that supported basic and intermediate level image processing operations. Students in the course were required to perform a standard set of image processing sequences such as histogramming and histogram equalization, edge detection and evaluation, image smoothing, region growing, Fourier filtering, and image warping. Each student, in consultation with the instructor, then pursued a specific topic in image processing which involved either combining several image processing operations to produce a desired result or developing special code to implement image processing algorithms that were discussed in the text but not included in the provided software. The nature of the course and its impact on education at the University of Wyoming is discussed in the paper that follows.

Two-dimensional modulation transfer functions for rotational panoramic radiography

The two-dimensional modulation transfer function (MTF) provides a method for describing resolution in panoramic x-ray systems where the process of image formation differs in the horizontal and vertical dimensions. As an example, two-dimensional MTFs for the Philips OrthOralix SD machine were calculated from point spread functions (PSF) describing the various sources of unsharpness within the system. The PSF for the focal spot was measured using a pinhole camera. The PSF for the screen-film combination was calculated from data supplied by the manufacturer. The PSF for the motion blurring that is inherent in rotational panoramic radiography was derived from standard mathematical models. The three functions were convolved together to obtain the PSF of the entire system and the two-dimensional MTF was derived from the system PSF by Fourier transformation. The two-dimensional MTF provides a tool which should be useful in the future for the evaluation of existing systems, for the design of improved equipment, and for the implementation of image processing algorithms.

Hough transform using Cordic method

The purpose of the letter is to demonstrate the usefulness of the Cordic algorithm for implementation of image processing algorithms in dedicated hardware to achieve near real-time processing speed. The Cordic algorithm will be discussed, and also its application for line and circle detection as well as for arbitrary shapes using Hough transforms.

An image filing system for the implementation of image processing algorithms in a research environment

An image filing system (IFS) has been written to facilitate the implementation and testing of image processing algorithms in a research environment. A programming substrate has been developed to provide applications with routines for acquiring, displaying, and manipulating images without regard for the underlying information format. Images of diverse modalities are cataloged and tracked through a series of image operations with descriptive pointers to all antecedents. This paper presents the design and implementation of the image filing system and describes one of the major image processing applications developed in the IFS environment.

An Overview of Digital Image Processing and Recognition (Invited Paper)

Interest in digital image processing techniques dates back to the early 1920's, when digitized pictures of world news events were first transmitted by submarine cable between New York and London. Applications of digital image processing concepts, however, did not become widespread until the middle 1960's, when third-generation digital computers began to offer the speed and storage capabilities required for practical implementation of image processing algorithms. Since then, this area has experienced vigorous growth, having been a subject of interdisciplinary research in fields ranging from engineering and computer science to biology, chemistry, and medicine.

On efficient global information extraction methods for parallel processors

The capability of a parallel processor for the fast implementation of image processing algorithms is demonstrated by the analysis of selected examples. An earlier study considered thresholding by the mode method as a challenge for the parallel processor. In this paper we identify the necessity for an efficient global feature extraction mechanism and show that a small increase in hardware (less than 5%) can result in more than two orders of magnitude speed improvement for this and some other algorithms. A hardware feature extraction (bit counting) mechanism is proposed and its performance is analyzed for several image processing algorithms. The main contention of this paper is that current parallel processors should incorporate this form of hardware if they are to be effectively utilized for many image processing applications.