Implementation Overhead Research Articles

Design and Implementation of a Low-Complexity Multi-h CPM Receiver with Linear Phase Approximation Synchronization Algorithm.

Multi-h continuous phase modulation (CPM), with extremely high spectral efficiency, involves the plague of high demodulation complexity with a large number of matched filters and a complex trellis. In this paper, an efficient all-digital demodulator for multi-h continuous phase modulation (CPM) is proposed based on a low-complexity decision-directed synchronization algorithm. Based on the maximum-likelihood estimation of the carrier phase and timing errors, we propose a reduced-complexity timing error detector with linear phase approximation (LPA) to the phase of the multi-h CPM. Compared with the traditional synchronization methods, it avoids derivative matched filtering and reduces about 2/3 of matched filters. The estimated accuracy and bit error rate (BER) performance of the LPA-based synchronization algorithm have no loss, as shown by the numerical simulation. Its stability is verified by the derived S-curve. Then, the receivers with the LPA-based synchronization for the three kinds of promising multi-h CPM are implemented on a Xilinx Kintex-7 FPGA platform. The experimental results show that the onboard tested BER of the proposed design has an ignorable loss in the numerical simulation. The implementation overhead on FPGA is significantly reduced by about 27% slices, 64% DSPs, and 70% block RAMs compared with the conventional method.

An Efficient Mapping Scheme on Neural Networks for Linear Massive MIMO Detection

For massive multiple-input multiple-output (MIMO) communication systems, simple linear detectors such as zero forcing (ZF) and minimum mean square error (MMSE) can achieve near-optimal detection performance with reduced computational complexity. However, such linear detectors always involve complicated matrix inversion, which will suffer from high computational overhead in the practical implementation. Due to the massive parallel-processing and efficient hardware-implementation nature, the neural network has become a promising approach to signal processing for the future wireless communications. In this paper, we first propose an efficient neural network to calculate the pseudo-inverses for any type of matrices based on the improved Newton's method, termed as the PINN. Through detailed analysis and derivation, the linear massive MIMO detectors are mapped on PINNs, which can take full advantage of the research achievements of neural networks in both algorithms and hardwares. Furthermore, an improved limited-memory Broyden-Fletcher-Goldfarb-Shanno (L-BFGS) quasi-Newton method is studied as the learning algorithm of PINNs to achieve a better performance/complexity trade-off. Simulation results finally validate the efficiency of the proposed scheme.

A high-performance fully adaptive routing based on software defined network-on-chip

Adaptive routing techniques have been proven to be effective solutions for handling network congestion and enhancing the performance of Network-on-Chip (NoC). Traditional adaptive routing algorithms may degrade flexibility and lead to the issue of high hardware implementation overhead. In this paper, we propose a fully adaptive routing (FAR) based on Software Defined NoC (SDNoC) to address these issues. The proposed FAR decouples path selection from packet forwarding. The routing path is determined by software techniques in the control layer according to the global congestion status and is encapsulated into the packet to control the forwarding of the packet. Evaluation results show that the proposed FAR yields an improvement of performance over the typical routing schemes in average packet latency and saturation throughput up to 8.2% and 6.1% respectively. The layout area and power consumption are at least 6.2% and 3.9% less compared with the typical routing schemes as well.

Anomaly detection speed-up by quantum restricted Boltzmann machines

Quantum machine learning promises to revolutionize traditional machine learning by efficiently addressing hard tasks for classical computation. While claims of quantum speed-up have been announced for gate-based quantum computers and photon-based boson samplers, demonstration of an advantage by adiabatic quantum annealers (AQAs) is open. Here we quantify the computational cost and the performance of restricted Boltzmann machines (RBMs), a widely investigated machine learning model, by classical and quantum annealing. Despite the lower computational complexity of the quantum RBM being lost due to physical implementation overheads, a quantum speed-up may arise as a reduction by orders of magnitude of the computational time. By employing real-world cybersecurity datasets, we observe that the negative phase on sufficiently challenging tasks is computed up to 64 times faster by AQAs during the exploitation phase. Therefore, although a quantum speed-up highly depends on the problem’s characteristics, it emerges in existing hardware on real-world data.

Securing Embedded System from Code Reuse Attacks: A Lightweight Scheme with Hardware Assistance.

The growing prevalence of embedded systems in various applications has raised concerns about their vulnerability to malicious code reuse attacks. Current software-based and hardware-assisted security techniques struggle to detect or block these attacks with minor performance and implementation overhead. To address this issue, this paper presents a lightweight hardware-assisted scheme to enhance the security of embedded systems against code reuse attacks. We develop an on-chip lightweight hardware shadow stack to validate target addresses at runtime for backward-edge control flow integrity, which backs up valid return addresses during function calls and automatically verifies actual return addresses during the return phase. Additionally, we propose a lightweight stream cipher circuit that encrypts and decrypts critical stack data related to control flow manipulation, preventing attackers from analyzing or tampering with them. When designing and implementing the security mechanism for embedded systems, we fully consider the constraints of limited system resources and performance, optimizing both the architecture design and implementation of the proposed hardware. Finally, we integrate both the proposed lightweight hardware shadow stack and the runtime data encryption hardware into the OR1200 processor. We have verified the system security function on the Terasic DE1-SoC FPGA platform and evaluated the system performance as well as implementation overhead. The results show that the proposed lightweight hardware-assisted scheme can provide a dedicated defense capability against code reuse attacks for embedded systems, with an average system performance overhead of 0.39% and an area footprint of 0.316 mm2.

R&D of an Innovative OFDM Communication Payload for Small-Size AUV

With its superiorities of low cost, high flexibility and deployment convenience, small-size autonomous underwater vehicles (AUVs) have been extensively applied to perform a variety of undersea missions. While underwater acoustic (UWA) communication provides a practical way to establish a wireless link, it still poses a significant challenge due to the strict limitations of a small-size AUV platform in terms of load capacity, energy supply and cost. Orthogonal frequency division multiplexing (OFDM) has drawn extensive attention due to its high data rate capability and relative robustness to multipath, the performance of which is unfortunately sensitive to the widespread Doppler effect. While efficient Doppler compensation is significantly crucial for UWA OFDM mobile communication, most of the conventional approaches are conducted using software resampling, thus rendering a huge burden on memory and calculation capability as well as a considerable processing delay. In this paper, from the perspective of hardware completion an UWA OFDM communication payload based on STM32F407 processor is designed and implemented to facilitate agile Doppler compensation with low computational overhead. In particular, after estimating Doppler by calculating the time compression or extension of the preamble signal, Doppler compensation is performed by directly adjusting the direct digital frequency synthesizer (DDS)-driven sampling rate of the analog-to-digital converter (ADC). As the Doppler is compensated parallel to the ADC acquisition, processing delay and memory requirement can be avoided. Finally, hardware-in-loop (HIP) simulation is performed to demonstrate the effectiveness and superiority of the proposed system. The results show that the designed system has the potential to achieve an effective communication rate of 3.19 kbps with the admissible implementation overhead. Future work will entail the integration and performance evaluation of the proposed UWA OFDM communication payload on a practical small-size AUV platform.

A Speculative Computation Approach for Energy-Efficient Deep Neural Network

Deep neural networks (DNNs) have been widely used for data processing and analysis nowadays. Many computational techniques have been proposed to improve the energy efficiency of executing DNNs, which is critical for emerging smart edge applications. This article presents a speculative computation approach to improving the energy efficiency of DNN computations. The proposed approach employs the techniques of input channel partitioning and threshold-based negative masking to predict and eliminate unnecessary computations. Moreover, a systematic procedure of threshold optimization is proposed to achieve the best tradeoff between the energy and accuracy performance. Finally, an energy-efficient DNN processor architecture was designed and implemented to support the proposed speculative computation approach. The experimental results show that the proposed DNN processor with speculative computation can enhance the energy efficiency of the processor by 22.8%, with only 0.96% accuracy degradation and 1% implementation overhead.

Scalable Load Balancing in Networked Systems: A Survey of Recent Advances

In this survey we provide an overview of recent advances on scalable load balancing schemes which provide favorable delay performance and yet require minimal implementation overhead. The basic load balancing scenario involves a single dispatcher where tasks arrive that must immediately be forwarded to one of $N$ single-server queues. The join-the-shortest-queue (JSQ) policy yields vanishing delays as $N$ grows large, as in a centralized queuing arrangement, but involves a prohibitive communication burden. In contrast, JSQ($d$) schemes that assign an incoming task to a server with the shortest queue among $d$ servers selected uniformly at random require little communication, but lead to constant delays. In order to examine this fundamental trade-off between delay performance and implementation overhead, we discuss a body of recent research on JSQ($d(N)$) schemes in which the diversity parameter $d(N)$ depends on $N$ and investigate the growth rate of $d(N)$ required to match the optimal JSQ performance on fluid and diffusion scales. Stochastic coupling techniques and scaling limits play an instrumental role in establishing this asymptotic optimality. We demonstrate how this methodology carries over to infinite-server settings, finite buffers, multiple dispatchers, servers arranged on graph topologies, and token-based load balancing schemes such as join-the-idle-queue (JIQ), thus providing a broad overview of the main trends in the field.

R&D of a low-complexity OFDM acoustic communication payload for Micro-AUV in confined space

With small size, high flexibility, low cost, and deployment convenience, Micro-sized autonomous underwater vehicle (Micro-AUV) is capable of performing diverse underwater missions efficiently in confined underwater space, for the extensive purpose of rescue, sightseeing, pipeline engineering and so on. The underwater acoustic (UWA) communication technique provides an effective way to support this types of underwater mission for telemetry and remote control of Micro-AUV. However, while the adverse multipath caused by confined space poses significant challenge to the classic coherent acoustic communication schemes that need channel estimation and equalization processing, the employment of non-coherent communication scheme is generally limited by low data rate. By utilizing time-domain and frequency-domain differential modulation to suppress the influence of multipath, a low-complexity UWA communication payload is designed to provide an effective solution to make a tradeoff between data rate and implementation complexity. Based on a STM32 series processor, this paper introduced the software and hardware implementation of a time-frequency differential OFDM UWA communication payload for Micro-AUV and presented the performance evaluation of the system in confined underwater space. The experimental results achieved in a confined lake show that the proposed system has the potential of being used for Micro-AUV to achieve a data rate of 1.96 kbps at a distance of 200m with acceptable implementation overhead.

Performance Analysis of Hybrid Cryptography System for High Security and Cloud-Based Storage

Now a day, the security of the data is playing a major part in communication systems due to further bushwhackers between channels media. The security position depends on cache crucial and as per literature, advanced the bit size of the key, advanced the security and also larger data size comes major challenge task for the further process. Thus, the generation of crucial with the further size is a major grueling task and at present, the Advanced Encryption Standard (AES) is a better cryptography system where the encryption and decryption can perform with a fixed key. The literature says the holomorphic function is well-suitable for data size reduction. To address this issue, new Holomorphic grounded encryption and decryption and AES are combined to increase the security position. The alternate novelty is that variable crucial generation using Elliptic Wind Cryptography (ECC) due to its enlarged proportion of consideration in assiduity and experimenters. The ECC uses point addition and point doubling to induce 256 values and addition operations can be avoided. After the generation of the matrix, each matrix value is translated and decrypted using a Holomorphic algorithm. The proposed work has been designed using MATLAB 2017a, dissembled, and validated with different datasets in real decors. Cloud computing is expected to be considered one of the primary computing platforms in the field of storage and security as it possesses many advantages such as profitability, efficiency as well as lower implementation overheads. Contemporary cloud computing security algorithms are enhanced extensions of cryptography. Data privacy, as well as data protection, are the major areas of concern in Cloud computing. The cryptographic with holomorphic based data encryption and interchange of information is exchanged and then accumulated in the cloud through holomorphic encryption which uses point addition and doubling operation to ensure data confidentiality of owners as well as users. Proposed work novel hybrid algorithm based on the context of encryption and decryption and thus integrates cryptography hybrid techniques include modified 126-bit AES and ElGamal based ECC through splitting algorithm. The advantage of splitting the larger data in size into binary form and then processing for encryption and decryption leads to optimization of latency, increase throughput, and security. The proposed hybrid approach has better security towards information sharing as well as cloud storage intrusions. Based on obtained results in MATLAB 2017a software tool, the obtained results show that 43% improvement in throughput and 12% reduction in latency, and a 21% improvement in security level.

Automatic Stream Identification to Improve Flash Endurance in Data Centers

The demand for high performance I/O in Storage-as-a-Service (SaaS) is increasing day by day. To address this demand, NAND Flash-based Solid-state Drives (SSDs) are commonly used in data centers as cache- or top-tiers in the storage rack ascribe to their superior performance compared to traditional hard disk drives (HDDs). Meanwhile, with the capital expenditure of SSDs declining and the storage capacity of SSDs increasing, all-flash data centers are evolving to serve cloud services better than SSD-HDD hybrid data centers. During this transition, the biggest challenge is how to reduce the Write Amplification Factor (WAF) as well as to improve the endurance of SSD since this device has a limited program/erase cycles. A specified case is that storing data with different lifetimes (i.e., I/O streams with similar temporal fetching patterns such as reaccess frequency) in one single SSD can cause high WAF, reduce the endurance, and downgrade the performance of SSDs. Motivated by this, multi-stream SSDs have been developed to enable data with a different lifetime to be stored in different SSD regions. The logic behind this is to reduce the internal movement of data—when garbage collection is triggered, there are high chances of having data blocks with either all the pages being invalid or valid. However, the limitation of this technology is that the system needs to manually assign the same streamID to data with a similar lifetime. Unfortunately, when data arrives, it is not known how important this data is and how long this data will stay unmodified. Moreover, according to our observation, with different definitions of a lifetime (i.e., different calculation formulas based on selected features previously exhibited by data, such as sequentiality, and frequency), streamID identification may have varying impacts on the final WAF of multi-stream SSDs. Thus, in this article, we first develop a portable and adaptable framework to study the impacts of different workload features and their combinations on write amplification. We then propose a feature-based stream identification approach, which automatically co-relates the measurable workload attributes (such as I/O size, I/O rate, and so on.) with high-level workload features (such as frequency, sequentiality, and so on.) and determines a right combination of workload features for assigning streamIDs . Finally, we develop an adaptable stream assignment technique to assign streamID for changing workloads dynamically. Our evaluation results show that our automation approach of stream detection and separation can effectively reduce the WAF by using appropriate features for stream assignment with minimal implementation overhead.

Exploiting LSB Self-quantization for Plaintext-related Image Encryption in the Zero-trust Cloud

The zero-trust (ZT) principle is a promising way to ensure data security in cloud storage. This principle stated that data confidentiality is guaranteed by encryption. However, in ZT image cloud storage scenarios, traditional symmetric cryptosystems and image encryption schemes based on the permutation-diffusion structure cannot balance between efficiency and security against some cryptanalysis. Existing plaintext-related image encryption schemes improve such problems but cause additional keys overhead for different plaintexts, additional ciphertexts overhead, or decryption failure under clipping and noise attacks. Thus, these encryption schemes cannot meet the requirements of ZT in both reducing implementation overhead and resisting multiple attacks. By using least significant bit (LSB) embedding in pixels, we propose a self-adaptive process driven by LSB self-quantization, which forms a novel plaintext-related encryption scheme in a provided ZT model. In our analysis, two pixel-level properties can be obtained through LSB repetitive embedding, LSB extraction, bitwise-XOR, and cyclic-shift operations. With these properties, the plaintext-related key stream is generated to encrypt pixel positions and pixel values, and its disturbance value can be spontaneously extracted from the LSB for decryption. As a result, the proposed scheme needs only one-round execution, resists multiple cryptanalysis without additional keys and ciphertexts, and ensures decryption under clipping or noise attacks. Further simulation results demonstrate that the scheme is efficient and has good resistance to these attacks, which indicates its good application potential for ZT image cloud storage scenarios.

A new S-box construction method meeting strict avalanche criterion

S-box is the main security component in lightweight block ciphers. Finding new algorithms and technical applications to generate S-box is still a current research topic. We proposed an S-box construction method that satisfies the strict avalanche criterion. It includes a nonlinear layer and a diffusion layer. These layers enable the constructed S-box to maintain good nonlinearity, differential uniformity, strict avalanche criterion, and a high number of algebraic terms. Secondly, we listed 20 existing classic 4 × 4 S-boxes and tested their cryptographic properties such as nonlinearity, difference uniformity, strict avalanche criterion, algebraic degree, algebraic item number, and fixed point. At the same time, the test results are compared with the proposed S-box. The results show that these cryptographic properties of our proposed S-box are superior to other S-boxes. In addition, we evaluated the proposed S-box hardware implementation overhead. To evaluate our S-box more objectively, we tested the above 20 S-boxes hardware implementation overhead under the same conditions, and the results show that the S-box we constructed achieved a good balance between cryptographic properties and hardware overhead.

Review, Analysis, and Implementation of Path Selection Strategies for 2D NoCs

Recent advances in very-large-scale integration (VLSI) technologies have offered the capability of integrating thousands of processing elements onto a single silicon microchip. Multiprocessor systems-on-chips (MPSoCs) are the latest creation of this technology evolution. Network-on-Chip (NoC) is a scalable and promising interconnection solution used by MPSoCs to achieve high performance. Routing algorithms provide a path to a packet toward the destination. For this, these algorithms should exhibit two characteristics. First, the route selection function should provide enough degree of adaptiveness to avoid network congestion. Second, it should not offer stale information on network congestion status to the neighboring routers. Many researchers have investigated network congestion and proposed techniques to control/avoid congestion. Such congestion avoidance-based algorithms significantly improve NoC performance. However, they may result in hardware overhead for side network implementation to collect congestion status. This paper reviews the selection strategies used to reduce congestion in NoC and classifies them on the technique adopted to handle and propagate congestion information. Additionally, this paper provides the implementation and analysis details of some state-of-art selection methods.

A Fractional-N Digital MDLL With Background Two-Point DTC Calibration

This article presents a fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> digital multiplying delay-locked loop (MDLL) that employs a digital-to-time converter (DTC) to control the reference injection for the fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> operation. The presented MDLL features a background two-point DTC calibration that simultaneously corrects the DTC gain and offset errors to achieve a low-jitter and low-spur architecture. The DTC errors are sensed using an embedded time-to-digital converter (TDC) and extracted in the digital domain for reduced implementation overhead. A new TDC dithering and dither noise cancellation technique is used to improve the estimation accuracy of the DTC errors at the presence of TDC quantization error and differential nonlinearity (DNL). In addition, the adaptive dither noise cancellation scheme uses a comb filter to decouple the dither noise and DTC error estimations, allowing the two schemes to operate simultaneously. The proof-of-concept MDLL prototype fabricated in 65-nm CMOS achieves −60-dBc fractional spur and 1.67-ps rms jitter at around 20-MHz offset. With the proposed calibration scheme, a >25-dB spur reduction in reference and fractional spurs is demonstrated.

Challenges and Opportunities for Practical and Effective Dynamic Information Flow Tracking

Information flow tracking was proposed more than 40 years ago to address the limitations of access control mechanisms to guarantee the confidentiality and integrity of information flowing within a system, but has not yet been widely applied in practice for security solutions. Here, we survey and systematize literature on dynamic information flow tracking (DIFT) to discover challenges and opportunities to make it practical and effective for security solutions. We focus on common knowledge in the literature and lingering research gaps from two dimensions— (i) the layer of abstraction where DIFT is implemented (software, software/hardware, or hardware) and (ii) the security goal (confidentiality and/or integrity). We observe that two major limitations hinder the practical application of DIFT for on-the-fly security applications: (i) high implementation overhead and (ii) incomplete information flow tracking (low accuracy). We posit, after review of the literature, that addressing these major impedances via hardware parallelism can potentially unleash DIFT’s great potential for systems security, as it can allow security policies to be implemented in a built-in and standardized fashion. Furthermore, we provide recommendations for the next generation of practical and efficient DIFT systems with an eye towards hardware-supported implementations.

Side-channel information leakage analysis and countermeasures in an embedded CPU microarchitecture

Side-channel attacks (SCAs) have become a significant threat nowadays to cryptographic devices, especially central processing units (CPUs). Based on the implementation of AES-128, the side-channel information leakage analysis is carried out in a 32-bit CPU microarchitecture in this work. Correlation power analysis (CPA) results show that it is obvious to reveal the secret key by using only 30 power traces based on the net-list simulation. Three flexibly configurable hardware-based countermeasures are proposed to prevent information leakage in the arithmetic and logic unit (ALU), register file (RF) and load/store unit (LSU), respectively, which are the most sensitive components according to our analysis. The proposed countermeasures have different protection effects on the CPU since the required trace number to reveal the secret key has increased from 30 to 100∼120,000. Moreover, the anti-attack capability of the CPU is improved by 4000 times using the three countermeasures simultaneously. The proposed countermeasures can be freely combined while considering the CPU security and implementation overhead. In practice, the anti-attack capability of the CPU can be further improved when the proposed countermeasures are implemented in real-world measurements, because additional noise will be introduced during the measurements.

A Mixture of Experts Approach for Low-Cost DNN Customization

Editor's notes: This article introduces a novel architecture for local learning, namely mixture of experts (MoEs), to customize a deep neural network (DNN) that is deployed on an edge device with performance improvement and low implementation overhead. -Deming Chen, University of Illinois at Urbana-Champaign

CIB-HIER

Hierarchical organization is widely used in high-radix routers to enable efficient scaling to higher switch port count. A general-purpose hierarchical router must be symmetrically designed with the same input buffer depth, resulting in a large amount of unused input buffers due to the different link lengths. Sharing input buffers between different input ports can improve buffer utilization, but the implementation overhead also increases with the number of shared ports. Previous work allowed input buffers to be shared among all router ports, which maximizes the buffer utilization but also introduces higher implementation complexity. Moreover, such design can impair performance when faced with long packets, due to the head-of-line blocking in intermediate buffers. In this work, we explain that sharing unused buffers between a subset of router ports is a more efficient design. Based on this observation, we propose Centralized Input Buffer Design in Hierarchical High-radix Routers (CIB-HIER), a novel centralized input buffer design for hierarchical high-radix routers. CIB-HIER integrates multiple input ports onto a single tile and organizes all unused input buffers in the tile as a centralized input buffer. CIB-HIER only allows the centralized input buffer to be shared between ports on the same tile, without introducing additional intermediate virtual channels or global scheduling circuits. Going beyond the basic design of CIB-HIER, the centralized input buffer can be used to relieve the head-of-line blocking caused by shallow intermediate buffers, by stashing long packets in the centralized input buffer. Experimental results show that CIB-HIER is highly effective and can significantly increase the throughput of high-radix routers.

Optimal hyper-scalable load balancing with a strict queue limit

Load balancing plays a critical role in efficiently dispatching jobs in parallel-server systems such as cloud networks and data centers. A fundamental challenge in the design of load balancing algorithms is to achieve an optimal trade-off between delay performance and implementation overhead (e.g. communication or memory usage). This trade-off has primarily been studied so far from the angle of the amount of overhead required to achieve asymptotically optimal performance, particularly vanishing delay in large-scale systems. In contrast, in the present paper, we focus on an arbitrarily sparse communication budget, possibly well below the minimum requirement for vanishing delay, referred to as the hyper-scalable operating region. Furthermore, jobs may only be admitted when a specific limit on the queue position of the job can be guaranteed.The centerpiece of our analysis is a universal upper bound for the achievable throughput of any dispatcher-driven algorithm for a given communication budget and queue limit. We also propose a specific hyper-scalable scheme which can operate at any given message rate and enforce any given queue limit, while allowing the server states to be captured via a closed product-form network, in which servers act as customers traversing various nodes. The product-form distribution is leveraged to prove that the bound is tight and that the proposed hyper-scalable scheme is throughput-optimal in a many-server regime given the communication and queue limit constraints. Extensive simulation experiments are conducted to illustrate the results.