VLSI Implementation Research Articles

VLSI Implementation of Discrete Cosine Transform Approximation Recursive Algorithm

In general, the approximation of Discrete Cosine Transform (DCT) is used to decrease computational complexity without impacting its efficiency in coding. Many of the latest algorithms used in DCT approximation functions have only a smaller DCT length transform of which some are non-orthogonal. For computing DCT orthogonal approximation, a general recursive algorithm is used here, and its length is obtained using DCT pairs of length N/2 of N addition cost in input pre-processing. The recursive sparse matrix has been decomposed by using the vector symmetry from the DCT basis in order to achieve the proposed approximation algorithm that is highly scalable to enforce the highest lengths software and hardware by using a current 8-point approximation to obtain a DCT approximation with two-length power, N>8.

Design and vlsi implementation of a decimation filter for hearing aid applications

Roughly 10% of the total common people experience some kind of hearing misfortune, yet just little level of this measurement utilize the portable amplifier. The shame related with wearing a portable amplifier, client disappointment with listening device execution, the expense and the battery life. Using computerized signal handling the advanced portable amplifier currently offers what the simple listening device can't offer. As of now low power VLSI design is more preferable in digital designs. More and more individuals around the globe experience the ill effects of hearing misfortunes. The expanding normal age and the developing populace are the principle explanations behind this. The pulverization channel utilized for portable amplifier is planned and executed both in MATLAB and Very High Speed Integrated Circuit Hardware Description Language. The obliteration channel is structured utilizing the circulated number-crunching multiplier in Very High Speed Integrated Circuit Hardware Description Language. Each computerized channel structure is reproduced utilizing Matlab and its total engineering is caught utilizing Simulink. The subsequent engineering is equipment productive and expends less force contrasted with traditional decoding channels. Contrasted with the decoding FIR-FIR engineering, the structured decoding channel design utilizing Comb-half band FIR-FIR adds to an equipment sparing and decreases the force scattering.

Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support

In this paper, we have addressed a speed-area efficient VLSI implementation of a cellular automaton (CA) based random number generator (RNG) on Field Programmable Gate Arrays (FPGAs), in which each CA cell was proposed to be a multi-bit word in the original algorithm. This is in contrast to typical CA algorithms comprising one bit per CA cell. The original algorithm is shown favorable for FPGA implementations on adopting a fabric conscious approach involving instantiation of physical FPGA primitives. We have supplemented the original architecture with scan path and alternating logic to facilitate fault localization without area and delay overhead. The overheads have been carefully nullified by increasing the utilization ratio of the configured primitives, and exploiting the fast hardwired fabric of the FPGA. Generation of the hardware description of the RNG through Verilog has been automated. Our proposed designs outperform equivalent behavioral implementations expressed at higher levels of abstraction, both in speed and area.

Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism Scheme

Binary neural networks (BNNs) have attracted significant interest for the implementation of deep neural networks (DNNs) on resource-constrained edge devices, and various BNN accelerator architectures have been proposed to achieve higher efficiency. BNN accelerators can be divided into two categories: streaming and layer accelerators. Although streaming accelerators designed for a specific BNN network topology provide high throughput, they are infeasible for various sensor applications in edge AI because of their complexity and inflexibility. In contrast, layer accelerators with reasonable resources can support various network topologies, but they operate with the same parallelism for all the layers of the BNN, which degrades throughput performance at certain layers. To overcome this problem, we propose a BNN accelerator with adaptive parallelism that offers high throughput performance in all layers. The proposed accelerator analyzes target layer parameters and operates with optimal parallelism using reasonable resources. In addition, this architecture is able to fully compute all types of BNN layers thanks to its reconfigurability, and it can achieve a higher area–speed efficiency than existing accelerators. In performance evaluation using state-of-the-art BNN topologies, the designed BNN accelerator achieved an area–speed efficiency 9.69 times higher than previous FPGA implementations and 24% higher than existing VLSI implementations for BNNs.

Compact Bit-Parallel Systolic Multiplier Over GF(2m)

This article presents a compact and efficient bit-parallel systolic array structure for multiplication over the extended binary field, GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ). The systolic array has a regular arrangement with local connections, making it more suitable for VLSI implementations. Also, it has the merits of having hardware complexity of order <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</i> (m) that distinguishes it from the previously reported bit-parallel designs having hardware complexity of order <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</i> (m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ). The achieved results exhibited that the suggested parallel architecture realizes a significant reduction in hardware complexity and the area-delay complexity over the competitor architectures previously published in the literature. Therefore, it is more suitable for usage in constrained hardware environments, having more restrictions on space, such as portable devices and smart cards.

WITHDRAWN: An extensive survey on signed, unsigned truncated multiplier

Abstract This work confers a widespread survey on the recent developments in Signed, Unsigned Truncated Multiplier, considering various aspects such as modeling, simulation tools and applications especially in signal processing and image processing, highlighting the future directions. Applications such as audio and signal processing, SDR and so on, based on the signal processing and image processing in the recent years of development of technology can function with high efficacy in performance and greatly compactable in terms of area. There could be more signal noises and fluctuations in the digital signal processing applications which use all types of gadgets. Besides, these applications occupy larger areas in VLSI implementation due to the arithmetic operation of Adders and Multiplier design. This survey paper gives a complete roadmap to design an efficient truncated multiplier which can be useful for both signed and unsigned operations. Finally provides a complete roadmap for truncated multiplier for signal processing applications.

Sub-Nyquist Wideband Spectrum Sensing Based on Analog to Information Converter for Cognitive Radio

With the development of wireless communication technology, higher spectrum efficiency is required for the 5G cellular networks. Cognitive radio (CR) has emerged as one of the most promising candidate solution to improve spectrum utilization and efficency. Wideband spectrum sensing has been the focal challenge point in cognitive radio technology, since existing techniques are reliant on analog to digital converters (ADC) with sampling at the Nyquist rate. However, in order to perform digitization of wideband RF signals at the Nyquist rate, a very high sampling frequency is required with primarily complex and energy inefficient designs. In this paper, a sub-Nyquist wideband spectrum sensing design is proposed. In the proposed design, an analog-to-information converter is presented. It utilizes Compressive Sensing which enables sampling far below the Nyquist rate, thus drastically reducing the power consumption, complexity and cost of the entire Receiver. The main biulding blocks in the proposed design which are: higher speed SAR analog to digital for random demodulator analog to information converter (AIC) were designed and simulated using cadance software for performance evaluation. The design was implemented in targeted technology of 130 nm standard CMOS technology. An optimization method suitable for VLSI implementation, termed Orthogonal Matching Pursuit (OMP), was utilized for spectrum recovery. Following comparative analyses with previously published studies, we demonstrate significant improvements in terms of speed and chip area of the SAR ADC design.

A low area VLSI implementation of extended tiny encryption algorithm using Lorenz chaotic system

A low area VLSI implementation of extended tiny encryption algorithm using Lorenz chaotic system

VLSI Implementation of Green Computing Control Unit on Zynq FPGA for Green Communication

The issue of the energy shortage is affecting the entire planet. This is occurring because of massive population and industry growth around the world. As a result, the entire world is attempting to implement green networking systems and manufacture the power/energy efficient products. This research work discusses the green networking system technologies. This work introduces a power‐efficient control unit (CU) design and implemented on the Zynq SoC (System on Chip) ultrascale field programmable gate array (FPGA). The VIVADO HLx Design Suite is used to simulate and analyze the CU model which is considered as one of the key components of central processing unit (CPU), used for data communication purposes. The CU is made suitable for the green communication by making it power‐efficient. Therefore, the power consumption of the CU is analyzed for the various set frequency value ranging between 100 MHz and 5 GHz, and it is discovered that as the clock frequency rises up, the total power consumption also tends to get increased. The total power of the proposed model is reduced by 77.42%, 21.29%, and 17.93% from three models, respectively, being compared in the present paper. Final results shows that the CU is better suited to run at low frequencies to optimize power consumption.

VLSI Implementation of LFA based Median Filter with Noise Detection Architecture for EMG Denoising

Noise Reduction with less computational time and resources of the signal is a major requirement in signal processing. In the real-world scenario, Electromyography (EMG) signals often affect by various noises. The EMG signal requires noise reduction to obtain an accurate diagnosis process. In this study, Ladner-Fischer Adder (LFA) based Median Filter (MF) architecture is used to remove the noise from the EMG signal. The noise evaluation process is included in this proposed method to eliminate the flicker noise from the signal. The proposed LFA-MF method is simulated in the Cadence RTL compiler and Xilinx tool to evaluate the performance in terms of power, delay and Look Up Table (LUT). The objective of this work is to design the noise detection structure to avoid the denoising process for all the samples. This helps to reduce the hardware resources of the entire median filter architecture. The simulation result of LFA-MF architecture showed that it has lower power consumption and delay in noise reduction. The LFA-MF architecture has a power consumption of 1006548 nW in 16-bit sample width, while the existing method has 1537940 nW power consumption.

VLSI Implementation of Algorithm for Performance Improvement of Minutiae Based Fingerprint Recognition System

VLSI Implementation of Algorithm for Performance Improvement of Minutiae Based Fingerprint Recognition System

VLSI Implementation of Multiply and Accumulate Unit Using Distributed Arithmetic

VLSI Implementation of Multiply and Accumulate Unit Using Distributed Arithmetic

Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography

As one of the postquantum protocol candidates, the supersingular isogeny key encapsulation (SIKE) protocol delivers promising public and secret key sizes over other candidates. Nevertheless, the considerable computations form the bottleneck and limit its practical applications. The modular multiplication operations occupy a large proportion of the overall computations required by the SIKE protocol. The VLSI implementation of the high-speed modular multiplier remains a big challenge. In this article, we propose three improved modular multiplication algorithms based on an unconventional radix for this protocol, all of which cost about 20% fewer computations than the prior art. Besides, a multiprecision scheme is also introduced for the proposed algorithms to improve the scalability in hardware implementation, resulting in three new algorithms. We then present very efficient high-speed constant-time modular multiplier architectures for the six algorithms. It is shown that these new architectures can be extensively pipelined and highly optimized to obtain high throughput and low latency. The field-programmable gate array (FPGA) implementation results show that all proposed multipliers achieve much higher throughput than previous designs, but the increase in resources is relatively small. In addition, the multipliers without the multiprecision scheme have very low latency, which is very friendly to high-speed applications of the SIKE protocol.

VLSI Implementation and Software Co-Simulation of Digital Image Watermarking with Increased Security

Background: Security is one of the fundamental and essential factors, which has to be addressed in the field of communication. Communication refers to the exchange of useful information between two or more nodes. Sometimes it is required to exchange some of the confidential information such as a company’s logo, which needs to be hidden from the third person. The data that is being exchanged between these nodes has to be kept confidential and secured from unintended users. The three fundamental components of security are confidentiality, integrity and authentication. The data that is being exchanged has to be confidential, and only the authorized party should have access to the information that is being exchanged. One of the key methods for securing the data is encryption. Objective: The main objective of this paper was to address the problem of data hiding and security in communication systems. There is a need for having hardware resources for having high speed data security and protection. Methods: In this paper, we implemented image watermarking using LSB technique to hide a secret image, and employed encryption using Advanced Encryption Standard, to enhance the security of the image. An image is a two dimensional signal, with each pixel value representing the intensity level. The secure transmission of the image along the channel is a challenging task, because of the reason that, any individual can access it, if no security measures are taken. Conclusion: An efficient method of digital watermarking has been implemented with increased security and performance parameters are presented. Results: In this paper, hardware realization of image watermarking/encryption and dewatermarking/ decryption is implemented using Very Large Scale Integration. The design is verified by means of co-simulation using MATLAB and Xilinx. The paper also presents the performance parameters of the design, with respect to speed, area and power.

A low area VLSI implementation of extended tiny encryption algorithm using Lorenz chaotic system

The rapid growing impact of light weight applications (RFID tags, smartcards, sensor nodes and FGPAs) makes security a major concern in communication systems. Light weight cryptographic algorithm or ciphers can provide security and confidentiality of data or messages transmitted. In this paper, we proposed low area VLSI implementation of extended tiny encryption algorithm using Lorenz chaotic system (XTEA-LCS method) to improve the efficiency of encryption and decryption process. The key is the major concern of the encryption and decryption process. So in this research random numbers generated using LCS was used for key purpose, which efficiently reduced area and execution time of XTEA-LCS method and improved the system security. The XTEA-LCS method has been implemented in the Xilinx tool using Verilog code on different Virtex devices such as Virtex6, Low Power Virtex-6 (LP Virtex-6), and Virtex-7. In the field programmable gate array (FPGA) implementation, the number of look up tables (LUTs), slices and flip flops reduced and the frequency increased compared to the existing methods: QTL algorithm, DROM-CSLA-QTL and XTEA. The XTEA-LCS methodology improves the FPGA performances by reducing LUTs by 82.96% and slices by 74.28% than conventional XTEA method.

Fixed-Complexity Tree Search Schemes for Detecting Generalized Spatially Modulated Signals: Algorithms and Hardware Architectures

In the generalized spatial modulation (GenSM) multiple input multiple output (MIMO) system, each block of data bits is mapped to a set of spatially multiplexed (SMX) symbols and an index of transmit antenna combination (TAC) of active antennas. The difficulty for the GenSM MIMO receiver is to detect the SMX symbols and TAC index simultaneously. Recently, we applied the conventional sphere decoding algorithm (SDA) successively to achieve the exact maximum likelihood detection (MLD) of GenSM MIMO signals. The SDA scheme suffers from variable computational complexity and leads to hardware detectors with variable throughput rate. Instead, fixed-complexity tree search algorithms, e.g., reduced fixed sphere decoding (rFSD), with nearly MLD performance are employed to facilitate hardware implementation. Here, we propose to apply the rFSD successively and design a hardware architecture for detecting GenSM MIMO signals under the scenario of 5 transmit antennas, 2 transmit radio frequency chains, 4 receive antennas, and 64-QAM SMX symbols. The VLSI implementation results under the TSMC 90nm CMOS technology reveal that our architecture requires 276.7K gates and provides detection throughput 1.613 Gbps, while operating at 322.6 MHz. Compared with other related architectures, our architecture provides higher detection throughput rate and is of better hardware efficiency.

Some Algorithms for Computing Short-Length Linear Convolution

In this article, we propose a set of efficient algorithmic solutions for computing short linear convolutions focused on hardware implementation in VLSI. We consider convolutions for sequences of length N= 2, 3, 4, 5, 6, 7, and 8. Hardwired units that implement these algorithms can be used as building blocks when designing VLSI -based accelerators for more complex data processing systems. The proposed algorithms are focused on fully parallel hardware implementation, but compared to the naive approach to fully parallel hardware implementation, they require from 25% to about 60% less, depending on the length N and hardware multipliers. Since the multiplier takes up a much larger area on the chip than the adder and consumes more power, the proposed algorithms are resource-efficient and energy-efficient in terms of their hardware implementation.

WITHDRAWN: On-chip cache memory protection with tag overflow buffers and VLSI implementation

A increasing barrier in the development of the future generation of reliable microprocessors has secure memory on chip against soft bugs.Present efforts primarily focused on improving cache data set performance.A tag array also needs massive production efficiency for soft factual errors for its vital significance for caching entry accuracy.Using the memory access address location, it is recommended to repeat the most recent access to tag documents in the tiny tag duplication buffer (TRB) in order to maintain the tag list skill integrity in the cache memory.

Design and VLSI Implementation of a Sorted MMSE QR Decomposition for 4×4 MIMO Detectors

Design and VLSI Implementation of a Sorted MMSE QR Decomposition for 4×4 MIMO Detectors

Design and VLSI Implementation of a Reduced-Complexity Sorted QR Decomposition for High-Speed MIMO Systems

In this article, a low-complexity and high-throughput sorted QR decomposition (SQRD) for multiple-input multiple-output (MIMO) detectors is presented. To reduce the heavy hardware overhead of SQRD, we propose an efficient SQRD algorithm based on a novel modified real-value decomposition (RVD). Compared to the latest study, the proposed SQRD algorithm can save the computational complexity by more than 44.7% with similar bit error rate (BER) performance. Furthermore, a corresponding deeply pipelined hardware architecture implemented with the coordinate rotation digital computer (CORDIC)-based Givens rotation (GR) is designed. In the design, we propose a time-sharing Givens rotation structure utilizing CORDIC modules in idle state to share the concurrent GR operations of other CORDIC modules, which can further reduce hardware complexity and improve hardware efficiency. The proposed SQRD processor is implemented in SMIC 55-nm CMOS technology, which processes 62.5 M SQRD per second at a 250-MHz operating frequency with only 176.5 kilo-gates. Compared to related studies, the proposed design has the best normalized hardware efficiency and achieves a 6-Gbps MIMO data rate which can support current high-speed wireless communication systems such as IEEE 802.11ax.