VLSI Implementation Research Articles

Weighted edge-based low-cost artifacts-free high-quality VLSI implementation for demosaicking

Weighted edge-based low-cost artifacts-free high-quality VLSI implementation for demosaicking

A mini I2C bus interface circuit design and its VLSI implementation

A mini I2C bus interface circuit design and its VLSI implementation

VLSI implementation of an energy-efficient color image compressor using improved block truncation coding and enhanced Golomb-rice coding for wireless sensor networks

VLSI implementation of an energy-efficient color image compressor using improved block truncation coding and enhanced Golomb-rice coding for wireless sensor networks

VLSI Implementation of an Annealing Accelerator for Solving Combinatorial Optimization Problems

VLSI Implementation of an Annealing Accelerator for Solving Combinatorial Optimization Problems

An Integrated Approach towards VLSI Implementation of SFQ Logic using Standard Cell Library and Commercial Tool Suite

Abstract The semiconductor industry seeks energy-efficient alternatives as Moore’s law nears its limits. The Single Flux Quantum (SFQ) integrated circuits (ICs) using thousands of niobium Josephson junctions (JJs) and operating at 4 K show great promise for digital computing circuits at high speed (>20 GHz) and low power (a few nW per junction). The leading logic families are Rapid Single Flux Quantum (RSFQ), and its energy-efficient variant (ERSFQ). IARPA’s SuperTools program aims to develop integrated design tools for superconductor electronics, targeting SFQ and Adiabatic Quantum-Flux-Parametron (AQFP) logic families. This paper presents a passive transmission line (PTL) based standard cell library for SFQ logic, designed with Synopsys Electronic Design Automation (EDA) software tools for MIT-LL 100μA/μm2 SFQ5ee fab node. The dual RSFQ/ERSFQ standard cell library facilitates seamless integration of SFQ RTL-to-GDS design flow with Synopsys Fusion Compiler, an automated design tool. The SFQ RTL-to-GDS flow entails logic synthesis, checking, placement, clock synthesis, and routing. Row-based placement for library cells and H-tree clock tree structures are employed. Fusion Compiler’s effectiveness is validated with Hypres designs such as finite impulse response (FIR) filters, scalable multiply-accumulate (MAC) units, and memory arrays, comparing single and dual clocking schemes. The synergy between Hypres and Synopsys achieves a milestone by demonstrating the design of a digital superconducting circuit with over 10 million JJs, facilitated by a fully automated design tool for the first time. Challenges in very large-scale SFQ scaling are also discussed.

Enhancing Field Multiplication in IoT Nodes with Limited Resources: A Low-Complexity Systolic Array Solution

Enhancing Field Multiplication in IoT Nodes with Limited Resources: A Low-Complexity Systolic Array Solution

Low Power VLSI Implementation of 32-Point FFT.

Low Power VLSI Implementation of 32-Point FFT.

FPGA-Based Satellite Vision Systems using Verilog HDL

Abstract: It is believed that the most effective way to collect information about the Earth's surface is through high- quality satellite images. Extracting a feature from an image is really difficult because you have to choose the best image segmentation methods and combine many strategies to find the Region in the most effective manner. This study makes recommendations for the classification techniques for objects in the satellite. On high-resolution satellite images, applying image processing methods. The methods used to define region mostly focus on urban, agricultural, and forest regions. There are several methods for extracting these traits. Using a Grey Level Cooccurrence Matrix is the most used method. It is employed to unveil specific characteristics regarding the spatial arrangement of gray levels in the texture image. The Grey Level Co-occurrence Matrix (GLCM) captures statistical details of neighboring pixels in an image, enabling the computation of textural features that enhance the comprehension of visual content. This research presents a VLSI implementation aimed at extracting four texture characteristics from the grey level co-occurrence matrix. Verilog was employed to model the hardware, with MATLAB used for software simulation. The simulation utilized the Verilog HDL language from the XILINX tool, and the implementation was executed on the SPARTAN FPGA board.

A Quasi-Cyclic LDPC Based Low Complexity and Area-Efficient Communication System for IEEE 802.11n

Low-density parity-check (LDPC) code, which has an excellent error-correcting performance that is close to the Shannon limit, is the most often used error correction code (ECC) for reliable and effective communication. Despite higher performance and lower decoding complexity, the main disadvantage of LDPC codes is their high encoding complexity. A significant problem is the VLSI implementation of the LDPC encoder and decoder. In this paper, structured LDPC codes—also known as quasi-cyclic low-density parity check codes—have been used since it is good bit error ratio (BER) performance and adaptable hardware execution characteristics. The Complete (Encoder-Channel-Decoder) communication system with a 1/2 code rate, 648 bits codeward length, and sub-block size of z = 27 has been constructed for the IEEE 802.11n wireless standard.

An Optimized VLSI Implementation of the Least Mean Square (LMS) Adaptive Filter Architecture on the Basis of Distributed Arithmetic Approach

An Optimized VLSI Implementation of the Least Mean Square (LMS) Adaptive Filter Architecture on the Basis of Distributed Arithmetic Approach

VLSI Implementation of Speech Steganography with Advanced Wavelet Transform

In the realm of secure communication systems, the integration of advanced wavelet transforms into speech steganography systems has emerged as a promising path. Secure transmission of sensitive information in military communications, confidential exchange of data in corporate environments, and protection of personal information in telecommunication networks. However, the current system employs conventional methods of speech steganography, relying on basic encryption techniques and simplistic embedding algorithms. While functional, these approaches lack robustness and fail to adequately conceal secret data within speech signals, leaving them vulnerable to detection and interception. So, the proposed system leverages advanced wavelet transforms to enhance the security and efficiency of speech steganography. By exploiting the multi-resolution analysis capabilities of wavelets, the system achieves improved embedding capacity while maintaining perceptual transparency. Additionally, the use of dynamic embedding algorithms based on wavelet coefficients ensures adaptability to varying signal characteristics, enhancing robustness against attacks and noise interference. The VLSI implementation of this system optimizes resource utilization and computational efficiency, making it suitable for real-time applications in communication systems.

Efficient VLSI Implementation of Hybrid LDPC-STBC Codes for Enhanced Satellite Communication Systems

Satellite communication systems play a pivotal role in facilitating global connectivity, necessitating the development of robust error correction codes to ensure reliable data transmission. In contemporary communication systems, the demand for higher data rates and improved spectral efficiency has led to the integration of advanced error correction techniques. However, existing systems often face challenges in striking a balance between complexity, power consumption, and performance. This work addresses the limitations of current systems by proposing a hybrid approach that combines the advantages of LDPC (Low-Density Parity-Check) codes and STBC (Space-Time Block Coding) techniques. The hybrid LDPC-STBC codes aim to enhance the error correction capabilities of satellite communication systems, ensuring robust data transmission in the presence of channel impairments. Despite the advancements in error correction coding, current systems encounter drawbacks such as increased computational complexity, higher power consumption, and potential performance degradation under adverse channel conditions. The proposed hybrid LDPC-STBC codes mitigate these issues by leveraging the strengths of both coding schemes, achieving a synergistic balance between error correction performance and computational efficiency.

Correction to: Real-time hardware architecture of an ECG compression algorithm for IoT health care systems and its VLSI implementation

Correction to: Real-time hardware architecture of an ECG compression algorithm for IoT health care systems and its VLSI implementation

An efficient spatial representation scheme for memory-based hippocampus-inspired model with VLSI implementation

An efficient spatial representation scheme for memory-based hippocampus-inspired model with VLSI implementation

VLSI implementation of ECG feature extraction: a literature review

VLSI implementation of ECG feature extraction: a literature review

Design and VLSI implementation of SAR Analog to Digital Converter Using Analog Mixed Signal

Design and VLSI implementation of SAR Analog to Digital Converter Using Analog Mixed Signal

VLSI implementation of ECG feature extraction: a literature review

VLSI implementation of ECG feature extraction: a literature review

An Area-Efficient Unified VLSI Architecture for Type IV DCT/DST Having an Efficient Hardware Security with Low Overheads

This paper introduces an efficient solution for designing a unified VLSI implementation for type IV DCT/DST while solving one challenging problem in obtaining high performance VLSI chips for common goods, which is solving the security of the hardware while obtaining a VLSI implementation with high performance. The new solution uses a new systolic array algorithm for type IV DST that can allow us to obtain an efficient unified VLSI architecture with one previously designed for type IV DCT. The proposed method uses special arithmetic structures that have been called quasi-cycle convolutions that can be efficiently mapped on linear systolic arrays. Moreover, the obtained unified VLSI architecture, besides being an efficient implementation with a low hardware complexity and high-speed performance, allows for an efficient inclusion of the obfuscation technique with very low overheads.

VLSI Implementation of 3-Parallel FIR Filters through Coefficient Symmetry Property and Fast FIR Algorithm

In multirate digital signal processing systems, polyphase filters are frequently used. The challenges in multirate digital signal processing systems primarily relate to efficiently processing signals at different rates while maintaining high-quality output. These challenges include computational complexity, power consumption, and signal delay. The coefficient symmetry property plays a key role in systematically arranging of filter taps in symmetric manner to improve operating efficiency. With a major focus on using the coefficient symmetry characteristic, this paper addresses the VLSI implementation of traditional Type-1 polyphase FIR filters. Furthermore, this paper incorporated 3-parallel FIR filters especially for sequences with odd lengths in order to take full advantage of the coefficient symmetry characteristic. The Fast FIR Algorithm (FFA) method is used to increase overall efficiency. Furthermore, in order to achieve better performance, a modified FFA technique is introduced to enhance overall performance. The paper thoroughly investigates important VLSI factors, such as power consumption, utilization, and delay, and shows how, by utilizing coefficient symmetry and applying this modified FFA technique, filters that are optimized for both power consumption and area utilization are able to be implemented. The results illustrate a significant reduction in both area and power consumption, particularly for longer filters, attributed to the reduced number of multiplication operations inherent in the fast FIR algorithm approach. Additionally, image processing application using 3x3 FIR filter is executed.

VLSI Implementation of Hybrid Memristor Based Logic Gates

Practical memristors have gained attention from researchers and scientists due to their potential use in a variety of electronic circuits and devices. In our paper, a hybrid Memristor-CMOS (MeMOS) logic circuit was designed and its transient response was analyzed. This circuit, which uses a N-type metal oxide semiconductor (NMOS), and P-type metal oxide semiconductor (PMOS) transistors, Operational amplifiers (OPAMPs), resistors, capacitors and multipliers replicate memristor characteristics. To facilitate the development of real memristor circuit applications, a memristor emulator is utilized for breadboard experiments. This emulator can be connected in a variety of configurations, including serial, parallel, or a combination of both, with identical or opposite polarities. By simply changing the connection, the emulator can be switched between decremental and incremental configurations. In our paper, we implemented AND logic using MeMOS. PSpice simulation of the proposed emulator have been demonstrated for TiO2 memristor model.