Signal Processing Implementation Research Articles

A DSP Based H.264 Decoder for a Multi-Format IP Set-Top Box

In this paper, the implementation of a digital signal processor (DSP) based H.264 decoder for a multi-format set-top box is described. Baseline and main profiles are supported. Using several software optimization techniques, the decoder has been fitted into a low-cost DSP. The decoder alone has been tested in simulation, achieving real-time performance with a 600 MHz system clock. Moreover, it has been integrated in a multi-format IP set-top box allowing the implementation of actual environment tests with excellent results. Finally, the decoder has been ported to a latest generation DSP.

DSP implementation of a heart valve disorder detection system from a phonocardiogram signal

Auscultation, the technique of listening to heart sounds, remains a primary detection tool for diagnosing heart valve disorders. Other techniques, e.g. electrocardiography, ultrasound, etc, are accurate as well as informative; but expensive. With major advancement in the speed of computers, heart sound signals can be processed with ease by memory efficient digital signal processing and pattern recognition algorithms. This paper presents a digital signal processor (DSP) implementation of such a technique by using new threshold criteria. The proposed work can detect whether a heart sound recording belongs to a person suffering from valvular heart disease or not by giving ‘diseased’ or ‘not diseased’ decisions. The algorithm is tested for nine commonly occurring pathological problems and normal heart sound. The robustness of the algorithm is also checked against synthetically injected additive white Gaussian noise (AWGN) with different SNR levels. It is found to give an accuracy of 96.67% up to SNR values of 15 dB and 93.33% up to SNR values of 5 dB.

Real-time digital signal-processor implementation of self-calibrating pulse-shape discriminator for high-purity germanium

Pulse-shape analysis of the ionization signals from germanium gamma-ray spectrometers is a method for obtaining information that can characterize an event beyond just the total energy deposited in the crystal. However, as typically employed, this method is data-intensive requiring the digitization, transfer, and recording of electronic signals from the spectrometer. A hardware realization of a real-time digital signal processor for implementing a parametric pulse shape analysis is presented. Specifically, a previously developed method for distinguishing between single-site and multi-site gamma-ray interactions is demonstrated in an on-line digital signal processor, compared with the original off-line pulse-shape analysis routine, and shown to have no significant difference. Reduction of the amount of the recorded information per event is shown to translate into higher duty-cycle data-acquisition rates while retaining the benefits of additional event characterization from pulse-shape analysis.

Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications

This paper presents the design and implementation of a novel VLIW digital signal processor (DSP) for multimedia applications. The DSP core embodies a distributed & ping-pong register file, which saves 76.8% silicon area and improves 46.9% access time of centralized ones found in most VLIW processors by restricting its access patterns. However, it still has comparable performance (estimated in cycles) with state-of-the-art DSP for multimedia applications. A hierarchical instruction encoding scheme is also adopted to reduce the program sizes to 24.1~26.0%. The DSP has been fabricated in the UMC 0.13 μm 1P8M Copper Logic Process, and it can operate at 333 MHz while consuming 189 mW power. The core size is 3.2?×?3.15 mm2 including 160 KB on-chip SRAM.

Hidden Markov Models and Multiple Transfer Functions for Voice Subtraction in an Acoustic Dosimeter

The exposure of an individual to noise is a critical topic in relation to noise-induced hearing loss and noise annoyance. Unfortunately, this exposure is difficult to quantify, because the individual's voice affects the noise itself. A new dosimeter is presented, relying on an accelerometer and a microphone system. The accelerometer (placed behind the user's ear, in close contact with the skull) is moderately sensitive to environmental noise. It can be used as an estimate of the clean voice, which can then be removed from the overall acoustic signal. Eventually, the voice-free signal can be processed to measure the noise exposure in a straightforward manner. In order to obtain an estimate of the clean voice, the accelerometric signal may be mapped to a virtual microphone signal. We apply autoregressive exogenous (ARX) models to realize such a mapping. As the ARX is a time-invariant model, we use hidden Markov models to split the input sequence into segments on a phonetic-class basis. Specialized ARX models are then estimated for each one of the classes. Simulation results and a real-world binaural digital signal processing (DSP) implementation of the system validate the approach to a significant extent.

Algorithmic and architectural design for real-time and power-efficient Retinex image/video processing

This paper presents novel algorithmic and architectural solutions for real-time and power-efficient enhancement of images and video sequences. A programmable class of Retinex-like filters, based on the separation of the illumination and reflectance components, is proposed. The dynamic range of the input image is controlled by applying a suitable non-linear function to the illumination, while the details are enhanced by processing the reflectance. An innovative spatially recursive rational filter is used to estimate the illumination. Moreover, to improve the visual quality results of two-branch Retinex operators when applied to videos, a novel three-branch technique is proposed which exploits both spatial and temporal filtering. Real-time implementation is obtained by designing an Application Specific Instruction-set Processor (ASIP). Optimizations are addressed at algorithmic and architectural levels. The former involves arithmetic accuracy definition and linearization of non-linear operators; the latter includes customized instruction set, dedicated memory structure, adapted pipeline, bypasses, custom address generator, and special looping structures. The ASIP is synthesized in standard-cells CMOS technology and its performances are compared to known Digital signal processor (DSP) implementations of real-time Retinex filters. As a result of the comparison, the proposed algorithmic/architectural design outperforms state-of-art Retinex-like operators achieving the best trade-off between power consumption, flexibility, and visual quality.

A Processor-In-Memory Architecture for Multimedia Compression

This paper presents the design and development of a novel, low-complexity processor-in-memory (PIM) architecture for image and video compression. By integrating a novel-processing element with SRAM, bandwidth is improved and latency is greatly reduced. This paper also presents PIM design techniques for reduced power, area, and complexity for rapid deployment and reduced cost. A design methodology is presented and followed by an analysis of the processing element performance and capabilities. The proposed datapath solution delivers between 2 to 40 times higher performance compared to other presented solutions. The architecture executes a discrete cosine and wavelet transforms achieving up to 40% higher throughput per watt and occupying as little as 0.9% area compared to a commercial digital signal processing and other application-specified integrated circuit implementations while maintaining precision. A comprehensive comparative analysis is also provided. The proposed processor-in-memory is implemented in 1.8-V 0.18-mum CMOS technology and operates with a 300-MHz clock

Binaural speech enhancement by complex wavelet transform based on interaural level and argument differences

Binaural information might enhance speech signals in noisy environments. Most precedent studies in this area have implemented signal processing in time and frequency domains. For this study, an enhancement method using complex wavelet transform (CWT) was proposed. The CWT has a scale domain whose bandwidth is inversely proportional to the scale level and may therefore be well compared to auditory filters. The proposed processing procedure is the following: (1) By computing CWT for a sound signal at every direction of arrival (DOA), a database (DB) of the scale domain wavelet coefficients is prepared for every DOA. (2) For binaural input signals from an unknown direction, the scale domain wavelet coefficients are calculated using CWT. (3) The DOA of the input signal is estimated as the direction for which interaural level and argument differences calculated from wavelet coefficients are the most similar to those in the DB. (4) The input signal is segregated similarly to FDBM (Nakashima et al., 2003) based on the estimated DOA. Experiments with a directional target signal and an interference sound source calculated from real HRTFs were conducted to show the effectiveness of the proposed algorithm. [This research was partially supported by Sendai Intelligent Knowledge Cluster.]

Hardware implementation of smart antenna systems

Abstract. Smart antenna systems attract a lot attentions now and believably more in the future, as it can increase the capacity of mobile communication systems dramatically. Design of smart antenna systems combines the technologies of antenna design, signal processing, and hardware implementation. In this paper, a propose of smart antenna structure, as well as some function blocks that have been already implemented in hardware will be presented.

Phase-resolved fluorescence technique with heterodyne signal processing for imaging of latent fingerprints

This paper describes the formulation and implementation of signal processing and experimental details of a system incorporating the heterodyne concept with a phase-resolved fluorescence technique for the detection and separation of latent fingerprint fluorescence emission from background fluorescence. The excitation laser source and gain of the detection device, which are modulated at megahertz frequency, are employed together with a heterodyne signal processing technique to separate the fingerprint fluorescence from the background fluorescence. The method provides improved contrast of fingerprint ridges. Experiments have been carried out on fingerprints deposited on various surfaces.

ON USING LINEAR PERIODICALLY RESETTING FILTER IN CURRENT CONTROL LOOP FOR ACTIVE POWER FILTER

Among linear control techniques, deadbeat control has been widely accepted as a feasible current control technique as far as the digital signal processor (DSP) implementation of active power filter (APF) is concerned. This control technique uses high gain on the error measured at one sample, to control the error ideally to zero by the next sample. The high gain makes the control very sensitive to any error or noise in the measurements, which is always there in electrical systems. Especially, the periodic noise in parallel implementation of an inverter or APF demands a higher order filter at the current transducer output, which affects the dynamic response of the system. Recently, few papers have reported the results about the use of linear periodically resetting integrators (LPRI) as filter in some electronic applications. This paper is an attempt to generalize the idea of LPRI and here we introduce the notion of linear periodically resetting filter (LPRF). The frequency characteristics of an LPRF are analyzed. Possible application of these filters in current control is studied. It is shown that these filters can be adopted to improve the performances of a current loop in APF.

Real time digital signal processing implementation for an APD-based PET scanner with phoswich detectors

Recent progress in advanced digital signal processing provides an opportunity to expand the computation power required for real time extraction of event characteristics in avalanche photodiode (APD)-based Positron Emission Tomography (PET) scanners. These developments are made possible by a highly parallel data acquisition (DAQ) system based on an integrated analog front-end and a high-speed fully digital signal processing section that directly samples the output of each preamplifier with a free-running, off-the-shelf, 45-MHz analog-to-digital converter that feeds the sampled data into a field programmable gate array (FPGA) VirtexII PRO from Xilinx. This FPGA features /spl sim/ 31 000 logic cells and two PowerPC processors, which allows up to 64 channels to be processed simultaneously. Each channel has its own digital signal processing chain including a trigger, a baseline restorer and a timestamp algorithm. Various timestamp algorithms have been tested so far, achieving a coincidence timing resolution of 3.2-ns full-width at half-maximum (FWHM) for APD coupled to Lutetium Oxyorthosilicate (APD-LSO) and 11.4-ns FWHM for APD coupled to Bismuth Germanium Oxide (APD-BGO) detectors, respectively. Channels are then multiplexed into a DSP processor from Texas Instruments for crystal identification by an ARMAX recursive algorithm borrowed from identification and vector quantization theory. The system can sustain an event rate of 10 000 events/s/channel without electronic dead time.

Real-Time Signal Processing for Multiantenna Systems: Algorithms, Optimization, and Implementation on an Experimental Test-Bed

A recently realized concept of a reconfigurable hardware test-bed suitable for real-time mobile communication with multiple antennas is presented in this paper. We discuss the reasons and prerequisites for real-time capable MIMO transmission systems which may allow channel adaptive transmission to increase link stability and data throughput. We describe a concept of an efficient implementation of MIMO signal processing using FPGAs and DSPs. We focus on some basic linear and nonlinear MIMO detection and precoding algorithms and their optimization for a DSP target, and a few principal steps for computational performance enhancement are outlined. An experimental verification of several real-time MIMO transmission schemes at high data rates in a typical office scenario is presented and results on the achieved BER and throughput performance are given. The different transmission schemes used either channel state information at both sides of the link or at one side only (transmitter or receiver). Spectral efficiencies of more than 20 bits/s/Hz and a throughput of more than 150 Mbps were shown with a single-carrier transmission. The experimental results clearly show the feasibility of real-time high data rate MIMO techniques with state-of-the-art hardware and that more sophisticated baseband signal processing will be an essential part of future communication systems. A discussion on implementation challenges towards future wireless communication systems supporting higher data rates (1 Gbps and beyond) or high mobility concludes the paper.

Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware Functions

This paper presents an architecture that combines VLIW (very long instruction word) processing with the capability to introduce application-specific customized instructions and highly parallel combinational hardware functions for the acceleration of signal processing applications. To support this architecture, a compilation and design automation flow is described for algorithms written in C. The key contributions of this paper are as follows: (1) a 4-way VLIW processor implemented in an FPGA, (2) large speedups through hardware functions, (3) a hardware/software interface with zero overhead, (4) a design methodology for implementing signal processing applications on this architecture, (5) tractable design automation techniques for extracting and synthesizing hardware functions. Several design tradeoffs for the architecture were examined including the number of VLIW functional units and register file size. The architecture was implemented on an Altera Stratix II FPGA. The Stratix II device was selected because it offers a large number of high-speed DSP (digital signal processing) blocks that execute multiply-accumulate operations. Using the MediaBench benchmark suite, we tested our methodology and architecture to accelerate software. Our combined VLIW processor with hardware functions was compared to that of software executing on a RISC processor, specifically the soft core embedded NIOS II processor. For software kernels converted into hardware functions, we show a hardware performance multiplier of up to times that of software with an average times faster. For the entire application in which only a portion of the software is converted to hardware, the performance improvement is as much as 30X times faster than the nonaccelerated application, with a 12X improvement on average.

A DSP based IP set-top box for home entertainment

In this paper, the implementation of a digital signal processor (DSP) based Internet protocol set-top box for home entertainment networks is described. The main functional blocks are the MPEG-2 transport stream demultiplexer, the audio and video decoders and the audio and video display management modules (with on-screen display capabilities). All blocks have been built into a single low-cost DSP to allow multi-format operation in the future. A prototype has been designed and fully tested in a real environment.

Continuous wavelet transform technique for fault signal diagnosis of internal combustion engines

A fault signal diagnosis technique for internal combustion engines that uses a continuous wavelet transform algorithm is presented in this paper. The use of mechanical vibration and acoustic emission signals for fault diagnosis in rotating machinery has grown significantly due to advances in the progress of digital signal processing algorithms and implementation techniques. The conventional diagnosis technology using acoustic and vibration signals already exists in the form of techniques applying the time and frequency domain of signals, and analyzing the difference of signals in the spectrum. Unfortunately, in some applications the performance is limited, such as when a smearing problem arises at various rates of engine revolution, or when the signals caused by a damaged element are buried in broadband background noise. In the present study, a continuous wavelet transform technique for the fault signal diagnosis is proposed. In the experimental work, the proposed continuous wavelet algorithm was used for fault signal diagnosis in an internal combustion engine and its cooling system. The experimental results indicated that the proposed continuous wavelet transform technique is effective in fault signal diagnosis for both experimental cases. Furthermore, a characteristic analysis and experimental comparison of the vibration signal and acoustic emission signal analysis with the proposed algorithm are also presented in this report.

Near-Field Sound-Source Localization Based on a Signed Binary Code

This paper proposes near-field sound-source localization based on crosscorrelation of a signed binary code. The signed binary code eliminates multibit signal processing for simpler implementation. Explicit formulae with near-field assumption are derived for a two microphone scenario and extended to a three microphone case with front-rear discrimination. Adaptive threshold for enabling and disabling source localization is developed for robustness in noisy environment. The proposed sound-source localization algorithm is implemented on a fixed-point DSP. Evaluation results in a robot scenario demonstrate that near-field assumption and front-rear discrimination provides almost 40% improvement in DOA estimation. A correct detection rate of 85% is obtained by a robot in a home environment.

A new SOI monolithic capacitive sensor for absolute and differential pressure measurements

In the present work, a new monolithic capacitive pressure sensor is being introduced. The sensor is manufactured according to a custom, 15-step SOI process. The process primarily offers great flexibility as far as sensor design is concerned. Absolute or differential pressure sensing is possible by simply arranging proper sensor package. Measurement sensitivity and span are easily regulated over a wide range of values by setting one-single design parameter. Attention is paid to avoid p–n junction formation in order to improve the sensor robustness against temperature increase and allow high-temperature post-processing without doping profile degradation. The presented design allows the implementation of an ordinary p-well CMOS post-process. Sensitivity of 2 mV/kPa, within a span of 180 kPa (2%) and a bandwidth of 25 kHz, is achievable by means of a CMOS switched-capacitor ASIC that is developed and presented here. Significant care has been taken for the ASIC performance to depend as less as possible on CMOS process and transistor-parameter variations that increase due to poor uniformity of the transistor substrate. Moreover, a state-of-the-art design is implemented for the circuit to provide robustness against parasitic capacitances connected in parallel with sensing capacitors. Implementation of additional analog signal processing improves the aforementioned accuracy at a significant extend. The sensors main applications include medical devices such as sphygmomanometers and respirators that require high reliability and biocompatibility.

Discrete-time synthesis of the sawtooth waveform with reduced aliasing

An efficient signal processing algorithm for generating a sawtooth waveform is proposed. The algorithm improves the trivial waveform sampling method, which suffers from low sound quality due to aliasing. The basic version of the new algorithm differentiates a piecewise parabolic waveform. Another version of the algorithm oversamples and decimates the parabolic wave with a simple filter prior to differentiation. The two algorithm variants improve the signal-to-noise ratio (SNR) over the trivial method by 10 and 15 dB, respectively. A perceptually weighted SNR suggests a larger subjective improvement. The proposed methods are applicable in a digital signal processor (DSP) implementation of subtractive sound synthesis.

Implementation and Performance Evaluation of DSP-Based Control for Constant-Frequency Discontinuous-Conduction-Mode Boost PFC Front End

A digital signal processor (DSP) implementation of digital control for constant-frequency, discontinuous-conduction-mode boost power-factor-correction converter for universal line-voltage (90-264 V/sub rms/) applications is presented. A step-by-step design procedure based on digital redesign technique is also provided. The performance evaluation of the proposed DSP control is performed on a 400-W prototype. It was shown that the implemented DSP-based control can achieve a power factor higher than 0.99 in the entire line range.