Implementation Of Random Access Memory Research Articles

Voltage-Tunable Superconducting Resonators: A Platform for Random Access Quantum Memory

In quantum computing architectures, one important factor is the trade-off between the need to couple qubits to each other and to an external drive and the need to isolate them well enough in order to protect the information for an extended period of time. In the case of superconducting circuits, one approach is to utilize fixed frequency qubits coupled to coplanar waveguide resonators such that the system can be kept in a configuration that is relatively insensitive to noise. Here, we propose a scalable voltage-tunable quantum memory (QuMem) design concept compatible with superconducting qubit platforms. Our design builds on the recent progress in fabrication of Josephson field effect transistors (JJ-FETs) which use InAs quantum wells. The JJ-FET is incorporated into a tunable coupler between a transmission line and a high-quality resonator in order to control the overall inductance of the coupler. A full isolation of the high-quality resonator can be achieved by turning off the JJ-FET. This could allow for long coherence times and protection of the quantum information inside the storage cavity. The proposed design would facilitate the implementation of random access memory for storage of quantum information in between computational gate operations.

Implementation of Low Power Memory on FPGA

Clock gating is a prominent and an efficacious methodology adopted to decrease the dynamic power (clock power) utilization in complementary metal oxide semiconductor (CMOS) based circuits. The sole intent of gating a clock signal is to minimize its switching activity and thereby reduce significant amount of power utilization of the clock signal. Memories or storage elements are the integral part of the complex designs used in the modern day devices enabling storage of exhaustive and crucial values being processed. In this paper, we present the design and implementation of Random Access Memory (RAM) with reduced power consumption using clock gating technique on a Field Programmable Gate Array (FPGA). These memory elements can be either of synchronous or asynchronous nature. The memories discussed in the proposed work are synchronous in nature and hence reading and writing operations take place on the positive or rising edge of the clock. A gating logic is applied to lessen the superfluous transitions of the clock signal propagating along the clock network of the circuit. The target device (FPGA) for this work is Xilinx Spartan 6 and the design tool is Xilinx ISE 14.7 with the memories being modelled in Verilog HDL and simulation outputs shown in ISim.

ASSOCIATIVE AND RANDOM ACCESS MEMORY USING ONE-DIMENSIONAL MAPS

A method for storing and retrieving information on the stable cycles of one-dimensional maps as proposed in Dmitriev [1991], Dmitriev, Panas & Starkov [1991] is considered. The applicability of this method in storing and retrieving two-dimensional pictures is demonstrated. Possible extensions by compressing information are discussed. An implementation of random access memory using a one-dimensional map is also considered.