Implementation Of Priority Queue Research Articles

A New FPGA-Based Task Scheduler for Real-Time Systems

This research demonstrates a novel design of an FPGA-implemented task scheduler for real-time systems that supports both aperiodic and periodic tasks. The periodic tasks are automatically restarted once their period has expired without any need for software intervention. The proposed scheduler utilizes the Earliest-Deadline First (EDF) algorithm and is optimized for multi-core CPUs, capable of executing up to four threads simultaneously. The scheduler also provides support for task suspension, resumption, and enabling inter-task synchronization. The design is based on priority queues, which play a crucial role in decision making and time management. Thanks to the hardware acceleration of the scheduler and the hardware implementation of priority queues, it operates in only two clock cycles, regardless of the number of tasks in the system. The results of the FPGA synthesis, performed on an Intel FPGA device (Cyclone V family), are presented in the paper. The proposed solution was validated through a simplified version of the Universal Verification Methodology (UVM) with millions of test instructions and random deadline and period values.

Implementation of a queue with priority with parameterizable variables to improve QoS

This article presents the implementation of a priority queue with simulated parameterized components on the scenario of a banking institution in which four main elements were used: 1) the dispenser, 2) the cashier(s), 3) the server that receives and assigns the priority of the turns, and 4) a screen that displays the order of the turns. In any banking institution, there is always a large number of users that require attention, so they implement special turns to give priority to customers, improving the quality of service. One of the important elements within the cycle of service provision is related to the waiting lines, commonly called queues. Basically one queue is managed with the First-In, First-Out discipline. In this aspect, disciplines such as queuing theory help to understand the behavior of queues by examining all the components of the waiting lists. One of the most used disciplines for the management of a queue, is the enqueue with priority. In a priority queue, the element with the highest priority is removed before any other elements. The research was carried out using mainly a quantitative approach. The main goal of this type of research is the formulation and demonstration of theories and seeks that the studies carried out can be replicated. The algorithm implemented highly parameterizable allowed the correct simulation of a priority queue that can be taken as a basis for a subsequent application in any type of organization.

Lease/Release

High memory contention is generally agreed to be a worst-case scenario for concurrent data structures. There has been a significant amount of research effort spent investigating designs that minimize contention, and several programming techniques have been proposed to mitigate its effects. However, there are currently few architectural mechanisms to allow scaling contended data structures at high thread counts. In this article, we investigate hardware support for scalable contended data structures. We propose Lease/Release, a simple addition to standard directory-based MESI cache coherence protocols, allowing participants to lease memory, at the granularity of cache lines, by delaying coherence messages for a short, bounded period of time. Our analysis shows that Lease/Release can significantly reduce the overheads of contention for both non-blocking (lock-free) and lock-based data structure implementations while ensuring that no deadlocks are introduced. We validate Lease/Release empirically on the Graphite multiprocessor simulator on a range of data structures, including queue, stack, and priority queue implementations, as well as on transactional applications. Results show that Lease/Release consistently improves both throughput and energy usage, by up to 5x, both for lock-free and lock-based data structure designs.

A segment tree based Top-k RMQ algorithm and its application to the autocomplete problem

Mikhail S. Dvoretckii - MSc Program Student, Lomonosov Moscow State University; Programmer, IQ Systems LLCAddress: 1, Leninskie Gory, Moscow, 119991, Russian FederationE-mail: mike.dvorecky@gmail.com An important way of ensuring data quality is controlling data input. One of the methods of doing that is checking the input data against the corresponding reference data where applicable. This may be done via autocomplete. Since reference data is usually stored in a centralized fashion, autocomplete algorithms usually run in client-server architectures and face strict time requirements. In this article, a new autocomplete task decomposition is formulated using an existing method based on range minimum queries (RMQ). The Top-k RMQ problem is formulated and used in the autocomplete problem decomposition. A segment tree based algorithm is proposed for the Top-k RMQ problem. While the conventional segment tree based RMQ algorithm when used in autocomplete (in the Top-k RMQ sub-problem) repeatedly processes the same nodes on the tree, the proposed algorithm is adapted directly to the Top-k RMQ problem and does not require any node of the segment tree to be processed more than twice. A complexity analysis is made for both the new Top-k RMQ algorithm and the conventional segment tree-based RMQ approach. This analysis considers different implementations of priority queues used in these algorithms, specifically binary heaps and ordered arrays. The new algorithm has time complexity that is not lower than that of the conventional algorithms with any priority queue implementation. To prove the practical value of the new algorithm, a series of experiments was conducted using the data from the All-Russian Classifier of Addresses - a practical source of reference data for Russian address inputs. The new algorithm demonstrates better time efficiency than the conventional one in all experiments with all priority queue implementations.

Lease/release

High memory contention is generally agreed to be a worst-case scenario for concurrent data structures. There has been a significant amount of research effort spent investigating designs which minimize contention, and several programming techniques have been proposed to mitigate its effects. However, there are currently few architectural mechanisms to allow scaling contended data structures at high thread counts. In this paper, we investigate hardware support for scalable contended data structures. We propose Lease/Release, a simple addition to standard directory-based MSI cache coherence protocols, allowing participants to lease memory, at the granularity of cache lines, by delaying coherence messages for a short, bounded period of time. Our analysis shows that Lease/Release can significantly reduce the overheads of contention for both non-blocking (lock-free) and lock-based data structure implementations, while ensuring that no deadlocks are introduced. We validate Lease/Release empirically on the Graphite multiprocessor simulator, on a range of data structures, including queue, stack, and priority queue implementations, as well as on transactional applications. Results show that Lease/Release consistently improves both throughput and energy usage, by up to 5x, both for lock-free and lock-based data structure designs.

Controller area network with priority queues and FIFO queues: improved schedulability analysis and message set extension

Controller area network (CAN) enables communication of electronic control units (ECUs) via messages using priority-based arbitration, which requires the implementation of priority queues (PQs) in the ECU device driver. Nevertheless, it is possible that not all ECUs on a CAN support PQs but use FIFO queues (FQs) instead. In this case, the classical CAN scheduling model with PQs is not suitable for the computation of message worst-case response times (WCRTs) that are essential for verifying the correct vehicle operation. This paper considers an existing scheduling model for CAN with both PQs and FQs. First, an improved algorithm for speeding up the WCRT computation is proposed. Second, the practical case where an existing CAN message set is extended by new messages is addressed. An original algorithm for assigning priorities to new messages while keeping the priority order of existing messages is developed. Both algorithms are evaluated by computational experiments.

Design and Implementation of Wireless Sensor Network Data Transfer Protocol

This paper discussed the problem of wireless sensor network data transmission protocols, and combined with the characteristics of WSN and the actual needs, the design and implementation of a data transmission priority queue and priority transmission scheme of ACK, provide an end-to-end transmission for the important information, and achieve the timely, reliable transmission of control information.

Recursive design of hardware priority queues

A recursive and fast construction of an n-element priority queue from exponentially smaller hardware priority queues and size n RAM is presented. All priority queue implementations to date require either O(logn) instructions per operation or, exponential (with key size) space or, expensive special hardware whose cost and latency dramatically increases with the priority queue size. Hence constructing a priority queue (PQ) from considerably smaller hardware priority queues (which are also much faster) while maintaining the O(1) steps per PQ operation is critical. Here we present such an acceleration technique called the Power Priority Queue (PPQ) technique. Specifically, an n-element PPQ is constructed from 2k-1 primitive priority queues of size nk(k=2,3,…) and a RAM of size n, where the throughput of the construct beats that of a single, size n primitive hardware priority queue. For example an n-element PQ can be constructed from either three n or five n3 primitive H/W priority queues.Applying our technique to a TCAM based priority queue, results in TCAM-PPQ, a scalable perfect line rate fair queuing of millions of concurrent connections at speeds of 100Gbps. This demonstrates the benefits of our scheme; when used with hardware TCAM. We expect similar results with systolic arrays, shift-registers and similar technologies.As a byproduct of our technique we present an O(n) time sorting algorithm in a system equipped with a Own entries TCAM, where here n is the number of items, and w is the maximum number of bits required to represent an item, improving on a previous result that used an Ω(n) entries TCAM. Finally, we provide a lower bound on the time complexity of sorting n-element with TCAM of size O(n) that matches our TCAM based sorting algorithm.

Least Cost Path Discovery over Graphs Defined for Large Volumes of Data Satisfying Node and Link Constraints

Computing shortest paths in graphs is one of the most fundamental and well-studied problems in combinatorial optimization. Numerous real-world applications have stimulated research investigations in this area. Several applications include large graphs involving thousands of nodes, which we cannot assume to be fully loaded into memory. The problem is of much interest, when the nodes and edges have several constraints to be satisfied apart from being large, in the computation of shortest path. Conventional Dijkstra’s algorithm does not serve the purpose. There has not been much research done in this area, although some papers investigate the problem of large graphs. The problem of finding an efficient point-to-point shortest path algorithm for graphs of larger sizes, satisfying node as well as link constraints is solved using two optimization strategies. First, we implement bi-directional Dijkstra’s algorithm with priority queue implementation using the heuristic value, in the path finding. The bi-directional strategy reduces the search space. Second, we introduce index of the graph table to preserve the local shortest segments, and exploit the table to further improve the performance. The final experimental results illustrates that this novel approach with the optimization strategies achieves high scalability and performance. General Terms Graph Theory, Algorithms

Formal Specification and Implementation of Priority Queue using Stream Functions

Formal specification of software components, as a core research area in software engineering, has been widely studied for decades. Although quite a few formal models have been proposed for this purpose, specification of concrete software components is still a challenging task due to the complexity of the functionalities of the components. In this paper, the authors use the stream function model to specify the behavior of priority queue, a commonly used software component. This specification formally defines the regular behavior and fault tolerance behavior of priority queue. In particular, a priority-concatenation operator is defined to handle the ordering of data items to ensure the highest-priority item is removed first. A finite state machine is built based on this specification as an implementation of priority queue. In addition, the authors also discuss a priority upgrading approach to handle possible starvation situation of low-priority data items in the priority queue.

Per-Flow Queue Management with Succinct Priority Indexing Structures for High Speed Packet Scheduling

Priority queues are essential building blocks for implementing advanced per-flow service disciplines and hierarchical quality-of-service at high-speed network links. Scalable priority queue implementation requires solutions to two fundamental problems. The first is to sort queue elements in real time at ever increasing line speeds (e.g., at OC-768 rates). The second is to store a huge number of packets (e.g., millions of packets). In this paper, we propose novel solutions by decomposing the problem into two parts, a succinct priority index (PI) in SRAM that can efficiently maintain a real-time sorting of priorities, coupled with a DRAM-based implementation of large packet buffers. In particular, we propose three related novel succinct PI data structures for implementing high-speed PIs: a PI, a counting priority index (CPI), and a pipelined counting priority index (pCPI). We show that all three structures can be very compactly implemented in SRAM using only ⊖(U) space, where U is the size of the universe required to implement the priority keys (time stamps). We also show that our proposed PI structures can be implemented very efficiently as well by leveraging hardware-optimized instructions that are readily available in modern 64-bit processors. The operations on the PI and CPI structures take ⊖(logW U) time complexity, where W is the processor word length (i.e., W = 64). Alternatively, operations on the pCPI structure take amortized constant time with only ⊖(logW U) pipeline stages (e.g., only four pipeline stages for U = 16 million). Finally, we show the application of our proposed PI structures for the scalable management of large packet buffers at line speeds. The pCPI structure can be implemented efficiently in high-performance network processing applications such as advanced per-flow scheduling with quality-of-service guarantee.

Ladder queue

This article describes a new priority queue implementation for managing the pending event set in discrete event simulation. Extensive empirical results demonstrate that it consistently outperforms other current popular candidates. This new implementation, called Ladder Queue, is also theoretically justified to have O (1) amortized access time complexity, as long as the mean jump parameter of the priority increment distribution is finite and greater than zero, regardless of its variance. Many practical priority increment distributions satisfy this condition including unbounded variance distributions like the Pareto distribution. This renders the LadderQ the ideal discrete event queue structure for stable O (1) performance even under practical queue distributions with infinite variance. Numerical simulations ranging from 100 to 10 million events affirm the O (1) property of LadderQ and that it is a superior structure for large-scale discrete event simulation.

Fast and lock-free concurrent priority queues for multi-thread systems

We present an efficient and practical lock-free implementation of a concurrent priority queue that is suitable for both fully concurrent (large multi-processor) systems as well as pre-emptive (multi-process) systems. Many algorithms for concurrent priority queues are based on mutual exclusion. However, mutual exclusion causes blocking which has several drawbacks and degrades the overall performance of the system. Non-blocking algorithms avoid blocking, and several implementations have been proposed. Previously known non-blocking algorithms of priority queues did not perform well in practice because of their complexity, and they are often based on non-available atomic synchronization primitives. Our algorithm is based on the randomized sequential list structure called Skiplist, and a real-time extension of our algorithm is also described. In our performance evaluation we compare our algorithm with a well-representable set of earlier known implementations of priority queues. The experimental results clearly show that our lock-free implementation outperforms the other lock-based implementations in practical scenarios for 3 threads and more, both on fully concurrent as well as on pre-emptive systems.

Reflected min-max heaps

In this paper we present a simple and efficient implementation of a min-max priority queue, reflected min-max priority queues. The main merits of our construction are threefold. First, the space utilization of the reflected min-max heaps is much better than the naive solution of putting two heaps back-to-back. Second, the methods applied in this structure can be easily used to transform ordinary priority queues into min-max priority queues. Third, when considering only the setting of min-max priority queues, we support merging in constant worst-case time which is a clear improvement over the best worst-case bounds achieved by Høyer.

Algorithms for modeling anatomic and target volumes in image‐guided neurosurgery and radiotherapy

The use of image‐guidance in surgery and radiotherapy has significantly improved patient outcome in neurosurgery and radiotherapy treatments. This work developed volume definition and verification techniques for image‐guided applications, using a number of algorithms ranging from image processing to visualization. Stereoscopic visualization, volumetric tumor model overlaid on an ultrasound image, and visualization of the treatment geometry were experimented with on a neurosurgical workstation. Visualization and volume definition tools were developed for radiotherapy treatment planning system. The magnetic resonance inhomogeneity correction developed in this work, possibly the first published data‐driven method with wide applicability, automatically mitigates the radio‐frequency (RF) field inhomogeneity artifact present in magnetic resonance images. Correcting the RF inhomogeneity improves the accuracy of the generated volumetric models. Various techniques to improve region growing are also presented. The simplex search method and combinatory similarity terms were used to improve the similarity function with a low additional computational cost and high yield in region correctness. Moreover, the effects of different priority queue implementations were studied. A fast algorithm for calculating high‐quality digitally reconstructed radiographs has been developed and shown to better meet typical radiotherapy needs than the two alternative algorithms. A novel visualization method, beam's light view, is presented. It uses texture mapping for projecting the fluence of a radiation field on an arbitrary surface. This work describes several improved algorithms for image processing, segmentation, and visualization used in image‐guided treatment systems. These algorithms increase the accuracy of image‐guidance, which can further improve the applicability and efficiency of image‐guided treatments.

Rapid simulator development for multicast protocol analysis

When evaluating new protocols and algorithms it is often desirable to be able to rapidly build a specialized simulator from scratch. The advantage of this approach is that software designers can avoid the often-steep learning curve associated with using existing simulators, and that specialized simulators can have significant computational advantages over general-purpose programs. The drawback is that simulators can be complex to develop and debug. This paper describes our experiences developing SESAME, a Java-based simulator designed to analyze multicast protocol performance. By using an appropriate set of design patterns we were able to rapidly develop a reusable and easy-to-implement framework for multicast algorithm and protocol analysis. We developed several useful approaches for rapid simulation development, including a multicast visualization tool and techniques for simulating concurrent processing within a computer network that substantially simplified code development and maintenance. Owing to performance concerns, we also ran an extensive series of performance tests of different priority queue implementations. Our design approach and the lessons that we learned in developing SESAME can be applied to rapid simulation development in general. Further, our performance results suggest that by using commercial off-the-shelf Java development environments it is possible to obtain sufficient performance for many time-sensitive applications such as discrete event simulation. Copyright © 2001 John Wiley & Sons, Ltd.

An experimental study of priority queues in external memory

In this paper we compare the performance of eight different priority queue implementations: four of them are explicitly designed to work in an external-memory setting, the others are standard internal-memory queues available in the LEDA library [Mehlhorn and Näher 1999]. Two of the external-memory priority queues are obtained by engineering known internal-memory priority queues with the aim of achieving effective performance on external storage devices (i.e., Radix heaps [Ahuja et al. 1990] and array heaps [Thorup 1996]). Our experimental framework includes some simple tests, like random sequences of insert or delete-minimum operations, as well as more advanced tests consisting of intermixed sequences of update operations and "application driven" update sequences originated by simulations of Dijkstra's algorithm on large graph instances. Our variegate spectrum of experimental results gives a good picture of the features of these priority queues, thus being helpful to anyone interested in the use of such data structures on very large data sets.

Parallel priority queues based on binomial heaps

We present an optimal parallel implementation of a meldable priority queue based on the binomial heap data structure. Our main result is an interesting application of the parallel computation of carry bits in a full adder logic to binomial heaps, thus optimizing the parallel time complexity of the Union (often called melding) of two queues. The Union operation as well as Insert, Min, Extract-Min and Multiple-Insert require doubly logarithmic time and are work-optimal, employing p∈ Θ(log n/loglog n) processors on the EREW–PRAM model. Parallel algorithms for Delete and Decrease-Key operations work by postponing the global effect of a node deletion/update, and achieve doubly logarithmic time and work-optimality in the amortized sense.

Priority queues and sorting methods for parallel simulation

The authors examine the design, implementation, and experimental analysis of parallel priority queues for device and network simulation. They consider: 1) distributed splay trees using MPI; 2) concurrent heaps using shared memory atomic locks; and 3) a new, more general concurrent data structure based on distributed sorted lists, designed to provide dynamically balanced work allocation and efficient use of shared memory resources. We evaluate performance for all three data structures on a Cray-TSESOO system at KFA-Julich. Our comparisons are based on simulations of single buffers and a 64/spl times/64 packet switch which supports multicasting. In all implementations, PEs monitor traffic at their preassigned input/output ports, while priority queue elements are distributed across the Cray-TBE virtual shared memory. Our experiments with up to 60000 packets and two to 64 PEs indicate that concurrent priority queues perform much better than distributed ones. Both concurrent implementations have comparable performance, while our new data structure uses less memory and has been further optimized. We also consider parallel simulation for symmetric networks by sorting integer conflict functions and implementing a packet indexing scheme. The optimized message passing network simulator can process /spl sim/500 K packet moves in one second, with an efficiency that exceeds /spl sim/50 percent for a few thousand packets on the Cray-T3E with 32 PEs. All developed data structures form a parallel library. Although our concurrent implementations use the Cray-TSE ShMem library, portability can be derived from Open-MP or MP1-2 standard libraries, which will provide support for one-way communication and shared memory lock mechanisms.

A comparative study of parallel and sequential priority queue algorithms

Priority queues are used in many applications including real-time systems, operating systems, and simulations. Their implementation may have a profound effect on the performance of such applications. In this article, we study the performance of well-known sequential priority queue implementations and the recently proposed parallel access priority queues. To accurately assess the performance of a priority queue, the performance measurement methodology must be appropriate. We use the Classic Hold, the Markov Model, and an Up/Down access pattern to measure performance and look at both the average access time and the worst-case time that are of vital interest to real-tiem applicatons. Our results suggest that the best choice for priority queue algorithms depends heavily on the application. For queue sizes smaller than 1,000 elements, the Splay Tree, the Skew Heap, and Henriksen's algorithm show good average access times. For large queue sized of 5,000 elements or more, the Calendar Queue and the Lazy Queue offer good average access times but have very long worst-case access times. The Skew Heap and the splay Tree exhibit the best worst-case access times. Among the parallel access priority queues tested, the Parallel Access Skew Heap provides the best performance on small shares memory multiprocessors.