FPGA Implementation Research Articles

FPGA Acceleration of AES Algorithm for High-Performance Cryptographic Applications

This research paper presents the FPGA implementation of the AES-128 Algorithm as an accelerator tailored for high-performance cryptographic applications. Leveraging the capabilities of the Virtex-7 evaluation kit, the AES algorithm is meticulously coded using Xilinx Vivado software. The results of the implementation reveal a resource-efficient design, utilizing 588 Look-Up Tables (LUTs) and 353 Flip Flops. This implementation showcases the efficacy of FPGA technology, specifically the Virtex-7 device, in achieving a fine balance between algorithmic complexity and resource utilization for cryptographic acceleration. The abstract underscores the significance of this research in advancing the field of hardware-accelerated cryptographic applications, offering a scalable solution with promising resource efficiency on the FPGA platform.

Research on shape-controllable generalized multi-cluster Hamiltonian conservative chaotic flow systems and their FPGA implementation

Research on shape-controllable generalized multi-cluster Hamiltonian conservative chaotic flow systems and their FPGA implementation

AES 128 Bit Optimization: High-Speed and Area-Efficient through Loop Unrolling

This study introduces a high-throughput FPGA implementation of AES-128, prioritizing efficiency for robust security and fast data processing needs. AES-128 is renowned for its security and widespread use in various applications. Employing techniques like loop unrolling and pipelining, the implementation maximizes throughput and customizes AES for FPGA architectures. A novel optimization approach, "new-affine-transformation," reduces resource demands and latency for the Sub-Bytes function. The AES architecture is strategically modified for efficiency, with rearranged functions and streamlined processing. The implementation, in VHDL and utilizing Xilinx Virtex-5 FPGA, achieves remarkable performance: 37.9 Gbps (encryption) and 38.5 Gbps (decryption) throughput at frequencies of 296.789 MHz (encryption) and 300.806 MHz (decryption). Resource utilization is efficient, with 264 (encryption) and 260 (decryption) slice registers and 1044 (encryption) and 1581 (decryption) total slices. Keywords: AES, FPGA, cryptography, encryption, decryption, throughput, plain text, cipher text

Novel Multilevel Current Source Converter With Asymmetric Configuration: Analysis, Comparison, Modulation, and FPGA Implementation

Novel Multilevel Current Source Converter With Asymmetric Configuration: Analysis, Comparison, Modulation, and FPGA Implementation

GEMA: A Genome Exact Mapping Accelerator Based on Learned Indexes.

In this article, we introduce GEMA, a genome exact mapping accelerator based on learned indexes, specifically designed for FPGA implementation. GEMA utilizes a machine learning (ML) algorithm to precisely locate the exact position of read sequences within the original sequence. To enhance the accuracy of the trained ML model, we incorporate data augmentation and data-distribution-aware partitioning techniques. Additionally, we present an efficient yet low-overhead error recovery technique. To map long reads more efficiently, we propose a speculative prefetching approach, which reduces the required memory bandwidth. Furthermore, we suggest an FPGA-based architecture for implementing the proposed mapping accelerator, optimizing the accesses to off-chip memory. Our studies demonstrate that GEMA achieves up to 1.36 × higher speed for short reads compared to the corresponding results reported in recently published exact mapping accelerators. Moreover, GEMA achieves up to ∼22 × faster mapping of long reads compared to the available results for the longest mapped reads using these accelerators.

Design and FPGA implementation of mixed VVC/HEVC CABAC decoding

Design and FPGA implementation of mixed VVC/HEVC CABAC decoding

Bifurcation investigation, phase synchronization and FPGA implementation of a new photosensitive Fitz Hugh Nagumo neuron based meminductor

Abstract This paper focuses on the estimation of the nonlinear encoding and responses of a photosensitive Fitz Hugh Nagumo (FHN) neuron-based-meminductor and provides a relevant analysis of its phase synchronization. In the pattern, a Fitz Hugh–Nagumo neuron connected to a meminductor is activated by a photocell, and a time-varying current source is generated by the presence of external optical signals. This coupling is a benchmark circuit with memory similar to artificial eyes with the ability to capture and encode external signals. It is designed with the aim of studying the dynamics of a neuron with a memory effect highlighted through the meminductor. An appropriate dynamical analysis is provided using standard indicators such as bifurcations to point out thorough transitions and the nature of the electrical neuronal activities. Some couplings between two FHN neurons with meminductor using hybrid synapses composed of passive electronic components are achieved. Relevant tools are used to analyze the stability of the synchronization which gives prominent details on the selection of the appropriate coupling. The energy balance of the external system is evaluated which gives the effort to achieve encoding signals and also proves the feasibility of the proposal in real-time implementation. Simulations are performed on FPGA. The results present a good agreement. In many engineering applications, the detection of optical signals is inescapable as well as the synchronization of its signals for the transmission of the stimuli. These results could be useful for the designer.

FPGA Implementation of Deep Learning Model Utilizing Different Normalization Algorithms for COVID-19 Diagnosis

Normalization is utilized to remove outliers from the dataset and address network bias. In this research, Mean-Variance-Softmax-Rescale (MVSR) and Min-Max normalizations are employed in various combinations for the diagnosis of COVID-19 using a Convolutional Neural Network (CNN)-based Deep Learning (DL) model, aimed at enhancing network accuracy. To accomplish this, the CNN model is developed within the Google Colab environment and trained using a publicly available dataset consisting of chest X-ray images related to COVID-19. The dataset is normalized using different combinations of the MVSR and Min-Max normalization algorithms to compare model accuracy. Each normalized dataset is used for model training, and subsequently, each trained model is integrated into the Kria KV260 Vision AI Starter Kit FPGA for the testing phase. The most accurate results are obtained when both MVSR and Min-Max normalizations are applied simultaneously. This high-performing scenario is re-evaluated with real-time camera and FPGA configuration. During real-time implementations, Min-Max normalization is performed within the Colab environment, while the MVSR normalization algorithm is executed using the Kria KV260 Vision AI Starter FPGA Kit. Experimentally, the highest accuracy is achieved in real-time with the MVSR+Min-Max scenario, reaching 93%. The model's precision, recall, and F1-Score values are determined as 0.91, 0.96, and 0.93, respectively.

Nonlinear coexistence phenomenon and FPGA implementation with the hybrid of memristive–memcapacitive hyperchaotic system

Nonlinear coexistence phenomenon and FPGA implementation with the hybrid of memristive–memcapacitive hyperchaotic system

FPGA Implementation of Direct Torque Control for Surface Mounted Permanent Magnet Synchronous Motor using PID Controller

This paper presents a real time FPGA implementation of a Direct Torque Controller for Surface Mounted Permanent magnet Synchronous Motor (SPM) using PID controller. The Direct Torque algorithm with PID controller is designed and implemented using VHDL.The complete digital controller is divided into three modules. From first module position of flux vector is found based on the flux error and torque error and the sector. The torque error is obtained from PID controller. From second module the switching state of the inverter is found based on the position of the flux vector, whereas third module indicates the complete digital controller. The digital controller algorithm presented in this paper has been implemented on a Xilinx Spartan-3 FPGA board. The inverter keeps the same state till the outputs of the hysteresis controllers change states. This inverter is fed to the SPM to maintain a desired constant speed when the load varies. Experimental results on FPGA implementation of a Direct Torque Controller for SPM using PID controller are provided in this paper for two reference speeds and two load torques.

Dynamics of multicavity hyperchaotic maps with rotational control operation and its applications

To provide more complex and random chaotic maps to applications and algorithms, we propose a boundary coupled modulation (BCM) model. By introducing the rotation-matrix (ROT), the corresponding rotation boundary coupled modulation (RBCM) model are constructed, and a series of hyperchaotic maps are generated with various attractors and numerous fixed points. The shape and size of the multicavity can be adjusted by controlling the parameters. Interestingly, RBCM maps are controlled by changing rotation coefficients (Rot-C, d, e, and θ), which can rotate the attractor of the enhanced BCM at any angle and direction. RBCM maps produce a more uniform topological space, and have multiple pairs of symmetric coexisting attractors. The BCM and RBCM maps exhibit rich dynamical behaviors, high complexity, and strong randomness.To verify the engineering practicability, we apply the BCM and RBCM maps to design pseudo-random number generators (PRNG), and test it with NIST, quadrature amplitude modulation (QAM) system. Finally, the FPGA implementation of the proposed chaotic map verifies.

FPGA-based fast bin-ratio spiking ensemble network for radioisotope identification

In this work, we demonstrate the training, conversion, and implementation flow of an FPGA-based bin-ratio ensemble spiking neural network applied for radioisotope identification. The combination of techniques including learned step quantisation (LSQ) and pruning facilitated the implementation by compressing the network’s parameters down to 30% yet retaining the accuracy of 97.04% with an accuracy loss of less than 1%. Meanwhile, the proposed ensemble network of 20 3-layer spiking neural networks (SNNs), which incorporates 1160 spiking neurons, only needs 334 μs for a single inference with the given clock frequency of 100 MHz. Under such optimisation, this FPGA implementation in an Artix-7 board consumes 157 μJ per inference by estimation.

FPGA Implementation of a Pipelined Kalman Filter for Object Tracking in Two Dimensions

In a location tracking system for a moving object, not only accuracy but also real-time processing are important factors. The Kalman filter, as a recursive function, stands out as one of the prominent algorithms for object tracking. It continuously compares measured data with predicted values based on the system characteristics in real time, and then corrects the error of the predicted values while considering the noise of both system and measured data. This paper focuses on designing a hardware-based Kalman filter for object tracking in two dimensions. Following an analysis of the Kalman filter algorithm, the blocks capable of parallel processing are identified and configured to be processed in parallel, effectively reducing data processing time. The clock speed is enhanced by using the pipeline technique. In addition, the time-sharing technique is applied to increase the utilization of hardware resources and reduce the area. Data was processed at 32-bit floating points to uphold accuracy comparable to software-implemented Kalman filters. The proposed Kalman filter architecture is designed using verilog HDL and then simulated in Synopsys VCS/Verdi. And the accuracy is verified by comparing results with a software-based Kalman filter designed using MATLAB. It was implemented using Zynq ZYNQ-7 ZC702 Programmable logic via Xilnix Vivado, and can operate at 33MHz. It takes a total of 44 clocks, or 1.32 us, to process one data. Therefore, it was confirmed that the designed Kalman filter hardware is suitable for real-time processing.

Co-design based FPGA implementation of an efficient new speech hyperchaotic cryptosystem in the transform domain

In this paper a new encryption system has been designed and implemented for real-time speech transmission to reduce bandwidth requirements, increase security and minimize residual intelligibility. To guarantee robustness and lightweight computation, the developed cryptosystem has been carried out in the wavelet transform domain based on a hyperchaotic model to generate mask and permutation keys. The cryptographic system has been designed using a hardware-software (HW/SW) co-design approach by developing several IP-cores in a relatively short development time. The performances and security evaluation of the system have been validated through simulation results followed by an experimental validation through the implementation of an encrypted speech signal transmission between two low cost Nexys-4 DDR FPGA platforms, operating in real-time for both wired and wireless communications. Compared to similar works, high performances have been obtained in terms of bandwidth efficiency due to the use of DWT, limited area of FPGA resources, low power consumption and high security level with a large keyspace that is sufficient to resist against brute force attacks. The designed system can be a very useful solution for many real-time secure integrated voice communication systems, multiple communication purposes, military, professional or personal high level of conversations security.

Design and FPGA Implementation of 4×4 Vedic Multiplier using Different Architectures

The need of high speed multiplier is increasing as the need of high speed processors are increasing. A Multiplier is one of the key hardware blocks in most of the fast processing systems which is not only a high delay block but also a major source of power dissipation. A conventional processor requires substantially more hardware resources and processing time in the multiplication operation, rather than addition and subtraction. This Project describes about the design of 4-bit, 8-bit and 32-bit Vedic multiplier using ancient Vedic mathematics which helps in delay and power reduction. Simulation is done in Xilinx VIVADO software using VHDL and display on LCD. The results for Vedic multiplier using various architecture and their delay comparison are done. Key Words: FPGA (Artix-7), adders, 4x4 Array Multiplier, Vedic Mathematics

Dynamic research of hidden attractors in discrete memristive neural network with trigonometric functions and FPGA implementation

Dynamic research of hidden attractors in discrete memristive neural network with trigonometric functions and FPGA implementation

Low latency FPGA implementation of NTT for Kyber

This paper presents an FPGA implementation of Number Theoretic Transform (NTT) for the Kyber Post-Quantum Cryptographic (PQC) standard. NTT is the slowest process within Kyber thus a large number of efforts has been conducted to enhance its computational efficiency. Leveraging parallelism and dedicated multipliers, our design achieves state-of-the-art latency, performing NTT/INTT in just 0.4/0.5μs, surpassing existing designs by at least 3.75/3 times. The proposed design is implemented on the cost-effective Artix-7 FPGA.

Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation

In signal processing applications, the multipliers are essential component of arithmetic functional units in many applications, like digital signal processors, image/video processing, Machine Learning, Cryptography and Arithmetic & Logical units (ALU). In recent years, Profuse multipliers are there. In that, Vedic multiplier is one of the high-performance multiplications and it is used to signal/image processing applications. In order to ameliorate the performance of this multiplier further, by proposed a novel multiplier using hybrid compressor. The proposed hybrid compressor-based multiplier is designed and implemented in Field programmable Gate Array (FPGA—spartan 6). The synthesis result shows that the speed of proposed hybrid compressor-based multiplier gets improved as compared to Array multiplier (35.83%), Wallace tree multiplier (34.58%), Vedic Multiplier based on Carry look ahead adder (CLA) (28.49%), Vedic Multiplier based on Ripple carry adder (RCA) (20.65%), Booth Multiplication (21.65%) and Vedic Multiplication based on Han-Carlson Adder (HCA) (20.10%) and Hybrid multiplier using Carry Select Adder (CSELA) (17.81%) and Hybrid Vedic Multiplier (7.15%).

Robust and efficient airplane cockpit video coding leveraging temporal redundancy

AbstractAirplane cockpit screens consist of virtual instruments where characters, numbers, and graphics are overlaid on a black or natural background. Recording the cockpit screen allows one to log vital plane data, as aircraft manufacturers do not offer direct access to raw data. However, traditional video codecs struggle at preserving character readability at the required low bit-rates. We showed in a previous work that large rate-distortion gains can be achieved if the characters are encoded as text rather than as pixels. We now leverage temporal redundancy to both achieve robust character recognition and improve encoding efficiency. A convolutional neural network is trained for character classification over synthetic samples augmented with occlusions to gain robustness against overlapping graphics. Further robustness to background occlusions is brought by a probabilistic framework that error-corrects the output of the convolutional neural network. Next, we propose a predictive text coding technique specifically tailored for text in cockpit videos that achieves competitive performance over commodity lossless methods. Experiments with real cockpit video footage show large rate-distortion gains for the proposed method with respect to three different video compression standards. Notably, the H.264/AVC codec retrofitted with our method outperforms H.265/HEVC-SCC and is competitive with the much more complex H.266/VVC while preserving text and graphics. The entire pipeline described in this work has been implemented at Safran Electronics as an embedded avionics system drawing just 2W of power thanks to a combination of software and FPGA implementation.

HLPerf: Demystifying the Performance of HLS-based Graph Neural Networks with Dataflow Architectures

The development of FPGA-based applications using HLS is fraught with performance pitfalls and large design space exploration times. These issues are exacerbated when the application is complicated and its performance is dependent on the input data set, as is often the case with graph neural network approaches to machine learning. Here, we introduce HLPerf, an open-source, simulation-based performance evaluation framework for dataflow architectures that both supports early exploration of the design space and shortens the performance evaluation cycle. We apply the methodology to GNNHLS, an HLS-based graph neural network benchmark containing 6 commonly used graph neural network models and 4 datasets with distinct topologies and scales. The results show that HLPerf achieves over 10 000 × average simulation acceleration relative to RTL simulation and over 400 × acceleration relative to state-of-the-art cycle-accurate tools at the cost of 7% mean error rate relative to actual FPGA implementation performance. This acceleration positions HLPerf as a viable component in the design cycle.