Fault-tolerant Implementation Research Articles

Fault-Tolerant Code-Switching Protocols for Near-Term Quantum Processors

Topological color codes are widely acknowledged as promising candidates for fault-tolerant quantum computing. Neither a two-dimensional nor a three-dimensional topology, however, can provide a universal gate set {, , }, with the gate missing in the two-dimensional and the gate in the three-dimensional case. These complementary shortcomings of the isolated topologies may be overcome in a combined approach, by switching between a two- and a three-dimensional code while maintaining the logical state. In this work, we construct resource-optimized deterministic and nondeterministic code-switching protocols for two- and three-dimensional distance-three color codes using fault-tolerant quantum circuits based on flag qubits. Deterministic protocols allow for the fault-tolerant implementation of logical gates on an encoded quantum state, while nondeterministic protocols may be used for the fault-tolerant preparation of magic states. Taking the error rates of state-of-the-art trapped-ion quantum processors as a reference, we find a logical failure probability of 3% for deterministic logical gates, which cannot be realized transversally in the respective code. By replacing the three-dimensional distance-three color code in the protocol for magic state preparation with the morphed code introduced in Vasmer and Kubica [PRX Quantum 3, 030319 (2022)], we reduce the logical failure rates by 2 orders of magnitude, thus rendering it a viable method for magic state preparation on near-term quantum processors. Our results demonstrate that code switching enables the fault-tolerant and deterministic implementation of a universal gate set under realistic conditions, and thereby provide a practical avenue to advance universal, fault-tolerant quantum computing and enable quantum algorithms on first, error-corrected logical qubits. Published by the American Physical Society 2024

Enhancing fault tolerance: dual Q-learning with dynamic scheduling

<span>Cloud computing has revolutionized IT delivery by offering scalable on-demand internet services encompassing software, platforms, and infrastructure. However, cloud services face significant performance challenges due to their susceptibility to failures given their vast operational scale. Implementing fault tolerance in dynamic cloud services is a key challenge, with complex configurations and dependencies complicating deployment. This paper introduces an innovative approach that combines double deep Q-learning (DDQL) with a dynamic fault-tolerant real-time scheduling algorithm (DFTRTSA) to enhance fault tolerance in real-time systems. DDQL, an extension of deep Q-learning, optimizes the fault-tolerance decision-making process. The algorithm adjusts scheduling strategies dynamically based on system conditions and errors. The fusion of DDQL and DFTRTSA aims to create a resilient and adaptive fault-tolerant mechanism, ensuring uninterrupted operation while meeting real-time requirements. This adaptive approach efficiently manages resources, meets deadlines, and gracefully handles errors, as demonstrated through experiments. Our DDQL-DFTRTSA method outperforms conventional fault-tolerant mechanisms in defect tolerance, energy efficiency, downtime reduction, and system dependability. It proves to be an ideal solution for real-time systems in dynamic and unpredictable environments.</span>

Probabilistic state synthesis based on optimal convex approximation

When preparing a pure state with a quantum circuit, there is an unavoidable approximation error due to the compilation error in fault-tolerant implementation. A recently proposed approach called probabilistic state synthesis, where the circuit is probabilistically sampled, is able to reduce the approximation error compared to conventional deterministic synthesis. In this paper, we demonstrate that the optimal probabilistic synthesis quadratically reduces the approximation error. Moreover, we show that a deterministic synthesis algorithm can be efficiently converted into a probabilistic one that achieves this quadratic error reduction. We also numerically demonstrate how this conversion reduces the T-count and analytically prove that this conversion halves an information-theoretic lower bound on the circuit size. In order to derive these results, we prove general theorems about the optimal convex approximation of a quantum state. Furthermore, we demonstrate that this theorem can be used to analyze an entanglement measure.

Partial Network Partitioning

We present an extensive study focused on partial network partitioning. Partial network partitions disrupt the communication between some but not all nodes in a cluster. First, we conduct a comprehensive study of system failures caused by this fault in 13 popular systems. Our study reveals that the studied failures are catastrophic (e.g., lead to data loss), easily manifest, and are mainly due to design flaws. Our analysis identifies vulnerabilities in core systems mechanisms including scheduling, membership management, and ZooKeeper-based configuration management. Second, we dissect the design of nine popular systems and identify four principled approaches for tolerating partial partitions. Unfortunately, our analysis shows that implemented fault tolerance techniques are inadequate for modern systems; they either patch a particular mechanism or lead to a complete cluster shutdown, even when alternative network paths exist. Finally, our findings motivate us to build Nifty, a transparent communication layer that masks partial network partitions. Nifty builds an overlay between nodes to detour packets around partial partitions. Nifty provides an approach for applications to optimize their operation during a partial partition. We demonstrate the benefit of this approach through integrating Nifty with VoltDB, HDFS, and Kafka.

Partitioning qubits in hypergraph product codes to implement logical gates

The promise of high-rate low-density parity check (LDPC) codes to substantially reduce the overhead of fault-tolerant quantum computation depends on constructing efficient, fault-tolerant implementations of logical gates on such codes. Transversal gates are the simplest type of fault-tolerant gate, but the potential of transversal gates on LDPC codes has hitherto been largely neglected. We investigate the transversal gates that can be implemented in hypergraph product codes, a class of LDPC codes. Our analysis is aided by the construction of a symplectic canonical basis for the logical operators of hypergraph product codes, a result that may be of independent interest. We show that in these codes transversal gates can implement Hadamard (up to logical SWAP gates) and control-Z on all logical qubits. Moreover, we show that sequences of transversal operations, interleaved with error correction, allow implementation of entangling gates between arbitrary pairs of logical qubits in the same code block. We thereby demonstrate that transversal gates can be used as the basis for universal quantum computing on LDPC codes, when supplemented with state injection.

Emergent ferromagnetism with superconductivity in Fe(Te,Se) van der Waals Josephson junctions

Ferromagnetism and superconductivity are two key ingredients for topological superconductors, which can serve as building blocks of fault-tolerant quantum computers. Adversely, ferromagnetism and superconductivity are typically also two hostile orderings competing to align spins in different configurations, and thus making the material design and experimental implementation extremely challenging. A single material platform with concurrent ferromagnetism and superconductivity is actively pursued. In this paper, we fabricate van der Waals Josephson junctions made with iron-based superconductor Fe(Te,Se), and report the global device-level transport signatures of interfacial ferromagnetism emerging with superconducting states for the first time. Magnetic hysteresis in the junction resistance is observed only below the superconducting critical temperature, suggesting an inherent correlation between ferromagnetic and superconducting order parameters. The 0-π phase mixing in the Fraunhofer patterns pinpoints the ferromagnetism on the junction interface. More importantly, a stochastic field-free superconducting diode effect was observed in Josephson junction devices, with a significant diode efficiency up to 10%, which unambiguously confirms the spontaneous time-reversal symmetry breaking. Our work demonstrates a new way to search for topological superconductivity in iron-based superconductors for future high Tc fault-tolerant qubit implementations from a device perspective.

Self-stabilizing Byzantine fault-tolerant repeated reliable broadcast

We study a well-known communication abstraction called Byzantine Reliable Broadcast (BRB). This abstraction is central in the design and implementation of fault-tolerant distributed systems, as many fault-tolerant distributed applications require communication with provable guarantees on message deliveries. Our study focuses on fault-tolerant implementations for message-passing systems that are prone to process-failures, such as crashes and malicious behavior.At PODC 1983, Bracha and Toueg, in short, BT, solved the BRB problem. BT has optimal resilience since it can deal with t<n/3 Byzantine processes, where n is the number of processes. The present work aims to design an even more robust solution than BT by expanding its fault-model with self-stabilization, a vigorous notion of fault-tolerance. In addition to tolerating Byzantine and communication failures, self-stabilizing systems can recover after the occurrence of arbitrary transient-faults. These transient faults allow the model to represent temporary deviations from the assumptions on which the system was originally designed to operate (provided that the algorithm code remains intact).We propose, to the best of our knowledge, the first self-stabilizing Byzantine fault-tolerant (BFT) solution for repeated BRB in signature-free message-passing systems (that follows BT's problem specifications). Our contribution includes a self-stabilizing variation on BT that solves a single-instance BRB for asynchronous systems. We also consider the problem of recycling instances of single-instance BRB. Our self-stabilizing BFT recycling for time-free systems facilitates the concurrent handling of a predefined number of BRB invocations and, in this way, can serve as the basis for self-stabilizing BFT consensus.

Quantum Bilinear Interpolation Algorithms Based on Geometric Centers

Bilinear interpolation is widely used in classical signal and image processing. Quantum algorithms have been designed for efficiently realizing bilinear interpolation. However, these quantum algorithms have limitations in circuit width and garbage outputs, which block the quantum algorithms applied to noisy intermediate-scale quantum devices. In addition, the existing quantum bilinear interpolation algorithms cannot keep the consistency between the geometric centers of the original and target images. To save the above questions, we propose quantum bilinear interpolation algorithms based on geometric centers using fault-tolerant implementations of quantum arithmetic operators. Proposed algorithms include the scaling-up and scaling-down for signals (grayscale images) and signals with three channels (color images). Simulation results demonstrate that the proposed bilinear interpolation algorithms obtain the same results as their classical counterparts with an exponential speedup. Performance analysis reveals that the proposed bilinear interpolation algorithms keep the consistency of geometric centers and significantly reduce circuit width and garbage outputs compared to the existing works.

DESCO: Decomposition-Based Co-Design to Improve Fault Tolerance of Security-Critical Tasks in Cyber Physical Systems

Confidentiality-Specific Faults (CSFs) will put cyber physical systems in threat, since they can result in corrupted information or even retrieve the cryptographic key of security-critical applications. In this paper, we will look into fault-tolerant co-design optimization for security-critical cyber physical systems with resource constraints, such that the encryption/decryption of confidential messages are protected against transient CSF faults. We consider imperfect fault detection mechanisms to identify transient CSF faults happened on confidentiality protection, and utilize duplication code to recovery from such faults. We utilize FPGA to accelerate the executions of security tasks, reducing the overheads of fault-tolerant implementations. The system-level design problem is formulated as a two-objective optimization problem, i.e., to minimize the average reliability degradation of the fault tolerant assignments and to minimize the balanced degree of the reliability degradation, subject to available FPGA budget, deadline, and application execution constraints. Since finding Pareto-optimal solutions is NP-hard, we propose an improved multi-objective optimization algorithm, called DEcomposition-based Security Co-design Optimization (DESCO), to search for Pareto-optimal solutions of fault-tolerant assignments. Experimental results demonstrate that DESCO is effective and can outperform other candidates, proving that our approach is promising in dealing with system-level optimization problem for security-critical applications on cyber physical systems.

Resilient Embedded Systems Designs via on the Fly Generation of Adaptive Degenerate Components Using Machine Learning

Software defined radio (SDR) provides significant advantages over traditional analog radio systems and are becoming increasingly relied on for “mission critical” applications. This along with risk of trojans, single-event upsets and human error creates the necessity for fault tolerant systems. Redundancy has been traditionally used to implement fault tolerance but incurs a substantial area overhead which is undesirable in most applications. Advancements in field-programmable gate array and system on a chip technologies have made implementing machine learning (ML) algorithms within embedded systems feasible. In this paper we explore the use of ML to implement fault tolerance in an SDR. Our approach, which we call adaptive component-level degeneracy (ACD), uses a ML model to learn the functionality of an SDR component. Once trained, the model can detect when the component is compromised and mitigate the issue with its own output. We demonstrate the ability of our model to learn multiple simulated SDR components. We compare the one-dimensional convolutional neural network and bidirectional recurrent neural network architectures at modeling time series components. We also implement ACD within a real-time SDR system using GNU Radio Companion. The results show great potential for the utilization of ML techniques for improving embedded system reliability.

Fault-tolerant quantum algorithm for dual-threshold image segmentation

The intrinsic high parallelism and entanglement characteristics of quantum computing have made quantum image processing techniques a focus of great interest. One of the most widely used techniques in image processing is segmentation, which in one of their most basic forms can be carried out using thresholding algorithms. In this paper, a fault-tolerant quantum dual-threshold algorithm has been proposed. This algorithm has been built using only Clifford+T gates for compatibility with error detection and correction codes. Because fault-tolerant implementation of T gates has a much higher cost than other quantum gates, our focus has been on reducing the number of these gates. This has allowed adding noise tolerance, computational cost reduction, and fault tolerance to the state-of-the-art dual-threshold segmentation circuits. Since the dual-threshold image segmentation involves the comparison operation, as part of this work we have implemented two full comparator circuits. These circuits optimize the metrics T-count and T-depth with respect to the best circuit comparators currently available in the literature.

Optical demonstration of quantum fault-tolerant threshold

A major challenge in practical quantum computation is the ineludible errors caused by the interaction of quantum systems with their environment. Fault-tolerant schemes, in which logical qubits are encoded by several physical qubits, enable to the output of a higher probability of correct logical qubits under the presence of errors. However, strict requirements to encode qubits and operators render the implementation of a full fault-tolerant computation challenging even for the achievable noisy intermediate-scale quantum technology. Especially the threshold for fault-tolerant computation still lacks experimental verification. Here, based on an all-optical setup, we experimentally demonstrate the existence of the threshold for the fault-tolerant protocol. Four physical qubits are represented as the spatial modes of two entangled photons, which are used to encode two logical qubits. The experimental results clearly show that when the error rate is below the threshold, the probability of correct output in the circuit, formed with fault-tolerant gates, is higher than that in the corresponding non-encoded circuit. In contrast, when the error rate is above the threshold, no advantage is observed in the fault-tolerant implementation. The developed high-accuracy optical system may provide a reliable platform to investigate error propagation in more complex circuits with fault-tolerant gates.

A Fuzzy Approach to Fault Tolerant in Cloud using the Checkpoint Migration Technique

Fault tolerance is one of the most important issues in cloud computing to provide reliable services. It is difficult to implement due to dynamic service infrastructures, complex configurations and different dependencies. Extensive research efforts have been made to implement fault tolerance in the cloud environment. Many studies focus only on fault detection and do not consider fault tolerance. For this reason, in this paper, in addition to recognizing the nature of the fault, a fuzzy logic-based approach is proposed to provide an appropriate response and increase the fault tolerance in the cloud environment. Checkpoint-based migration technique is used to increase fault tolerance. Using a checkpoint during migration can reduce time and processing costs and balance the load between virtual machines in the event of a fault. The simulation is performed according to the data center of Vietnam Telecommunications Company (VDC). The results of the proposed method in a period of 60 minutes show 98.03% fault detection accuracy, which is 4.5% and 4.1% superior to FLPT and PLBFT algorithms, respectively.

Towards highly-concurrent leaderless state machine replication for distributed systems

State Machine Replication (SMR) is a fault-tolerant service implementation technique used by many modern Internet services. A single leader is used in classic SMR to order all state machine commands. Due to the scalability and availability difficulties of the single-leader approach, recent protocols propose a leaderless technique in which each replica can make progress using a quorum of replicas. While the leaderless strategy is gaining traction, it necessitates all replicas serializing a directed graph with the precise specification, which usually results in sequential execution. When employing popular multicore servers, sequential execution also limits performance. We propose an efficient scheduler termed CCDG (Concurrent Construct Dependency Graphs) for Leaderless State Machine Replication to increase parallelization to fully exploit multicore capabilities and boost performance. To reach higher parallelism levels and make better use of multicore technology, CCDG provides concurrent construction of dependency graphs with guaranteed linearizability. Meanwhile, CCDG improves tail latency by eliminating unnecessary dependencies to reduce scheduling wait times. Our extensive experimental study shows that CCDG achieves up to 3.3 times the throughput in workloads with conflicting commands compared to EPaxos, one of the most popular leaderless SMR consensus protocols.

Load Balancing Using Dynamic Ant Colony System Based Fault Tolerance in Grid Computing

Load balancing is often disregarded when implementing fault tolerance capability in grid computing. Effective load balancing ensures that a fair amount of load is assigned to each resource, based on its fitness rather than assigning a majority of tasks to the most fitting resources. Proper load balancing in a fault tolerance system would also reduce the bottleneck at the most fit resources and increase utilization of other resources. This paper presents a fault tolerance algorithm based on ant colony system, that considers load balancing based on resource fitness with resubmission and checkpoint technique, to improve fault tolerance capability in grid computing. Experimental results indicated that the proposed fault tolerance algorithm has better execution time, throughput, makespan, latency, load balancing and success rate.

Asynchronous reconfiguration with Byzantine failures

Replicated services are inherently vulnerable to failures and security breaches. In a long-running system, it is, therefore, indispensable to maintain a reconfiguration mechanism that would replace faulty replicas with correct ones. An important challenge is to enable reconfiguration without affecting the availability and consistency of the replicated data: the clients should be able to get correct service even when the set of service replicas is being updated. In this paper, we address the problem of reconfiguration in the presence of Byzantine failures: faulty replicas or clients may arbitrarily deviate from their expected behavior. We describe a generic technique for building asynchronous and Byzantine fault-tolerant reconfigurable objects: clients can manipulate the object data and issue reconfiguration calls without reaching consensus on the current configuration. With the help of forward-secure digital signatures, our solution makes sure that superseded and possibly compromised configurations are harmless, that slow clients cannot be fooled into reading stale data, and that Byzantine clients cannot cause a denial of service by flooding the system with reconfiguration requests. Our approach is modular and based on dynamic Byzantine lattice agreement abstraction, and we discuss how to extend it to enable Byzantine fault-tolerant implementations of a large class of reconfigurable replicated services.

Fast Real-Time RDFT- and GDFT-Based Direct Fault Diagnosis of Induction Motor Drive

This paper presents the theoretical analysis and experimental verification of a direct fault harmonic identification approach in a converter-fed electric drive for automated diagnosis purposes. On the basis of the analytical model of the proposed real-time direct fault diagnosis, the fault-related harmonic component is calculated using recursive DFT (RDFT) and Goertzel DFT (GDFT), applied instead of the full spectrum calculations required in the most popular FFT algorithm. The simulation model of an inverter sensorlessly controlled induction motor drive is linked with the induction machine rotor fault model for testing the sensitivity of the GDFT- and RDFT-based fault diagnosis to state variable estimation errors. According to the presented simulation results, the accuracy of the direct identification of a fault-related harmonic is sensitive to the quality of fault harmonic frequency estimation. The sensitivity analysis with respect to RDFT and GDFT algorithms is included. Based on the experimental setup with a sensorlessly controlled induction motor drive with the investigated rotor fault, fault diagnosis algorithms were implemented in the microprocessor by integration with the control system in one microcontroller and experimentally verified. The RDFT and GDFT approach has shown accurate and fast direct automated fault identification at a significantly decreased number of arithmetical operations in the microcontroller, which is convenient for the frequency-domain fault diagnosis in electric drives and supports fault-tolerant control system implementation.

Universal hardware-efficient topological measurement-based quantum computation via color-code-based cluster states

Topological measurement-based quantum computation (MBQC) enables one to carry out universal fault-tolerant quantum computation via single-qubit Pauli measurements with a family of large entangled states called cluster states as resources. Raussendorf's three-dimensional cluster states (RTCSs) based on the surface codes are mainly considered for topological MBQC. In such schemes, however, the fault-tolerant implementation of the logical Hadamard, phase ($Z^{1/2}$), and $T$ ($Z^{1/4}$) gates which are essential for building up arbitrary logical gates has not been achieved to date without using state distillation, while the controlled-NOT (CNOT) gate does not require it, to best of our knowledge. State distillation generally consumes many ancillary logical qubits, thus it is a severe obstacle against practical quantum computing. To solve this problem, we suggest an MBQC scheme via a family of cluster states called color-code-based cluster states (CCCSs) based on the two-dimensional color codes instead of the surface codes. We define logical qubits, construct elementary logical gates, and describe error correction schemes. We show that all the logical Clifford gates including the CNOT, Hadamard, and phase gates can be implemented fault-tolerantly without state distillation, although the fault-tolerant $T$ gate still requires it. We further prove that the minimal number of physical qubits per logical qubit in a CCCS is at most approximately 1.8 times smaller than the case of an RTCS. We lastly show that the error threshold of MBQC via CCCSs for logical-$Z$ errors is 2.7-2.8%, which is comparable to the value for RTCSs, assuming a simple error model where physical qubits have $X$-measurement or $Z$ errors independently with the same probability.

The Optimization and Application of 3-Bit Hermitian Gates and Multiple Control Toffoli Gates

The well-known 3-bit Hermitian gate (a Toffoli gate) has been implemented using Clifford + T circuits. Compared with the Peres gate, its implementation circuit requires more controlled-NOT (CNOT) gates. However, the Peres gate is not Hermitian. This paper reports four 3-bit Hermitian gates named LI gates. Whose realized circuits have the same T-count, T-depth, and CNOT-count as the Peres gate. Furthermore, two decomposition methods of a multiple control Toffoli (MCT) gate are proposed for different primary optimization goals. Then, we design the equality, less-than, and full comparators with the minimum circuit width using proposed Hermitian gates and optimized MCT gates. A fault-tolerant circuit is required for robust quantum computing. Clifford+T circuits are accepted solutions for fault-tolerant implementation. Considering T-count, T-depth, CNOT-count, and circuit width as the primary optimization goals, we design the optimized Clifford + T circuits of three comparators using LI gates and optimized MCT gates. Comparison and analysis show that the proposed comparators have better overall performances for T-count, T-depth, CNOT-count, and circuit width than the best-known comparators without quantum measurements.

A polynomial time and space heuristic algorithm for T-count

An important part of reaping computational advantage from a quantum computer is to reduce the quantum resources needed to implement a desired quantum algorithm. Quantum algorithms that are too large to be practical on noisy intermediate scale quantum devices will require fault-tolerant error correction. This work focuses on reducing the physical cost of implementing quantum algorithms when using the state-of-the-art fault-tolerant quantum error correcting codes, in particular, those for which implementing the T gate consumes vastly more resources than the other gates in the gate set. More specifically, in this paper we consider the group of unitaries that can be exactly implemented by a quantum circuit consisting of the Clifford + T gate set. The Clifford + T gate set is a universal gate set and in this group, using state-of-the-art surface codes, the T gate is by far the most expensive component to implement fault-tolerantly. So it is important to minimize the number of T gates necessary for a fault-tolerant implementation. Our primary interest is to compute a circuit for a given n-qubit unitary U, using the minimum possible number of T gates (called the T-count of unitary U). We consider the problem COUNT-T, the optimization version of which aims to find the T-count of U. In its decision version the goal is to decide if the T-count is at most some positive integer m. Given an oracle for COUNT-T, we can compute a T-count-optimal circuit in time polynomial in the T-count and dimension of U. We give a provable classical algorithm that solves COUNT-T (decision) in time and space , where N = 2 n and c ⩾ 2. This gives a space-time trade-off for solving this problem with variants of meet-in-the-middle techniques. We also introduce an asymptotically faster multiplication method that shaves a factor of N 0.7457 off of the overall complexity. Lastly, beyond our improvements to the rigorous algorithm, we give a heuristic algorithm that outputs a T-count-optimal circuit and has space and time complexity poly(m, N), under some assumptions. In our heuristic algorithm we developed a novel way of pruning the search space. While our heuristic method still scales exponentially with the number of qubits (though with a lower exponent), there is a large improvement by going from exponential to polynomial scaling with m. We implemented our heuristic algorithm with up to 4 qubit unitaries and obtained a significant improvement in time. For all benchmark and random unitaries we studied, the T-count returned by our algorithm is at most the T-count of their circuits shown in previous papers.