Dataflow Implementation Research Articles

STIFT: A Spatio-Temporal Integrated Folding Tree for Efficient Reductions in Flexible DNN Accelerators

Increasing deployment of Deep Neural Networks (DNNs) recently fueled interest in the development of specific accelerator architectures capable of meeting their stringent performance and energy consumption requirements. DNN accelerators can be organized around three separate NoCs, namely distribution, multiplier, and reduction networks (or DN, MN, and RN, respectively) between the global buffer(s) and the compute units (multipliers/adders). Among them, the RN, used to generate and reduce the partial sums produced during DNN processing, is a first-order driver of the area and energy efficiency of the accelerator. RNs can be orchestrated to exploit a Temporal, Spatial or Spatio-Temporal reduction dataflow. Among these, Spatio-Temporal reduction is the one that has shown superior performance. However, as we demonstrate in this work, a state-of-the-art implementation of the Spatio-Temporal reduction dataflow, based on the addition of Accumulators (Ac) to the RN (i.e., RN+Ac strategy), can result into significant area and energy expenses. To cope with this important issue, we propose STIFT (that stands forSpatio-Temporal Integrated Folding Tree) that implements the Spatio-Temporal reduction dataflow entirely on the RN hardware substrate (i.e., without the need for the extra accumulators). STIFT results into significant area and power savings regarding the more complex RN+Ac strategy, at the same time its performance advantage is preserved.

Management of Climate Resilience: Exploring the Potential of Digital Twin Technology, 3D City Modelling, and Early Warning Systems.

Cities, and in particular those in coastal low-lying areas, are becoming increasingly susceptible to climate change, the impact of which is worsened by the tendency for population concentration in these areas. Therefore, comprehensive early warning systems are necessary to minimize harm from extreme climate events on communities. Ideally, such a system would allow all stakeholders to acquire accurate up-to-date information and respond effectively. This paper presents a systematic review that highlights the significance, potential, and future directions of 3D city modelling, early warning systems, and digital twins in the creation of technology for building climate resilience through the effective management of smart cities. In total, 68 papers were identified through the PRISMA approach. A total of 37 case studies were included, among which (n = 10) define the framework for a digital twin technology, (n = 14) involve the design of 3D virtual city models, and (n = 13) entail the generation of early warning alerts using the real-time sensor data. This review concludes that the bidirectional flow of data between a digital model and the real physical environment is an emerging concept for enhancing climate resilience. However, the research is primarily in the phase of theoretical concepts and discussion, and numerous research gaps remain regarding the implementation and use of a bidirectional data flow in a true digital twin. Nonetheless, ongoing innovative research projects are exploring the potential of digital twin technology to address the challenges faced by communities in vulnerable areas, which will hopefully lead to practical solutions for enhancing climate resilience in the near future.

Fast and accurate variable batch size convolution neural network training on large scale distributed systems

AbstractLarge‐scale distributed convolution neural network (CNN) training brings two performance challenges: model performance and system performance. Large batch size usually leads to model test accuracy loss, which counteracts the benefits of parallel SGD. The existing solutions require massive hyperparameter hand‐tuning. To overcome this difficult, we analyze the training process and find that earlier training stages are more sensitive to batch size. Accordingly, we assert that different stages should use different batch size, and propose a variable batch size strategy. In order to remain high test accuracy under larger batch size cases, we design an auto‐tuning engine for automatic parameter tuning in the proposed variable batch size strategy. Furthermore, we develop a dataflow implementation approach to achieve the high‐throughput CNN training on supercomputer system. Our approach has achieved high generalization performance on SOAT CNN networks. For the ShuffleNet, ResNet‐50, and ResNet‐101 training with ImageNet‐1K dataset, we scale the batch size to 120 K without accuracy loss and to 128 K with only a slight loss. And the dataflow implementation approach achieves 93.5% scaling efficiency on 1024 GPUs compared with the state‐of‐the‐art.

Aplikasi E-Transaksi dan Pelaporan Kegiatan di Galeri Investasi Politeknik Piksi Ganesha

An investment gallery in a university becomes a teaching medium, especially for students in studying investment in the capital market. Transactions and processing of investor data at the Piksi Ganesha Polytechnic Investment Gallery, Bandung are currently still done manually and not yet computerized so that the recapitulation of investment activities, search for investor data, and transaction reporting and investor activity data is not yet effective and efficient, so this study aims to design transaction applications. and web-based Investor activity data reporting at the Piksi Ganesha Polytechnic Investment Gallery Bandung. The research method used is descriptive qualitative with data collection techniques through observation, interviews, documentation and literature study. The software development method uses the waterfall. Information system design using data flow diagrams and implementation with PHP programming language with bootstrap framework and My SQL database. It is hoped that the Investment Gallery application can make it easier for investors to get information and facilitate transactions and for users to make it easier to manage activities and report investment activities transactions.

Towards hybrid supercomputing architectures

In light of recent work on combining control-flow and dataflow architectures on the same chip die, a new architecture based on an asymmetric multicore processor is proposed. The control-flow architectures are described as a most commonly used computer architecture today. Both multicore and manycore architectures are explained, as they are based on the same principles. A dataflow computing model assumes that data input flows through hardware as either a software or hardware dataflow implementation. In software dataflow, processors based on the control-flow paradigm process tasks based on their availability from the same queue (if there are any). In hardware dataflow architectures, the hardware is configured for a particular algorithm, and data input is streamed into the hardware, and the output is streamed back to the multicore processor for further processing. Hardware dataflow architectures are usually implemented with FPGAs. Hybrid architectures employ asymmetric multicore and manycore computer architectures that are based on the control-flow and hardware dataflow architecture, all combined on the same chip die. Advantages include faster processing time, lower power consumption (and heating), and less space needed for the hardware.

Implementation of Data Flow, Predictive Model, and Data Visualization in Corbion Process Analysis System

Corbion Group Netherlands B.V. is a company specialized in food ingredients such as lactic acid which involves fermentation process. Thus, a system was created to monitor on real-time fermentation process in order to gain insight and control of the process. This system is called Corbion Process Analysis System, or CorPAS. CorPAS covers many projects in Corbion, and in general, it extracts data from flat files, then transforms and loads the data into Power BI for data visualization. The data extraction still needs to be manually done by the users by opening the databases and copy all the data into flat files. CorPAS 2.0. was initiated to improve the previous system and add a new feature. Automated data extraction was successfully implemented with data transformation and visualization, alongside with implementation of a new feature, such as data science predictive modeling. The solution was built with R language and data visualization tool such as Power BI.

Exploring mental models of the right to informational self-determination of office workers in Germany

AbstractApplied privacy research has so far focused mainly on consumer relations in private life. Privacy in the context of employment relationships is less well studied, although it is subject to the same legal privacy framework in Europe. The European General Data Protection Regulation (GDPR) has strengthened employees’ right to privacy by obliging that employers provide transparency and intervention mechanisms. For such mechanisms to be effective, employees must have a sound understanding of their functions and value. We explored possible boundaries by conducting a semi-structured interview study with 27 office workers in Germany and elicited mental models of the right to informational self-determination, which is the European proxy for the right to privacy. We provide insights into (1) perceptions of different categories of data, (2) familiarity with the legal framework regarding expectations for privacy controls, and (3) awareness of data processing, data flow, safeguards, and threat models. We found that legal terms often used in privacy policies used to describe categories of data are misleading. We further identified three groups of mental models that differ in their privacy control requirements and willingness to accept restrictions on their privacy rights. We also found ignorance about actual data flow, processing, and safeguard implementation. Participants’ mindsets were shaped by their faith in organizational and technical measures to protect privacy. Employers and developers may benefit from our contributions by understanding the types of privacy controls desired by office workers and the challenges to be considered when conceptualizing and designing usable privacy protections in the workplace.

Fast Realization of 3-D Space-Time Correlation Sea Clutter of Large-Scale Sea Scene Based on FPGA: From EM Model to Statistical Model

Memoryless nonlinear transform (MNLT) method was widely used in the statistical model for sea clutter simulations. When the radar scattering data sets were obtained, we can simulate large scene and long-time varying 3-D sea surface scattering using expended power spectral quickly and accurately. Compared with the personal computer platform, field-programmable gate array (FPGA) has the unique merit of energy efficiency, high performance and adaptability. In this article, we proposed a novel architecture for implementing the 3-D MNLT algorithm on FPGA using high-level synthesis. As the simulation size increases, the demand for storage resources will also increase rapidly, and the on-chip memory resource will be limited on FPGA. Aiming at these problems, we divided the 3-D space-time simulation into a 2-D spatial simulation and a 3-D temporal simulation, so that we can make full use of the off-chip memory. Our design employs multiple on-chip buffer structures to decrease the transfer time of internal and external data on the FPGA. We also design a dataflow inverse fast Fourier transform processing engine (PE). The dataflow implementation overlapped butterfly operation, increasing concurrency and the overall throughput of this PE. Experimental results show that we can obtain the same accuracy and higher efficiency on a Xilinx Zynq XC7Z100 SoC platform.

Classification of Farmer’s Eligibility as Recipients of Subsidized Fertilizer Assistance with C4.5 Algorithm

Farmers are the main actors in agricultural development, have a major contribution in realizing Indonesia’s agricultural vision. To support the realization of agricultural production and productivity targets, the government’s supports is by issuing policies to provide subsidized fertilizer assistance. The criteria for farmers who are eligible to receive subsidized fertilizer assistance are having land less than 1.9 hectares, have been members of farmer groups, and having work as a farmer or a private employee. Data collection was carried out using the method of observation and interviews with farmer groups in Gunung Kidul. Data classification is done by applying the C4.5 algorithm to 300 data of prospective farmers receiving subsidized fertilizer assistance. Application development includes interface design, making data flow diagrams, implementation and testing. From the research that has been done by applying the C4.5 Algorithm for farmer data, there are 300 data with 113 training data. Produce a data classification of farmers who are eligible to receive assistance at 95,58% accurate and targeted to the needs of farmers. This means that the C4.5 algorithm can be used as a classification for determining the eligibility of farmers to receive subsidized fertilizer.

Megaphone

We design and implement Megaphone, a data migration mechanism for stateful distributed dataflow engines with latency objectives. When compared to existing migration mechanisms, Megaphone has the following differentiating characteristics: (i) migrations can be subdivided to a configurable granularity to avoid latency spikes, and (ii) migrations can be prepared ahead of time to avoid runtime coordination. Megaphone is implemented as a library on an unmodified timely dataflow implementation, and provides an operator interface compatible with its existing APIs. We evaluate Megaphone on established benchmarks with varying amounts of state and observe that compared to naïve approaches Megaphone reduces service latencies during reconfiguration by orders of magnitude without significantly increasing steady-state overhead.

Optimizing data-flow implementations for inter-organizational processes

Inter-organizational business processes can be designed top-down: starting from a global process model, where each activity and gateway is assigned to one of the participating organizations, local processes (or views/stubs for refinement) are generated for each organization. The resulting inter-organizational process is executed by the local processes in a fully distributed manner. Implementing the data-flow in such a scenario is highly complex, both because of the combinatorial explosion of possible solutions and because of conflicting goals for implementing the data-flow. We present a flexible, heuristic algorithm for implementing the data-flow for inter-organizational processes according to various user preferences, which significantly improves over the base-line approaches proposed so far. The approach is fully implemented and a comprehensive, multi-dimensional evaluation is provided.

RIPL

Specialized FPGA implementations can deliver higher performance and greater power efficiency than embedded CPU or GPU implementations for real-time image processing. Programming challenges limit their wider use, because the implementation of FPGA architectures at the register transfer level is time consuming and error prone. Existing software languages supported by high-level synthesis (HLS), although providing a productivity improvement, are too general purpose to generate efficient hardware without the use of hardware-specific code optimizations. Such optimizations leak hardware details into the abstractions that software languages are there to provide, and they require knowledge of FPGAs to generate efficient hardware, such as by using language pragmas to partition data structures across memory blocks. This article presents a thorough account of the Rathlin image processing language (RIPL), a high-level image processing domain-specific language for FPGAs. We motivate its design, based on higher-order algorithmic skeletons, with requirements from the image processing domain. RIPL’s skeletons suffice to elegantly describe image processing stencils, as well as recursive algorithms with nonlocal random access patterns. At its core, RIPL employs a dataflow intermediate representation. We give a formal account of the compilation scheme from RIPL skeletons to static and cyclostatic dataflow models to describe their data rates and static scheduling on FPGAs. RIPL compares favorably to the Vivado HLS OpenCV library and C++ compiled with Vivado HLS. RIPL achieves between 54 and 191 frames per second (FPS) at 100MHz for four synthetic benchmarks, faster than HLS OpenCV in three cases. Two real-world algorithms are implemented in RIPL: visual saliency and mean shift segmentation. For the visual saliency algorithm, RIPL achieves 71 FPS compared to optimized C++ at 28 FPS. RIPL is also concise, being 5x shorter than C++ and 111x shorter than an equivalent direct dataflow implementation. For mean shift segmentation, RIPL achieves 7 FPS compared to optimized C++ on 64 CPU cores at 1.1, and RIPL is 10x shorter than the direct dataflow FPGA implementation.

StreamDrive: a Dynamic Dataflow Framework for Clustered Embedded Architectures

In this paper, we present StreamDrive, a dynamic dataflow framework for programming clustered embedded multicore architectures. StreamDrive simplifies development of dynamic dataflow applications starting from sequential reference C code and allows seamless handling of heterogeneous and application-specific processing elements by applications. We address issues of efficient implementation of the dynamic dataflow runtime system in the context of constrained embedded environments, which have not been sufficiently addressed by previous research. We conducted a detailed performance evaluation of the StreamDrive implementation on our Application Specific MultiProcessor (ASMP) cluster using the Oriented FAST and Rotated BRIEF (ORB) algorithm typical of image processing domain. We have used the proposed incremental development flow for the transformation of the ORB original reference C code into an optimized dynamic dataflow implementation. Our implementation has less than 10% parallelization overhead, near-linear speedup when the number of processors increases from 1 to 8, and achieves the performance of 15 VGA frames per second with a small cluster configuration of 4 processing elements and 64KB of shared memory, and of 30 VGA frames per second with 8 processors and 128KB of shared memory.

Algorithm for Identification of Infinite Clusters Based on Minimal Finite Automaton

We propose a finite automaton based algorithm for identification of infinite clusters in a 2D rectangular lattice with L=X×Y cells. The algorithm counts infinite clusters and finds one path per infinite cluster in a single pass of the finite automaton. The finite automaton is minimal according to the number of states among all the automata that perform such task. The correctness and efficiency of the algorithm are demonstrated on a planar percolation problem. The algorithm has a computational complexity of O(L) and could be appropriate for efficient data flow implementation.

A Data-Flow Soft-Core Processor for Accelerating Scientific Calculation on FPGAs

We present a new type of soft-core processor called the “Data-Flow Soft-Core” that can be implemented through FPGA technology with adequate interconnect resources. This processor provides data processing based on data-flow instructions rather than control flow instructions. As a result, during an execution on the accelerator of the Data-Flow Soft-Core, both partial data and instructions are eliminated as traffic for load and store activities. Data-flow instructions serve to describe a program and to dynamically change the context of a data-flow program graph inside the accelerator, on-the-fly. Our proposed design aims at combining the performance of a fine-grained data-flow architecture with the flexibility of reconfiguration, without requiring a partial reconfiguration or new bit-stream for reprogramming it. The potential of the data-flow implementation of a function or functional program can be exploited simply by relying on its description through the data-flow instructions that reprogram the Data-Flow Soft-Core. Moreover, the data streaming process will mirror those present in other FPGA applications. Finally, we show the advantages of this approach by presenting two test cases and providing the quantitative and numerical results of our evaluations.

DaSH: A benchmark suite for hybrid dataflow and shared memory programming models

Abstract The current trend in development of parallel programming models is to combine different well established models into a single programming model in order to support efficient implementation of a wide range of real world applications. The dataflow model has particularly managed to recapture the interest of the research community due to its ability to express parallelism efficiently. Thus, a number of recently proposed hybrid parallel programming models combine dataflow and traditional shared memory models. Their findings have influenced the introduction of task dependency in the OpenMP 4.0 standard. This article presents DaSH – the first comprehensive benchmark suite for hybrid dataflow and shared memory programming models. DaSH features 11 benchmarks, each representing one of the Berkeley dwarfs that capture patterns of communication and computation common to a wide range of emerging applications. DaSH also includes sequential and shared-memory implementations based on OpenMP and Intel TBB to facilitate easy comparison between hybrid dataflow implementations and traditional shared memory implementations based on work-sharing and/or tasks. Finally, we use DaSH to evaluate three different hybrid dataflow models, identify their advantages and shortcomings, and motivate further research on their characteristics.

Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs

Multimedia applications and embedded platforms are both becoming very complex in order to improve user experience. Thus, multimedia developers need high-level methods to automate time-consuming and error-prone tasks. Dynamic dataflow modeling is attractive to describe complex applications, such as video codecs, at a high level of abstraction. This paper presents a dataflow-based design approach to implement video codecs on embedded multi-core platforms. First, we introduce a custom architecture model to design low-power multi-core chips based on distributed memory and Transport-Triggered Architecture processor cores. Then, we describe software synthesis techniques to improve dynamic dataflow implementations. This methodology has been implemented into open-source tools and demonstrated on video decoders based on the MPEG-4 Visual standard and the new High Efficiency Video Coding standard. The simulations achieve real-time decoding (40FPS) of high definition (720P) MPEG-4 Visual video sequences on a custom multi-core platform clocked at 1Ghz, which is an improvement of more than 100 % over previously proposed implementations.

Fast and Efficient Implementation of Forward Clarke Transform's Algorithm Data Flow on FPGA for Green Technology

This paper is about the implementation of Forward Clarke Transform (FCT) module on Field Programmable Logic Controller (FPGA) using Verilog hardware description language (HDL). FCT that is mathematically represented in matrix form is used to convert a three-phase Permanent Magnet Synchronous Motor (PMSM) stator current into two-phase quadrature current. The input and output (I/O) interphase signals i.e. ia and ib, iα and iβ are all in 2’s complement 16 bits. To address the complicated hardware based floating arithmetic, floating point calculations involved are handled as fixed-point. Apart from that, the module is also required to complete the FCT calculation within four clock cycles.

Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware

In recent years, parameterized dataflow has evolved as a useful framework for modeling synchronous and cyclo-static graphs in which arbitrary parameters can be changed dynamically. Parameterized dataflow has proven to have significant expressive power for managing dynamics of DSP applications in important ways. However, efficient hardware synthesis techniques for parameterized dataflow representations are lacking. This paper addresses this void; specifically, the paper investigates efficient field programmable gate array (FPGA)-based implementation of parameterized cyclo-static dataflow (PCSDF) graphs. We develop a scheduling technique for throughput-constrained minimization of dataflow buffering requirements when mapping PCSDF representations of DSP applications onto FPGAs. The proposed scheduling technique is integrated with an existing formal schedule model, called the generalized schedule tree, to reduce schedule cost. To demonstrate our new, hardware-oriented PCSDF scheduling technique, we have designed a real-time base station emulator prototype based on a subset of long-term evolution (LTE), which is a key cellular standard.

Securing skeletal systems with limited performance penalty: The muskel experience

Algorithmic skeletons have been exploited to implement several parallel programming environments, targeting workstation clusters as well as workstation networks and computational grids. When targeting non-dedicated clusters, workstation networks and grids, security has to be taken adequately into account in order to guarantee both code and data confidentiality and integrity. However, introducing security is usually an expensive activity, both in terms of the effort required to managed security mechanisms and in terms of the time spent performing security related activities at run time. We discuss the cost of security introduction as well as how some features typical of skeleton technology can be exploited to improve the efficiency code and data securing in a typical skeleton based parallel programming environment and we evaluate the performance cost of security mechanisms implemented exploiting state of the art tools. In particular, we take into account the cost of security introduction in muskel, a Java based skeletal system exploiting macro data flow implementation technology. We consider the adoption of mechanisms that allow securing all the communications involving remote, unreliable nodes and we evaluate the cost of such mechanisms. Also, we consider the implications on the computational grains needed to scale secure and insecure skeletal computations.