Cache Implementation Research Articles

Optimizing Web-Based Survey Applications with Laravel and Cloud Computing

This study aims to optimize the performance of a web-based survey application through the implementation of the Laravel framework and cloud computing technology. Survey applications often face challenges regarding response speed and scalability as the number of users increases. In this research, performance testing of the application was conducted both before and after optimization. The test results show that the application's response time significantly decreased after the implementation of Laravel and cloud technology. Before optimization, the average response time reached 4.5 seconds at 1,000 users, while after optimization, it dropped to 2.2 seconds. This performance improvement was achieved through efficient caching implementation, database query optimization using Eloquent ORM, and balanced load distribution via load balancers. Additionally, the application's availability increased to 99.9% thanks to cloud features such as auto-scaling and data replication. The conclusion of this study indicates that the combination of Laravel and cloud computing technology is effective in enhancing the performance and reliability of web-based survey applications, providing practical guidance for other web application developers facing similar challenges.

Optimisasi Web Service REST API Menggunakan Load Balancer dan Cache dengan Algoritma Round Robin (Studi Kasus: Madani Infosphere)

In today's digital era, the use of REST API Web Services is increasing, becoming a major foundation in web application development due to its simplicity and scalability. However, increased demand and data complexity often lead to a decrease in Web Service performance, especially in terms of response time and service availability. This research focuses on the performance optimisation of Madani Infosphere Web Service, an information platform developed by the non-profit organisation MADANI Berkelanjutan. This platform previously used a single server architecture that was prone to performance issues. To overcome this, this research applies load balancer technology with a round robin algorithm to distribute the workload evenly across multiple servers and uses a cache to store frequently accessed data. The results show that the use of load balancer with round robin algorithm is effective in overcoming potential server overload, making Web Service performance more stable and responsive. In addition, the cache implementation successfully reduces server workload and speeds up response time. Thus, this optimisation can improve the efficiency and availability of Madani Infosphere Web Services.

Reducing DNS Traffic to Enhance Home IoT Device Privacy.

The deployment of Internet of Things (IoT) devices is widespread in different environments, including homes. Although security is incorporated, homes can become targets for cyberattacks because of their vulnerabilities. IoT devices generate Domain Name Server (DNS) traffic primarily for communication with Internet servers. In this paper, we present a detailed analysis of DNS traffic from IoT devices. The queried domains are highly distinctive, enabling attackers to easily identify the IoT device. In addition, we observed an unexpectedly high volume of queries. The analysis reveals that the same domains are repeatedly queried, DNS queries are transmitted in plain text over User Datagram Protocol (UDP) port 53 (Do53), and the excessive generation of traffic poses a security risk by amplifying an attacker's ability to identify IoT devices and execute more precise, targeted attacks, consequently escalating the potential compromise of the entire IoT ecosystem. We propose a simple measure that can be taken to reduce DNS traffic generated by IoT devices, thus preventing it from being used as a vector to identify the types of devices present in the network. This measure is based on the implementation of the DNS cache in the devices; caching few resources increases privacy considerably.

MOODLE MANUAL UPGRADE METHODOLOGY

This abstract outlines a systematic four-step methodology for upgrading Moodle from version 3.6.5 to 3.9.9. The process begins with comprehensive backup and preparation, followed by the replacement of the Moodle codebase and execution of the upgrade script. Post-upgrade checks are performed to ensure the smooth functioning of core and third-party components. Additionally, the abstract explores the actions and functions of the cron script, emphasizing its role in executing scheduled tasks critical for Moodle's operation.
 Furthermore, the document sheds light on common reasons behind slow Moodle operation and provides practical tips for enhancing system speed. Recommendations include optimizing server resources, database maintenance, strategic caching implementation, and the judicious use of content delivery networks (CDNs). The importance of upgrading PHP and database versions is highlighted, alongside the benefits of disabling unused features and employing server monitoring tools. The abstract emphasizes the significance of staying abreast of Moodle updates for continued performance improvements and bug fixes, offering a holistic guide for upgrading and optimizing Moodle systems.

Bagaimana Mengatasi Masalah Server-Lag pada Website Kampus Ketika Penyusunan KRS

The purpose of this research is to analyze server-LAG problems on campus websites when preparing KRS. This type of research is qualitative research using experimental methods. Data collection techniques in this study used literature and interview methods. The literature method is a method used to obtain data and supporting theories in making web servers. Based on the results of the tests and analysis carried out, it can be concluded that the steps taken to overcome server lag on the campus website have been successful. Implementation of database optimization, caching and load balancing significantly improves server performance and reduces lag. This success in addressing the server lag issue helped create a better user experience during the KRS build period.

MRAM-Based Cache System Design and Policy Optimization for RISC-V Multi-Core CPUs

On-chip cache, being the crucial constituent of central processing unit (CPU), accounts for a pivotal portion of the system’s overall power consumption. The typical SRAM-based cache is vulnerable to high static leakage power consumption, while multiple challenges encountered in scaling up its capacity. In the paper, magnetic random-access-memory (MRAM) cache is considered as a promising candidate in RISC-V CPU systems. After analyzing the performances of single-core, dual-core, quad-core, and octa-core systems, a quad-core RISC-V based CPU system with a two- level hierarchical cache structure is designed, in which Spin-Orbit Transfer (SOT)-MRAM is adopted as the L1 private cache and Spin-Transfer Torque (STT)-MRAM as the L2 shared cache. Details on the microarchitecture of the multi-core CPU design are provided. Energy evaluation shows that this quad-core cache system can achieve 66.4% leakage power saving and 34.5% total power saving compared to SRAM. For high efficiency of data-exchange in the novel MRAM CPU systems, three types of characteristics optimizing methods are proposed. An optimized cache-coherency protocol incorporating non-inclusive policy is proposed. The quad-core system is updated by adding the coherence control module and a directory in the design scheme. The simulation results on multiple dimensions show that the policy of the hybrid MRAM memory is a promising candidate for multi-core RISC-V system, with the benefits of low-power consumption and high hit rate. Finally, the peripheral circuitry and manufacturing cost for the implementation of the MRAM cache is discussed in the paper.

Cache-related Hardware Capabilities and Their Impact on Information Security

Caching is an important technique to speed-up execution, and its implementation and use cases vary. When applied specifically to the memory hierarchy, caching is used to speed up memory accesses and memory translations. Different cache implementations are considered microarchitectural secrets and oftentimes change between generations. The integration of caches in hardware greatly influences security policy enforcement in the platform since caches maintain copies of code and data and their security properties. Examples of attacks due to the existence of caches are side-channels against cryptographic software, recent speculative execution abuses to leak secret data, and usages of cache-based manipulations (e.g., forcing cache splits/incoherence) to hide from security software detection. This survey examines the security issues due to different cache usages in a microarchitecture. The survey also explains the most complicated caching features and their impact on the security of the platform in different scenarios.

Mobile Edge Computing, Springer International Publishing, 2022: ISBN: 978-3-030-83944-4, 113 Pages

This book offers comprehensive, self-contained knowledge on mobile edge computing (MEC), not only covering the basics, essential topics, and future directions, but also detailing the design and implementation of communications, computing, and caching in MEC. The first chapter provides an overview of MEC by outlining its technological characteristics and distinctions from cloud computing. Mobile cloud computing (MCC) integrates cloud computing with mobile devices to enhance mobile device capabilities such as computing and storage. Compared to mobile cloud computing (MCC), MEC provides an IT service environment and cloud computing capabilities at the edge of the network, within the radio access network, and close to mobile subscribers. Thus, the user experience can be further improved by the execution of computation- and storage-sensitive applications through computing in the edge cloud and the delivery of related computing services. This book provides basic concepts of MEC, explores the promising application scenarios of MEC integrated with emerging technologies, and gives insights into possible future directions of MEC. Due to the broad coverage on both the principle and applications of MEC, the book allows for easy cross-referencing and is suitable for researchers seeking a comprehensive but quick view of the current and future research focus about MEC and the related areas.

Novel prioritized LRU circuits for shared cache in computer systems

Cache sharing technique is critical in multi-core and multi-threading systems. It potentially delays the execution of real-time applications and makes the prediction of the worst-case execution time (WCET) of real-time applications more challenging. Prioritized cache has been demonstrated as a promising approach to address this challenge. Instead of the conventional prioritized cache schemes realized at the architecture level by using cache controllers, this work presents two prioritized least recently used (LRU) cache replacement circuits that directly accomplish the prioritization inside the cache circuits, hence significantly reduces the cache access latency. The performance, hardware and power overheads due to the proposed prioritized LRU circuits are investigated based on a 65 nm CMOS technology. It shows that the proposed circuits have very low overhead compared to conventional cache circuits. The presented techniques will lead to more effective prioritized shared cache implementations and benefit the development of high-performance real-time systems.

A Novel Framework for Fog Computing: Lattice-Based Secured Framework for Cloud Interface

Interconnection and intercommunication between people, processes, and things have been enhanced with the development of the Internet of Things (IoT) and extended with fog computing for better efficiency. Fog computing improves the network services and circumvents the problem of escalated data management as an interface between cloud and terminal with the requirement of secure data transmission. In this article, a novel security framework is designed for fog computing intended for improving the security of IoT. This framework uses single point of aggregation from fog interface and lattice cryptographic approach to establish the security for the services. Azure cloud platform and Sage lattice cryptographic base have been employed to evaluate the performance of the framework. It is noticed that the Level 1-Level 2 (L1–L2) cache implementation in the system significantly improves the efficiency of the framework. The results show that the proposed framework is robust in preventing attacks on fog nodes and additionally provides an advantage for low communication overhead.

ABOUT OPTIMAL MANAGEMENT OF WORK-STEALING DEQUES IN TWO-LEVEL MEMORY

In the parallel work-stealing load balancers, each core owns a personal buffer of tasks called deque. One end of the deque is used by its owner to add and retrieve tasks, while the second end is used by other cores to steal tasks. Our experience in software implementations has shown that it is important to optimize work with cache memory in parallel work-stealing load balancers. For example, by modifying deques so that they can hold task objects instead of pointers, we managed to increase the performance more than 2.5 times on the CPU-bound applications and decrease last-level cache misses up to 30 % compared to Intel TBB (Threading Building Blocks) and Intel / MIT (Massachusetts Institute of Technology) Cilk work-stealing schedulers. Therefore, it is important to investigate special methods of working with deques in two-level memory, and not just try to optimize the use of universal cache implementations. The paper analyzes the problem of optimal control of a work-stealing deque in two-level memory (for example, registers – random access memory), where probabilities of parallel operations with the deque are known. The classic sequential cyclic method for representing a deque in memory is considered. If a deque overflows or empty, we transfer elements from its middle part from the fast memory to the slow memory, since data from the end parts of the deque may be needed earlier. The problem is to find the optimal number of elements from both sides of the deque to leave in the fast memory if the deque is full or empty. The average time to get into the states when it is necessary to reallocate the memory is maximized.The simulation model and the mathematical model in the form of an absorbing Markov chain were constructed. The results of numerical experiments are presented.

An Analysis on Wireless Edge Caching in In-Band Full-Duplex FR2-IAB Networks

This article develops a 3GPP inspired analytical framework for cache-enabled in-band full-duplex (IBFD) integrated access and backhaul (IAB) heterogeneous network in the FR2 (millimeter wave) band. In particular, by assuming wide-band FR2 channel model, we analyze the performance of cache-enabled IAB nodes that serve multiple users in access in IBFD mode through hybrid beamforming architectures. Since, IBFD transmission is considered, the IAB nodes are able to retrieve any non-cached files simultaneously through backhaul from the IAB donor nodes, which also use hybrid beamforming architectures. Utilizing stochastic geometry tools, we first derive the lower-bound for the average success probability (ASP) of file delivery for the considered system model, using which we evaluate two quintessential performance metrics: latency and average throughput of file delivery under a cache-enabled content delivery phase. Further, as a baseline for comparison, we also consider conventional half-duplex techniques, namely time division duplex and frequency division duplex transmission and evaluate their performance with respect to cache size, node density, content popularity, antenna numbers, blockage density, and residual self-interference. Numerical results demonstrate the precedency of using wireless edge caching as a cost-effective measure for improving the FR2-IAB network's performance. More importantly, we provide several design insights for the implementation of wireless edge caching in IBFD FR2-IAB networks, with respect to required residual self interference cancellation, increasing antenna number, increasing target data rate and IAB node density.

The New Non-Volatile Based On STT-MRAM Lies in The Design and Implementation of High-Speed Cache of Magnetic Random Memory Material

With the development of semiconductor technology, the buffer of processor integration is getting larger and larger. The high-speed design of storage capacity of traditional memory devices has an important connection with cache. How to design new non-volatile magnetic random memory has become an important step. To solve these problems, researchers at home and abroad have discussed a large number of new non-volatile memory technologies, which have excellent characteristics such as non-volatility, low power consumption and high memory density. The key optimization techniques for the disadvantages of high write power, limited write life and long write latency of the new non-volatile memory are analyzed. Finally, the possible research directions of new non-volatile memory devices in future cache optimization are discussed.

Energy-efficient Delay-aware and Profit Maximization Caching enabled, Congestion Control in Stochastic Network

We are presenting a new unified structure for dynamic distributed forwarding and congestion-controlled network caching enabled. Improved use of data transfer capacity and storage resources in Stochastic networks in aspects of energy-efficient and profit-maximization. In the investigation of stochastic networks, a framework has been developed for combined implementation of caching, forwarding and traffic command called the Markov Decision Process in Stochastic Learning (MDPSL) strategy. The MDPSL structure uses a virtual plane that manages customer request prices, as well as a real plane that processes actual interest packets and data packets. It can accomplish dynamically structured transmission and caching. It can fulfill dynamically distributed forwarding and caching. Focus on MDPSL communication and queuing systems, including wireless networks with time-varying channels, mobility, and arrival of random traffic. Using this framework, estimates of the time are optimized such as throughput, utility throughput, energy, and distortion. Explicit performance-delay tradeoffs are provided to show the expense of attaining optimality. A congestion control algorithm is intended to improve client services subject to network stability when optimally coupled with forwarding and caching algorithms

GpuSPHASE—A shared memory caching implementation for 2D SPH using CUDA (new version announcement)

Smoothed particle hydrodynamics (SPH) is a meshless Lagrangian method that has been successfully applied to computational fluid dynamics (CFD), solid mechanics and many other multi-physics problems. gpuSPHASE is a graphics processing unit (GPU) accelerated solver for 2D SPH simulations that is optimized for relatively small numbers of particles but long physical simulation times as required to solve transport phenomena in process engineering applications. The software aims at a low latency execution pipeline with thousands of iterations per second on contemporary GPU accelerator cards, while using symplectic time integration for long term stability of the simulations. For this, a novel caching algorithm for CUDA shared memory is proposed and implemented. gpuSPHASE is validated against SPHERIC test cases and the performance is evaluated and compared to state of the art implementations of the SPH method. New version program summaryProgram Title: gpuSPHASEProgram Files doi:http://dx.doi.org/10.17632/8vpwwh8th5.2Licensing provisions: GPLv3Programming language: CUDA C++Journal reference of previous version: Comput. Phys. Comm., 213 (2017), 165–180Does the new version supersede the previous version?: YesReasons for the new version: The software is in active development and thus several new features have been added since the initial release. Those improvements are related to accuracy, maintainability and platform independence.Summary of revisions:•Build process: The previous distribution was relatively complicated to build due to the external dependencies of the software. This process has been optimized such that CMake is used for all platforms to build the software. For performance reasons several decisions have to be taken at compile time, which can be configured through the CMake configuration. External dependencies are platform independently retrieved and included using CMake features.•Code: While optimized for performance, zero-cost decorators were added to improve the readability of the code. Furthermore, a weak form of type punning was used previously, which was entirely replaced by a custom defined type to eliminate the possibility of undefined behavior.•Floating point precision: As described in the literature and in the original version of the manuscript, 32 bit floating point precision is generally sufficient for SPH simulations of water [1,2]. While not optimized for the opportunistic caching strategy, 64 bit floating point precision has been added. Due to the significant performance loss of consumer grade GPUs for FP64 computations the performance may be considerably worse. FP64 precision can be used to check if FP32 is sufficient and thus detect simulations where FP64 is required. This feature does not influence the already implemented cell relative position calculations that allow for large computational domains without any loss in accuracy [2]. Improvements can be observed e.g. in the Poiseuille flow test case released with DualSPHysics 4.2 [3] with the configuration of ν=10−6 [m2.s−1], ρ=1000 [kg.m−3] and a body force of Fx=10−4 [m.s−2], as shown in Fig. 1.•Particle shifting: The diffusion based particle shifting method proposed by Skillen et al. (2013) [4] is implemented. As suggested by Lind et al. (2012) [5], the particle concentration is augmented with the factor fij to prevent pairing instability for free surface flows [6]. The improvements are best observed with Poiseuille flow configuration of ν=10−2 [m2.s−1], ρ=1 [kg.m−3] and a body force of Fx=10−1 [m.s−2] [7]. This test case does not converge with gpuSPHASE using single or double precision due to the problems described by [8]. Enabling particle shifting allows to execute the simulation until t>100, as shown in Fig. 2.•Advective-diffusion and heat transfer: Heat transfer is modeled based on the temperature T and the thermal conductivity k as dT∕dt=ρ−1cp−1k∇2T. The SPH discretization is implemented according to Alshaer et al. (2017) [9] and successfully verified [10]. The mass transfer of concentration C is modeled using the advective-diffusion equation dC∕dt=D∇2C−∇⋅(vC). The model is implemented according to the discretization of Aristodemo et al. [11] and successfully verified [12].Nature of problem: gpuSPHASE aims at free surface fluid dynamics simulations of long running physical phenomena that must be calculated in the order of real-time. Due to the long physical time and thus the requirement of millions to billions of iterations, the code is restricted to 2D. This restriction allows for optimizations that would not be possible for more generic approaches [13].Solution method: gpuSPHASE is a 2D SPH solver for CUDA capable devices that is optimized for the computation of real-time simulations. Compile time definitions allow to optimize the code for fast execution of the CUDA kernel functions. Symplectic time integration and correction methods enable stable simulations of long physical time problems.

Cold, hard cache

On the implementation and maintenance of caches.

대용량 파일시스템을 위한 선택적 압축을 지원하는 인-메모리 캐시의 설계와 구현

대용량 파일시스템을 위한 선택적 압축을 지원하는 인-메모리 캐시의 설계와 구현

Impact of spintronic memory on multicore cache hierarchy design

Spintronic memory [spin-transfer torque-magnetic random access memory (STT-MRAM)] is an attractive alternative technology to CMOS since it offers higher density and virtually no leakage current. Spintronic memory continues to require higher write energy, however, presenting a challenge to memory hierarchy design when energy consumption is a concern. This study motivates the use of STT-MRAM for the first-level caches of a multicore processor to reduce energy consumption without significantly degrading the performance. The large STT-MRAM first-level cache implementation saves leakage power. Moreover, the use of small level-0 cache regains the performance drop due to STT-MRAM long write latencies. The combination of both reduces the energy-delay product by 65% on average compared with CMOS baseline. The proposed STT hierarchy also shows good scalability over the CMOS with a few benchmarks which scale significantly better. The PARSEC and Splash2 benchmark suites are analysed running on a modern multicore platform, comparing performance, energy consumption and scalability of the spintronic cache system to a CMOS design.

A program optimization for automatic database result caching

Most popular Web applications rely on persistent databases based on languages like SQL for declarative specification of data models and the operations that read and modify them. As applications scale up in user base, they often face challenges responding quickly enough to the high volume of requests. A common aid is caching of database results in the application's memory space, taking advantage of program-specific knowledge of which caching schemes are sound and useful, embodied in handwritten modifications that make the program less maintainable. These modifications also require nontrivial reasoning about the read-write dependencies across operations. In this paper, we present a compiler optimization that automatically adds sound SQL caching to Web applications coded in the Ur/Web domain-specific functional language, with no modifications required to source code. We use a custom cache implementation that supports concurrent operations without compromising the transactional semantics of the database abstraction. Through experiments with microbenchmarks and production Ur/Web applications, we show that our optimization in many cases enables an easy doubling or more of an application's throughput, requiring nothing more than passing an extra command-line flag to the compiler.

안드로이드 IPC 가속화를 위한 커널 바인더 캐쉬의 설계 및 구현

안드로이드 IPC 가속화를 위한 커널 바인더 캐쉬의 설계 및 구현