Implementation Of Bus Research Articles

SpaceWire State Machine Verification Based on Model Checking

SpaceWire is a high-speed data transmission bus standard proposed by ESA for the aerospace applications. Hosted by the National Astronomical Observatories, Chinese Academy of Sciences, the Space Solar Telescope project takes the SpaceWire bus standard as space communication link. The SpaceWire communication circuit implemented by our group is a part of the SST project. In order to improve the fault detection and fault correction capacity and the reliability of the SpaceWire bus, we add a more error analysis and data storage module into the original six state modules of the standard protocol in the exchange layer.We adopt the formal verification method based on the model checking to verify the finite state machine of the SpaceWire control module. The properties expressed by the high-order temporal logic formula are verified automatically to be true by the SMV model verifier of the Cadence Company. Verification results show that our SpaceWire bus implementation and the additional error analysis and data storage module are faithful to the protocol specification. Therefore, we also can integrate SpaceWire bus circuit into the SST project.

Managing Demographic Data Inconsistencies in Healthcare Information Systems

Healthcare IT and IS departments have the arduous task of managing the varied information sources into readily accessible, consistent and referential information views. Patient hospital workflows, from admission to discharge, provide a series of data streams for convergences into disparate systems. Protocols such as DICOM and HL7 exist for the purposes of exchanging information within the PACS and RIS information silos in the hospital enterprise. These protocols ensure data confidence for downstream systems, but are not designed to provide referential data cross system in the system-of-systems model. As data crosses the PACS and RIS information domains, data inconsistency is introduced. This paper explores the causes for data disparity and presents a referential data design for disparate systems through the implementation of an XML bus for data exchange and an RDF framework for data semantic.

A service‐oriented virtual learning environment

PurposeThe purpose of this paper is to present a prototype pluggable service‐oriented virtual learning environment, enabling teachers to create an integrated teaching environment using tools that have been chosen to best meet their academic requirements.Design/methodology/approachThis is an implementation of a WAFFLE Bus. A microkernel software design pattern is used to enable tools to be added and removed from the system. An enterprise service bus is used to provide workflow and message transformation functionality. Tools are managed through web service interfaces and Shibboleth is used to effect interoperability at the web application user interface. The initial services for the prototype were chosen to implement a simple web service teaching workflow.FindingsFirst, Shibboleth is shown to provide a solution to the virtual learning environment tools' interoperability problem. Second, the service‐oriented virtual learning environment naturally leads to the ability to operate with many different types of information channels in and out of the system. This leads to a multiplicity of possible types of context‐dependent user interface. Third, immersive 3D, possibly the most interesting interface, will provide a context amenable to even the smallest development teams for the introduction of artificial intelligence into teaching. Finally, web service workflow is shown to provide a viable option for the implementation of learning designs with advantages and disadvantages compared to existing approaches.Research limitations/implicationsDifferent types of information channels are associated with different security problems. It will be important to determine what the best ways are of establishing secure channels to student personal learning environments. The present web service workflow design tools are of the highest quality and usability, but the design process is still a job for a specialist. It might be possible, however, to modify these open source tools to bring the design process within the grasp of non‐specialists.Originality/valueThe software system presented herein represents one possible path leading away from VLE monolithy using a service‐oriented approach. A new solution to the tools' interoperability problem is presented along with a multi‐faceted approach to the user interface. The enterprise service bus creates a flexible platform for the delivery of web service teaching and learning workflows. It is posited that the use of an immersive 3D user interface will create a context that facilitates the introduction of an artificial intelligence layer into the virtual learning environment that can serve robot teaching avatars.

Implementation of a Walking School Bus: Lessons Learned: July 2009 issue of Journal of School Health

Journal of School HealthVolume 79, Issue 7 p. 333-335 Implementation of a Walking School Bus: Lessons Learned: July 2009 issue of Journal of School Health First published: 01 June 2009 https://doi.org/10.1111/j.1746-1561.2008.00418.x Journal of School Health is written and produced by the American School Health Association. Activity planning, test questions, and pilot testing were conducted by Susan F. Wooley, PhD, CHES, and selected members of ASHA’s Editorial Board and Professional Development Committee. Read the full textAboutPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinked InRedditWechat Volume79, Issue7July 2009Pages 333-335 RelatedInformation

Implementation of a Walking School Bus: Lessons Learned*

Obesity is rapidly becoming the most common chronic medical condition affecting children. To address this crisis, an Albuquerque, New Mexico, elementary school partnered with University of New Mexico researchers and conducted a Walking School Bus (WSB). The purpose of this article is to examine the feasibility of implementing a WSB. This pilot study featured 2 WSBs conducted for 10 weeks with kindergarten through fifth-grade students from a predominantly Hispanic elementary school. Qualitative and quantitative data, including coordinator field notes, attendance records, surveys of student and parent satisfaction, and a focus group, were used to evaluate feasibility. Student and adult participants expressed a high degree of enthusiasm regarding their involvement in the WSB. Participants uniformly indicated that the WSB provided a supportive and safe environment to promote social interaction and physical activity. Conducting a WSB in an urban, underserved school district is feasible but requires attention to ensure participants' involvement and safety. In particular, it is recommended to begin the planning process early to enhance investment from key stakeholders. Effective, low-cost interventions are increasingly desired as solutions to the problem of obesity. The WSB has emerged as a promising strategy to address obesity and encourage partnerships across different social levels. Further research is necessary to assess the logistical challenges associated with conducting a large-scale WSB trial and whether such efforts lead to reductions in obesity risk factors.

1802 知的マルチエージエント交通流シミュレータへのオンデマンドバスの実装とその評価(OS18.社会・環境・防災シミュレーション(1),オーガナイズドセッション)

1802 知的マルチエージエント交通流シミュレータへのオンデマンドバスの実装とその評価(OS18.社会・環境・防災シミュレーション(1),オーガナイズドセッション)

Design and implementation of enterprise service bus

The existing Enterprise Service Bus(ESB)products can hardly fulfill enterprises' changeable requirements of business processes due to their absence or inadequacy of manageability,flexibility and openness.Importing work flow technology,an innovative ESB design scheme was proposed with component model as its basis,service chain as the design,deployment and management unit of ESB applications,and event-driven asynchronous messaging as the communication mechanism.Our work has been applied in the NPUESB system.Results prove that the design can not only effectively realize enterprise application integration,but also efficiently implement and manage ESB applications and deal with changeable enterprise business processes,meanwhile possessing good openness and scalability properties.

Micromission spacecraft: a low-cost, high-capability platform for space science missions

The Ball Micromission Spacecraft (MSC) is a multi-purpose platform capable of supporting science missions at distances from the Sun ranging from 0.7 to 1.7 AU. In the baseline scenario, MSC is launched as a secondary payload on an Ariane 5 rocket from Kourou, French Guiana, to GTO using the Ariane 5 structure for auxiliary payloads (ASAP5). The maximum launch wet mass is 242 Kg and can include up to 45 Kg of payload depending on AV needs. The on-board propulsion system is used for maneuvering in the Earth-Moon system and injecting the spacecraft into its final orbit or trajectory. For Mars missions, MSC enables orbiting Mars for science payloads and/or communications and navigation assets, or for precision Mars fly-bys to drop up to six probes. The micromissions spacecraft bus can be used for science targets other than Mars, including the Moon, Earth, Venus, Earth-Sun Lagrange points, or other small bodies. This paper summarizes the current spacecraft concept and describes the multimission spacecraft bus implementation in more detail.

PNoC: a flexible circuit-switched NoC for FPGA-based systems

Increases in chip density due to Moore's law allow for the implementation of ever larger and more complex systems on a single chip (SoCs). The communication mechanisms employed in such SoCs are an important contribution to their overall performance. Networks on chip (NoCs) promise to overcome the scalability problems found in bus-based interconnect. To date, most work has focused on packet-switched NoCs. Circuit-switched networks are an intriguing alternative, which promise high communication rates and predictable communication latencies. A new lightweight circuit-switched architecture called programmable NoC (PNoC) is described. PNoC is a flexible architecture that is suitable for use in FPGA-based systems. Implementation results on a Virtex-II Pro device are given using an image binarisation demonstration which resulted in as much as a 23× speedup compared with a shared bus implementation.

Wrapper-based bus implementation techniques for performance improvement and cost reduction

A low-cost wrapper-based bus implementation is described that performs well in system-on-chip (SOC) designs. Novel wrapper implementation techniques are used to create wrappers without embedded data buffers. The bus uses 1) a novel slave wrapper interface that supports flow control signals, 2) a write buffer switching technique for the master wrappers to achieve good performance at a small hardware cost, 3) a novel retry management technique called slave designated retry control (SDRC) to enable slow IP core connections and a livelock avoidance scheme using the SDRC technique, and 4) a novel bit-width conversion technique using data-width converters embedded in the bus multiplexers. A CPU-based SOC designed with the proposed bus showed that these techniques can increase throughput by about 14%, and reduce read and write latencies by about 16% and 11% compared to a conventional wrapper-based bus, when running a modeled average traffic pattern for this chip. The implemented results show that these techniques can reduce the hardware costs by 28% or 50% compared with two conventional wrapper-based conversion techniques. The chip is implemented using 0.15-/spl mu/m CMOS process technologies. The area for the on-chip bus is 3.3 mm/sup 2/ and the operation clock frequency is 200 MHz.

Implementation of a self-timed segmented bus

We propose an asynchronous structure for implementation on a SoC. An intersegment topological arrangement preserves parallelization and, through a so-called central arbiter, efficiently organizes communication with high signaling speed in the proposed structure. Researchers proposed the concept of segmenting buses primarily for multicomputer architectures. More recent approaches address on-chip implementation of segmented buses. We present an asynchronous segmented-bus architecture targeted for the modular design of high-performance SoC applications. The structure not only enables faster operation than a conventional bus system but also offers lower power consumption per transferred data item. This is possible because segmentation is realized in such a way that the majority of data transfers in the system are intrasegment transactions on relatively short wires with low or moderate capacitive loads.

Handshake protocol using return-to-zero data encoding for high performance asynchronous bus

In SoC design, synchronous buses are used frequently to interconnect several IPs. However, it is difficult to use synchronous buses for SoC design because of the increase of wire delay caused by the crosstalk effect and the difficulty of synchronisation caused by the clock-skew problem. The use of an asynchronous bus is an alternative solution for SoC design methodology. A new handshake protocol is proposed using the return-to-zero data encoding scheme for the implementation of a new high performance asynchronous bus. Simulation results reveal that the proposed handshake protocol increases the read throughput of the asynchronous bus by 30.5%, and decreases the read latency by 12.5%.

Low cost access to Mars—Mars micromissions spacecraft

The Mars micromission (MM) spacecraft (MMSC) is a multi-purpose platform capable of orbiting Mars for communications/navigation and science payloads or for precision Mars flybys to drop up to six probes. An MMSC is launched as a secondary payload on an Ariane 5 rocket from Kourou, French Guiana, to GTO using the Ariane 5 structure for auxiliary payloads (ASAP5). The maximum launch wet mass is 222 kg and can include up to 45 kg of payload depending on Δ V needs. The on-board propulsion system is used for maneuvering in the Earth–Moon system and injecting the spacecraft into Mars transfer orbit and, if needed, Mars orbit. The first MMSC to be launched in early 2003 will be a Communications/Navigation (Comm/Nav) Orbiter. JPL is responsible for the Comm/Nav payload. Ball Aerospace, working with JPL, provides the multi-purpose spacecraft bus, system integration and test, and assists in operations over the 3 year mission duration. This paper summarizes the baseline spacecraft concept for the first Mars Com/Nav mission as defined at the start of the program in February 2000 and describes the spacecraft bus implementation in more detail.

Design and Implementation of Bus–Holding Control Strategies with Real-Time Information

A systematic study is described to address various design and implementation issues associated with the problem of real-time bus holding control. Two holding control models have been investigated. The first model follows the conventional threshold-based control logic that determines holding times on the basis of headway to the preceding bus. The second model makes use of both preceding and following headways in identifying optimal control decisions with the assumption that real-time bus location information is available for estimating future bus arrivals at the control stop. An extensive simulation analysis is performed using a real-fife bus route operated by the Grand River Transit of the region of Waterloo, Ontario. The simulation results have substantiated several conclusions and yielded new findings on various issues such as where to set the control point, how many control points should be used, what is the optimal control strength, and what is the value of real-time location information.

Parallel optical interconnects may reduce the communication bottleneck in symmetric multiprocessors

We start with a detailed analysis of the communication issues in today's symmetric multiprocessor (SMP) architectures to study the benefits of implementing optical interconnects (OI) in these machines. We show that the transmission of block addresses is the most critical communication bottleneck of future large SMPs owing to the need to preserve the coherence of data duplicated in caches. An address transmission bandwidth as high as 200-300 Gb/s may be necessary in ten years from now; this requirement will represent a difficult challenge for shared electric buses. In this context we suggest the introduction of simple point-to-point OIs for a SMP cache-coherent switch, i.e., for a VLSI switch that would emulate the shared-bus function. The operation might require as much as 10,000 input-outputs (IOs) to connect 100 processors, particularly if one maintains the present parallelism of transmissions to preserve a large bandwidth and a short memory access latency. The interest for OIs comes from the potential increase of the transmission frequency and from the possible integration of such a high density of IOs on top of electronic chips to overcome packaging issues. Then we consider the implementation of an optical bus that is a multipoint optical line involving more optical technology. This solution allows multiple simultaneous accesses to the bus, but the preservation of the coherence of caches can no longer be maintained with the usual fast snooping protocols.

Universal serial bus implementation in an integrated access chip for ISDN systems

The universal serial bus technology comes as a response to the increasing demands for unified interfaces and the need for flexible easy-to-use products for personal computers. Integrating this technology into PBXs and ISDN ICs can play an important role in the integration of telecommunications and computer technologies. The paper reports the findings of a research project called COPARIS for ISDN chip design with the additional USB interface. It also presents the software and hardware design approaches for implementing USB functions in the COPARIS chip. The research indicates that a balanced approach is the best, where the computationally intensive functions should be implemented in hardware and the rest in software.

A delay analysis of FDQ (Fair Distributed Queue) and DQDB networks

A delay analysis of FDQ (Fair Distributed Queue) and DQDB (with and without the BWB mechanism) is presented. A network of two active nodes with a large separation of nodes is considered in each case. Under the common set of assumptions of single buffer nodes, geometric arrivals and the packet size of one segment, the mean delay at each node is obtained using limited independence assumptions. Results from the analyses are compared to simulation results. The analyses are shown to be quite accurate for low to moderate loads and they only require the solution of polynomial equations. The mean delays at both stations under FDQ with equal arrival rates are shown to be almost equal. DQDB and DQDB with BWB have increasingly asymmetric mean delays with higher arrival rates. For a dual bus implementation, the mean delay at the upstream station is less than that at the downstream station for all three protocols. FDQ has the smallest difference between the two stations' delay results and DQDB has the highest in this case.

The Movie-2 Digital Audio/Video Expansion Bus

The use of economical, general-purpose personal computers (PCs) in demanding professional video applications like nonlinear editing, graphics creation, animation recording, three-dimensional (3-D) rendering, video-on-demand, and commercial insertion continues to grow. In these applications, specialized PC adapters are typically used to handle the massive processing requirements for transporting natural data types in real time. Commonly used subsystems include video input/output (I/O), video processing (digital video effects [DVE-mixing]), video compression/decompression (codec), audio I/O, audio processing (equalization [EQ]-mixing), mass storage interface, network interface, and video-in-a-window console display. Although it is possible to accomplish some of these tasks with host central processing unit (CPU) software and a single highly integrated adapter, most professional systems require more than one adapter. How to connect these multiple video adapters together inside a PC is a question that system integrators have been wrestling with for many years. This paper examines the limitations of commercially available buses in these demanding broadcast video applications, proposes the Movie-2 bus as a high-performance open-architecture standard that overcomes these limitations, discusses the Movie-2 bus in detail, and finally, presents a model of a typical nonlinear editing platform as an example of system-level Movie-2 bus implementation.

Performance Implications of Synchronization Support for Parallel Fortran Programs

This paper studies the performance implications of architectural synchronization support for automatically parallelized numerical programs. As the basis for this work, we analyze the needs for synchronization in automatically parallelized numerical programs. The needs are due to task scheduling, iteration scheduling, barriers, and data dependence handling. We present synchronization algorithms for efficient execution of programs with nested parallel loops. Next, we identify how various hardware synchronization support can be used to satisfy these software synchronization needs. The synchronization primitives studied are test&set, fetch&add, and exchange-byte operations. In addition to these, synchronization bus implementation of lock/unlock and fetch&add operations are also considered. Finally, we ran experiments to quantify the impact of various architectural support on the performance of a bus-based shared memory multiprocessor running automatically parallelized numerical programs. We found that supporting an atomic fetch&add primitive in shared memory is as effective as supporting lock/unlock operations with a synchronization bus. Both achieve substantial performance improvement over the cases where atomic test&set and exchange-byte operations are supported in shared memory.

A hierarchical analog test bus framework for testing mixed-signal integrated circuits and printed circuit boards

Progress in analog circuit testing has been hindered by the lack of structured design-for-testability methodologies. With the increasing complexity of analog/mixed-signal circuits, test program development time is now a major obstacle in achieving shorttime-to-market, while production testing cost is a prominent factor in total production cost. TheAnalog Autonomous Test is a structured design-for-testability scheme for analog circuits. Originally developed for testing analog circuits at chip level, AAT extends naturally to cover testing of mixedsignal integrated circuits mounted on printed circuit boards. With the addition of an analog test bus to PCBs, testability for analog components (bothcore circuits andglue circuits) can be improved, in a manner similar to that achieved for digital boards by the IEEE 1149.1 boundary scan scheme. Details on the implementation of thisAnalog Autonomous Test Bus, both at chip level and board level, are presented here. Its limitations and potential applications are also discussed.