Block Cipher Implementations Research Articles

Power Attack Vulnerability Assessment of Circuit-Level PRESENT Encryption IP Using Artificial Intelligence Mechanisms

Artificial Intelligence (AI) schemes eliminate the need for intellectual human knowledge of crypto algorithms to facilitate side-channel attacks on security implementations. Side channel attack analysis for circuit-level hardware (VLSI) implementations of symmetric-key block ciphers through artificial machine models are yet to be addressed. The proposed design of block cipher architecture, which is the implementation under attack features, secure adiabatic logic style the Charge Balancing Symmetric Pre-resolve Adiabatic Logic (CBSPAL). This style exhibits uniform power consumption through its inherent circuit arrangement, which makes it robust toward side-channel power attacks. This paper considers several Multilayer Perceptron (MLP) architectures to mount non-profiled side-channel attacks on round 1- PRESENT circuit-level implementation. Supervised learning of the MLP models through training with power waveforms employs binary LSB labeling. An attack on the custom dataset with 50,000 supply power traces collected from the CBSPAL implementation fails to retrieve secret information in any of the 8 bytes. The traditional Correlation Power Attack (CPA) was also not thriving with the proposed implementation. Comparison is made through a similar attack approach on benchmark AES (ASCAD dataset), which distinguishes the secret information throughout all the parameters of interest: normalized accuracy, normalized NMM accuracy and rank plots on byte 3.

FortiFix : A Fault Attack Aware Compiler Framework for Crypto Implementations

Fault attacks are one of the most powerful forms of cryptanalytic attack on embedded systems, that can corrupt cipher’s operations leading to a breach of confidentiality and integrity. A single precisely injected fault during the execution of a cipher can be exploited to retrieve the secret key in a few milliseconds. Naïve countermeasures introduced into implementation can lead to huge overheads, making them unusable in resource-constraint environments. On the other hand, optimized countermeasures requires significant knowledge, not just about the attack, but also on the (a) the cryptographic properties of the cipher, (b) the program structure, and (c) the underlying hardware architecture. This makes the protection against fault attacks tedious and error-prone. In this paper, we introduce the first automated compiler framework named FortiFix that can detect and patch fault exploitable regions in a block cipher implementation. The framework has two phases. The pre-compilation phase identifies regions in the source code of a block cipher that are vulnerable to fault attacks. The second phase is incorporated as transformation passes in the LLVM compiler to find exploitable instructions, quantify the impact of a fault on these instructions, and finally insert appropriate countermeasures based on user defined security requirements. As a proof of concept, we have evaluated two block cipher implementations AES-128 and CLEFIA-128 on three different hardware platforms such as MSP430 (16-bit), ARM (32-bit) and RISCV (32-bit).

Efficient Design for a Hardware Implementation of the LED Block Cipher

Efficient Design for a Hardware Implementation of the LED Block Cipher

On the dynamic reconfigurable implementations of MISTY1 and KASUMI block ciphers.

Novel hardware architectures for dynamic reconfigurable implementation of 64-bit MISTY1 and KASUMI block ciphers are proposed to enhance the performance of cryptographic chips for secure IoT applications. The SRL32 primitive (Reconfigurable Look up Tables-RLUTs) and DPR (Dynamic Partial Reconfiguration) are employed to reconfigure single round MISTY1 / KASUMI algorithms on the run-time. The RLUT based architecture attains dynamic logic functionality without extra hardware resources by internally modifying the LUT contents. The proposed adaptive reconfiguration can be adopted as a productive countermeasure against malicious attacks with the added advantage of less reconfiguration time (RT). On the other hand, the block architecture reconfigures the core hardware by externally uploading the partial bit stream and has significant advantages in terms of low area implementation and power reduction. Implementation was carried out on FPGA, Xilinx Virtex 7. The results showed remarkable results with very low area of 668 / 514 CLB slices consuming 460 / 354 mW for RLUT and DPR architectures respectively. Moreover, the throughput obtained for RLUT architecture was found as 364 Mbps with very less RT of 445 nsec while DPR architecture achieved speed of 176 Mbps with RT of 1.1 msec. The novel architectures outperform the stand-alone existing hardware designs of MISTY1 and KASUMI implementations by adding the dynamic reconfigurability while at the same achieving high performance in terms of area and throughput. Design details of proposed unified architectures and comprehensive analysis is described.

New Second-order Threshold Implementation of Sm4 Block Cipher

New Second-order Threshold Implementation of Sm4 Block Cipher

SAND-2: An optimized implementation of lightweight block cipher

The development of ARX-based lightweight block ciphers has been plagued by the difficulty of theoretical security analysis. SAND solves this problem better by obtaining an equivalent representation based on a synthetic S-box. This paper analyzed SAND in terms of diffusivity and found that it can be optimized. SAND has the issue of slow diffusion after the initial plaintext and key are all 0. On the other hand, it takes at least 11 rounds for SAND to reach full diffusion without AddRoundKey. Thus, this paper proposes a high-diffusion architecture SAND-2 to address the above issues. Firstly, issue 1 is solved by replacing the AND operation with a NAND operation and calling the round function dynamically. Then, in order to solve issue 2, P1 and P2 permutations are introduced into G0 and G1, respectively. The full diffusion speed of SAND-2 is 63.7% increased compared to SAND. In addition, the comparison results of hardware indicators show that the hardware resources of SAND-2 are slightly lower, and the throughput is 10% higher than SAND. Finally, the security analysis shows that SAND-2 reaches the upper bound of the resisting differential analysis in fewer rounds.

Efficient low-area, high-frequency hardware implementations of shadow lightweight block ciphers for resource-constrained IoT devices and sensor networks

Efficient low-area, high-frequency hardware implementations of shadow lightweight block ciphers for resource-constrained IoT devices and sensor networks

Hardware implementations of LBlock and XXTEA lightweight block ciphers for resource-constrained IoT application

Recent growth in the number of connected Internet of Things (IoT) devices in a network has raised lot of security related issues. Since these devices are mostly battery powered, have low memory and weak computational capability, therefore lightweight ciphers are the most suitable choice for providing security. Among various lightweight ciphers available, we have chosen to implement corrected block TEA (XXTEA) and LBlock ciphers. These lightweight ciphers are feistel based, having simple encryption algorithms. In this work, two different architectures are proposed namely round-based implementation of LBlock cipher and serial implementation of XXTEA cipher with variable length message. Both the architectures are implemented on different field programmable gate array (FPGA) device families and application-specific integrated circuit (ASIC) implementation is performed on 0.18 μm complementary metal-oxide semiconductor (CMOS) technology. By analysing the performance metrics, comparison of the proposed work is done with the existing ciphers. For the proposed LBlock and XXTEA variable length architectures, the percentage improvement obtained with respect to area consumption is 50.92% and 26.04% respectively.

AVX512Crypto: Parallel Implementations of Korean Block Ciphers Using AVX-512

Cryptographic algorithms are widely used as the foundation of various security systems and applications (e.g., secure communication, blockchain systems, and cloud services). A block cipher is an essential cryptographic algorithm to achieve confidentiality. This paper proposes parallel implementations of Korean block ciphers using Advanced Vector eXtension (AVX)-512, which is a new Single instruction, multiple data (SIMD) instruction set that has recently been integrated into several high-end Intel central processing unit (CPU). Target algorithms are LEA, HIGHT, and CHAM block ciphers. Additionally, this paper also proposes applicable implementing techniques, which are designed for each algorithm. These enable to use of parallel processing instructions in AVX-512 properly for each algorithm. The proposed LEA-128 (192, 256 resp.)implementation demonstrates a performance improvement of 506.09% (323.31%, 386.76% resp.) compared to the reference code, and our HIGHT implementation exhibits a performance improvement of 520.88% compared to the reference code. In addition, CHAM-64/128 (128/256 resp.) implementation shows a performance improvement of 1,325.81% (833.61% resp.) compared to the reference code. In addition, we measured the performance with a 32MB long message. LEA-128 (192, 256 resp.) implementation showed an improvement of 556.32% (594.74%, 615.38% resp.) compared with the reference code. Also, HIGHT implementation showed 834.40%, and CHAM showed 1,332.40% (832.86% resp.) for CHAM-64/128 (CHAM-128/256 resp.), compared by the reference code. To the best of our knowledge, this is the first result of the study to optimize Korean cryptographic algorithms using the AVX-512 instruction set. The proposed methods can effectively be used in Addition, Rotation, and XOR (ARX)-based cryptographic algorithms, enabling efficient cryptographic algorithm processing in various environments such as hash-based signatures, service environments, gateway, and edge computing.

Hardware Implementations of LBlock and XXTEA Lightweight Block Ciphers for Resource-Constrained IoT application

Hardware Implementations of LBlock and XXTEA Lightweight Block Ciphers for Resource-Constrained IoT application

Efficient hardware implementation of SIMECK lightweight block cipher

The internet of things (IoT) has recently expanded, resulting in a new world of smart gadgets with substantial security consequences. For their vital security role, lightweight block ciphers have gained a significant amount of development in low resource devices (LRDs). SIMECK is a new lightweight block cipher family that incorporates the finest aspect of both SIMON and SPECK. SIMECK is a more efficient block cipher than SIMON and SPECK cipher. These lightweight ciphers are especially referred to as an alternative to the AES for RCD. In this study, area optimised architecture is implemented for SIMECK lightweight block cipher with sizes: 64/128. For implementation on different platforms such as Sparton-6, Sparton-3, Virtex-7, Virtex-6, Virtex-5 and Virtex-4 FPGA are used to examine several properties such as block size, key scheduling, and throughput, among others. The proposed area optimised architecture have attained a maximum operating frequency of 496.429 MHz with 61 slices and a high throughput of 706.032 Mbps on the Virtex-7 platform.

Latency-Aware Accelerator of SIMECK Lightweight Block Cipher

This article presents a latency-optimized implementation of the SIMECK lightweight block cipher on a field-programmable-gate-array (FPGA) platform with a block and key lengths of 32 and 64 bits. The critical features of our architecture include parallelism, pipelining, and a dedicated controller. Parallelism splits the digits of the key and data blocks into smaller segments. Then, we use each segmented key and data block in parallel for encryption and decryption computations. Splitting key and data blocks helps reduce the required clock cycles. A two-stage pipelining is used to shorten the critical path and to improve the clock frequency. A dedicated controller is implemented to provide control functionalities. For the performance evaluation of our design, we report implementation results for two different cases on Xilinx 7-series FPGA devices. For our case one, the proposed architecture can operate on 382, 379, and 388 MHz frequencies for Kintex-7, Virtex-7, and Artix-7 devices. On the same Kintex-7, Virtex-7, and Artix-7 devices, the utilized Slices are 49, 51, and 50. For one encryption and decryption computation, our design takes 16 clock cycles. The minimum power consumption is 172 mW on the Kintex-7 device. For the second case, we targeted the same circuit frequency of 50 MHz for synthesis on Kintex-7, Virtex-7, and Artix-7 devices. With minimum hardware resource utilization (51 Slices), the least consumed power of 13.203 mW is obtained for the Kintex-7 device. For proof-of-concept, the proposed SIMECK design is validated on the NEXYS 4 FPGA with the Artix-7 device. Consequently, the implementation results reveal that the proposed architecture is suitable for many resource-constrained cryptographic applications.

Parallel Implementations of ARIA on ARM Processors and Graphics Processing Unit

The ARIA block cipher algorithm is Korean standard, IETF standard (RFC 5794), and part of the TLS/SSL protocol. In this paper, we present the parallel implementation of ARIA block cipher on ARMv8 processors and GPU. The ARMv8 processor is the latest 64-bit ARM architecture and supports ASIMD for parallel implementations. With this feature, 4 and 16 parallel encryption blocks are implemented to optimize the substitution layer of ARIA block cipher using four different Sboxes. Compared to previous works, the performance was improved by 2.76× and 8.73× at 4-plaintext and 16-plaintext cases, respectively. We also present optimal implementation on GPU architectures. GPUs are highly parallel programmable processors featuring maximum arithmetic and memory bandwidth. Optimal settings of ARIA block cipher implementation on GPU were analyzed using the Nsight Compute profiler provided by Nvidia. We found that using shared memory reduces the execution timing when performing substitution operations with Sbox tables. When using many threads with shared memory instead of global memory, it improves performance by about 1.08∼1.43×. Additionally, techniques using table expansion to minimize bank conflicts have been found to be inefficient when tables cannot be copied by the size of the bank. We measured the performance of ARIA block ciphers implemented with various settings. This represents an optimized GPU implementation of the ARIA block cipher.

Low-Latency and Low-Randomness Second-Order Masked Cubic Functions

Masking schemes are the most popular countermeasure to mitigate Side-Channel Analysis (SCA) attacks. Compared to software, their hardware implementations require certain considerations with respect to physical defaults, such as glitches. To counter this extended leakage effect, the technique known as Threshold Implementation (TI) has proven to be a reliable solution. However, its efficiency, namely the number of shares, is tied to the algebraic degree of the target function. As a result, the application of TI may lead to unaffordable implementation costs. This dependency is relaxed by the successor schemes where the minimum number of d + 1 shares suffice for dth-order protection independent of the function’s algebraic degree. By this, although the number of input shares is reduced, the implementation costs are not necessarily low due to their high demand for fresh randomness. It becomes even more challenging when a joint low-latency and low-randomness cost is desired. In this work, we provide a methodology to realize the second-order glitch-extended probing-secure implementation of cubic functions with three shares while allowing to reuse fresh randomness. This enables us to construct low-latency second-order secure implementations of several popular lightweight block ciphers, including Skinny, Midori, and Prince, with a very limited number of fresh masks. Notably, compared to state-of-the-art equivalent implementations, our designs lower the latency in terms of the number of clock cycles while keeping randomness costs low.

Secure and Robust Internet of Things with High-Speed Implementation of PRESENT and GIFT Block Ciphers on GPU

With the advent of the Internet of Things (IoT) and cloud computing technologies, vast amounts of data are being created and communicated in IoT networks. Block ciphers are being used to protect these data from malicious attacks. Massive computation overheads introduced by bulk encryption using block ciphers can become a performance bottleneck of the server, requiring high throughput. As the need for high-speed encryption required for such communications has emerged, research is underway to utilize a graphics processor for encryption processing based on the high processing power of the GPU. Applying bit-slicing of lightweight ciphers was not covered in the previous implementation of lightweight ciphers on GPU architecture. In this paper, we implemented PRESENT and GIFT lightweight block ciphers GPU architectures. It minimizes the computation overhead caused by optimizing the algorithm by applying the bit-slicing technique. We performed practical analysis by testing practical use cases. We tested PRESENT-80, PRESENT-128, GIFT-64, and GIFT-128 block ciphers in RTX3060 platforms. The throughput of the exhaustive search are 553.932 Gbps, 529.952 Gbps, 583.859 Gbps, and 214.284 Gbps for PRESENT-80, PRESENT-128, GIFT-64, and GIFT-128, respectively. For the case of data encryption, it achieved 24.264 Gbps, 24.522 Gbps, 85.283 Gbps, and 10.723 Gbps for PRESENT-80, PRESENT-128, GIFT-64, and GIFT-128, respectively. Specifically, the proposed implementation of a PRESENT block cipher is approximately 4× higher performance than the latest work that implements PRESENT block cipher. Lastly, the proposed implementation of a GIFT block cipher on GPU is the first implementation for the server environment.

High-throughput block cipher implementations with SIMD

The development of new technologies has put forward higher requirements for the performance and security of block ciphers. To meet the needs of these situations, Bitslicing is one of the block cipher implementation techniques which can provide high efficiency and resistance to cache-timing attacks. The S-box is usually the most time-consuming component for Bitsliced implementations. In this paper, we present techniques to optimize the S-box implementation and derive the most compact representations available for Bitslicing. Then we show that the efficiency of linear layers can be further improved by introducing a state-of-the-art technique. As a result, our implementations have significant advantages over previous implementations. The throughputs of our AES and SM4 implementations achieve 27068Mbps and 30026Mbps on i5-11335G7, both exceeding the throughput of AES-NI on the same platform.

Ultra-lightweight FPGA-based RC5 designs via data-dependent rotation block optimization

Lightweight cryptography provides security to resource-constrained applications, such as embedded systems and Internet of Things (IoT) devices. This work explores an ultra-lightweight implementation of RC5 block cipher, via two levels of serialization. We also exploit a resource-sharing optimization technique for the data-dependent rotation (DDR) module, since it is the most computationally intensive component of the RC5 block cipher. We present two RC5 hardware structures: (i) an 8-bit serial RC5 architecture using a dual-part DDR unit; this design occupies only 54 slices on a Spartan-6 FPGA device and is 69% superior in terms of Throughput-per-Slice (TPS) compared to the smallest 8-bit AES FPGA implementation, (ii) a novel bit-serial RC5 architecture based on shift-register LUT (SRL) primitives; this design consumes only 20 Spartan-6 slices and shows 81% improvement in throughput performance at the expense of only 5% additional area resources compared to the smallest bit-serial AES design reported. The proposed DDR-based optimizations and efficient time scheduling make our proposed designs outperform most of the state-of-the-art lightweight block cipher designs in terms of hardware efficiency (with regard to TPS).

Bit-policy based chosen-plaintext collision attack on reused-mask AES

Side-channel collision attacks have shown good efficiency on breaking unprotected or reused-mask implementations of block ciphers. Depending on the relationship between “Hamming distance of values” and “average distance of traces”, this work presents a novel bit-policy based chosen-plaintext collision attack to break a software implementation of reused-mask AES. Some factors affecting the success rates of the proposed scheme and their reasons are analyzed, such as how to measure the distance of traces, signal-to-noise ratio (SNR), how to select points of interest (POI) and the number of traces (n). In this paper, two measurements, the least square method (LSM) and the central moment product method (CMP), are adopted to calculate the distance of traces. Then their probability distribution and efficiency are theoretically analyzed and simulated. As a result, CMP outperforms LSM, and all the other three factors, i.e. SNR, POI, n, are relevant to the distribution of LSM and CMP. When LSM and CMP are combined with the proposed scheme and the compared ones, both theoretical and practical analysis are given to illustrate how the number of traces impacts on the success rates at different levels of SNR; as a result the developed attack has the best performance among all the compared schemes at both low and high level of SNR, especially at high level of SNR. To gain a success rate of 95%, at SNR of 0 dB and −8 dB, our optimal scheme and the compared optimal scheme have 800 and 4500 less energy traces, respectively. Furthermore, our attack requires no detailed knowledge about the design of SBoxes, nor does it require templates for profiling.

Lightweight ANU-II block cipher on field programmable gate array

Nowadays the number of embedded devices communicating over a network is increasing. Thus, the need for security appeared. Considering various constraints for the limited resources devices is very important. These constraints include power, memory, area and latency. A perfect environment for satisfying requirements of security in limited resources devices is lightweight cryptography. A recent lightweight algorithm that has a low area and high throughput which is the ANU-II block cipher. Many technologies like the internet of things (IoT) needed lightweight hardware architectures to provide security for it. In IoT issues like the size of memory, power consumption and smaller gate counts need to take care of by using lightweight cryptography. This paper presents hardware lightweight data path implementation for the ANU-II algorithm using field programmable gate array (FPGA). This paper presents a hardware implementation of a 64-bit ANU-II block cipher. Also, this research presents comparisons based on various design metrics among our data path for the ANU-II cipher and other existing data path designs. The result of the proposed design shows a high throughput of 1502.31, 1951.86, and 2696.47 Mbps. Also, it shows the high efficiency of 7.0201, 31.9977, and 10.6579 Mbps/slice as compared to other ciphers in this paper.

FPGA Implementation of Rectangle Lightweight Block Cipher

Abstract: Block ciphers are basic building blocks for network security. In recent years, designing a lightweight block cipher is the main goal of VLSI design engineers. In this paper, we have designed and verified the functionality of the RECTANGLE block cipher which is one of the lightweight block cipher using Modelsim simulator and implemented using Intel Quartus Prime 18.0 FPGA device. Using the bit-slice technique a RECTANGLE block cipher allows lightweight and fast implementations. The en-cryption architecture has two parts one is round transformation and the other is key scheduling. RECTANGLE uses Substitution-Permutation network. It takes 64-bit plain text and an 80-bit key as an input and converts it into a 64-bit ciphertext. There are three main advantages of using the RECTANGLE block cipher. First, it has a simple design. Second, it is very hardware friendly. By selecting the proper S-block RECTANGLE can achieve good security performance. Index Terms: Lightweight Block Cipher, Block Ciphers, Encryption, Bit-slice technique, Round Transformation, Key Scheduling, Substitution Block, Permutation Block.