Analog Circuit Implementation Research Articles

Fractional Trigonometric Function Approximations in a Regular System

Introduction: Linear fractional differential equations of the commensurable order, specifically those related to fractional trigonometry, pose challenges in terms of analytical solutions. background: This study presents an approach to the solution of fractional differential equations with commensurate order, specifically those associated with fractional trigonometry. Methods: The purpose of this article is to present a novel approximate analytical technique to solve linear fractional differential equations of the commensurable order, which are related to fractional trigonometry. This method is used to obtain approximate solutions by forming linear combinations of appropriate fractional basic functions, for which Laplace transforms are irrational functions. This approximation technique enables us to represent these functions using timeinvariant linear system models. Also, the implementation of analog circuits of these basic fractional order systems can be obtained using approximation of rational functions. Results: The research demonstrates the efficacy and precision of this method through illustrative examples, showcasing its effectiveness in solving linear fractional systems. Conclusion: The newly introduced approximate analytical method presents a promising approach to solving linear fractional differential equations of the commensurable order, providing accurate solutions and possibly offering applications in various fields.

Bionic modeling and dynamics analysis of heterogeneous brain regions connected by memristive synaptic crosstalk

The coupling dynamics between different brain regions has long been a gap in the study of neural dynamics. To overcome this bottleneck, the synaptic crosstalk characterized by coupled memristors is creatively connected to different brain regions characterized by two heterogeneous Hopfield neural networks (HNNs), forming a novel bionic memristive synaptic crosstalk coupled-HNN (MSC-HNN) model for the first time. Rigorous boundedness and stability analyses ensure that coupling dynamics are generated within a bounded region. Utilizing innovative dynamics methods, it is revealed that the plasticity of synaptic crosstalk allows MSC-HNN to exhibit homogeneous dynamics properties globally, and the two internal HNNs preserve heterogeneous bifurcation processes and attractors. Interestingly, when the initial conditions undergo slight variations, the multistability phenomenon is simultaneously represented by the coexisting parameter bifurcation and the local basin of attraction, which enhances the diversity of activities in MSC-HNN. Furthermore, these novel dynamics effects are evaluated and validated through quantitative calculations of complexity measures and spectra. Subsequently, the developed analog and digital circuit implementation paradigms confirm the feasibility and practical value of MSC-HNN.

On two-parameter bifurcation and analog circuit implementation of a Chameleon chaotic system

In this paper, the two-parameter space bifurcation of a three-dimensional Chameleon system is investigated. It is called Chameleon since the type and the number of the system equilibrium are adjustable for different parameter configurations. Aided by the computation analysis, the graphic structures of two-parameter bifurcation of the Chameleon system are characterized for the first time. With different two-parameter configurations, the bifurcation evolution shows that various self-excited and hidden attractors exist. In addition, numerical demonstration of the two-dimensional slice through the attraction basin space is presented. The results show that the basin of attraction of the typical hidden chaotic attractor does not associated with the origin, which makes the attractor difficult to be numerically localized and experimentally observed. To solve the problem, offset boost scheme is adopted to control the basin of attraction and make it touch the origin, which allows to coin the hidden attractor via configuring zero initial value and making it feasible in experimental observation. Finally, the analog circuit-assisted experiment validated the feasibility of the scheme.

Hyperchaotic multiscroll dynamics, complex behavior in a simple homogeneous dynamical network of jerk oscillators: bidirectional coupling scheme method, dynamical study, analog circuit and microcontroller-based implementation

Hyperchaotic multiscroll dynamics, complex behavior in a simple homogeneous dynamical network of jerk oscillators: bidirectional coupling scheme method, dynamical study, analog circuit and microcontroller-based implementation

Dynamics of a simple third-order autonomous MLC circuit

Abstract This paper reports a new simple third-order memristive circuit only containing three elements of inductor, capacitor, and active generalized memristor, from which rich dynamical behaviors are generated. With a dimensionless system model, the performed analyses show that the proposed memristive circuit only has an unstable equilibrium point of saddle-focus-type. The antimonotonicity makes the system exhibits coexisting chaotic and periodic bubbling single-parameter bifurcation routes. Moreover, the quasiperiodic torus, various bursting and beat phenomena with chaotic and periodic oscillations are demonstrated by numerical simulations. The analog circuit implementations are further presented to show the phase portraits and time sequences of the generated attractors.

Locally Active Memristor-Based Neuromorphic Circuit: Firing Pattern and Hardware Experiment

Analog circuit implementation of neuron model is an essential category of neuromorphic circuit since it can reproduce neuron firing patterns and assist in exploring neuron-based applications. The neuron models built by electrophysiological ion transport mechanism can effectively mimic the neuron firing patterns. However, they are rather difficult to implement on analog level because these neuron models involve complex exponential nonlinearities for characterizing the ion channels. Thanks to the superiorities of locally active memristor in constructing artificial neuron circuit, two locally active memristors are employed to characterize the sodium and potassium ion channels and then a memristive neuromorphic circuit is successfully built in this paper. Numerical simulations demonstrate that the memristive neuromorphic circuit can generate abundant firing patterns with respect to memristor-and stimulus-related parameters. Moreover, quasi-periodic bifurcation behavior and coexisting firing patterns are triggered by different memristor initial conditions. Employing off-the-shelf discrete circuit components, a PCB-based analog circuit is manually constructed and hardware experiments are executed. Experimental results captured from hardware measurements satisfactorily verify the numerically simulated ones and effectively show the feasibility of the memristive neuromorphic circuit in generating neuron firing patterns.

Dynamic behaviors of a two-neuron model coupled with memristor and its analog circuit implementation

Dynamic behaviors of a two-neuron model coupled with memristor and its analog circuit implementation

Field-programmable analog array (FPAA) based four-state adaptive oscillator for analog frequency analysis.

Adaptive oscillators are a subset of nonlinear oscillators that can learn and encode information in dynamic states. By appending additional states onto a classical Hopf oscillator, a four-state adaptive oscillator is created that can learn both the frequency and amplitude of an external forcing frequency. Analog circuit implementations of nonlinear differential systems are usually achieved by using operational amplifier-based integrator networks, in which redesign procedures of the system topology is time consuming. Here, an analog implementation of a four-state adaptive oscillator is presented for the first time as a field-programmable analog array (FPAA) circuit. The FPAA diagram is described, and the hardware performance is presented. This simple FPAA-based oscillator can be used as an analog frequency analyzer, as its frequency state will evolve to match the external forcing frequency. Notably, this is done without any analog-to-digital conversion or pre-processing, making it an ideal frequency analyzer for low-power and low-memory applications.

Analog circuit implementation and adaptive neural backstepping control of a network of four Duffing-type MEMS resonators with mechanical and electrostatic coupling

This paper investigates the analog circuit implementation and adaptive neural backstepping control of a network of four Duffing-type MEMS resonators with mechanical and electrostatic coupling. Firstly, the mathematical model of such network is established by using a series-parallel mode of mechanical and electrostatic coupling between MEMS resonators. Secondly, the dynamic analysis reveals that the coupled network can generate complex nonlinear behaviors which seriously affect the system performance without taking actions. Thirdly, based on the energy flow theory, its equivalent analog electronic circuit is established to further verify inherent dynamical characteristics of a network of four Duffing-type MEMS resonators. Fourthly, to suppress the mentioned harmful nonlinear behaviors above, an adaptive neural backstepping control scheme is proposed here wherein the interval type 2 fuzzy neural network (IT2FNN) is used to estimate unknown nonlinear functions along with cosine barrier function to guarantee states boundedness. Stability analysis proves that all signals of the closed-loop system are bounded and the tracking errors are limited to the pregiven boundary. Finally, the effectiveness of our scheme is testified by abundant numerical simulation results.

Numerical Sensitivity Analysis and Hardware Verification of a Transiently-Chaotic Attractor

We introduce a new chaotic system with nonhyperbolic equilibrium and study its sensitivity to different numerical integration techniques prior to implementing it on an FPGA. We show that the discretization method used in numerically integrating the set of differential equations in MATLAB and Mathematica does not yield chaotic behavior except when a low accuracy Euler method is used. More accurate higher-order numerical algorithms (such as midpoint and fourth-order Runge–Kutta) result in divergence in both MATLAB and Mathematica (but not Python), which agrees with the divergence observed in an analog circuit implementation of the system. However, a fixed-point digital FPGA implementation confirms the chaotic behavior of the system using Euler and fourth-order Runge–Kutta realizations. Therefore, the increased sensitivity of chaotic systems with nonhyperbolic equilibrium should be carefully considered for reproducibility.

Analogue circuit implementation of a new logistic‐like map

Discrete chaotic system has complex dynamics and becomes to be a present hot topic, but its analogue circuit implementation is rarely discussed. In this paper, by simplifying the logistic map, a new Logistic-like map is proposed. Its cobweb plots, bifurcations, Lyapunov exponents, and dynamic map are investigated theoretically and numerically. The results show that the Logistic-like map has complex dynamical behaviours. And then Psim simulation model is proposed to verify the feasibility of analogue circuit implementation. Finally, an analogue circuit experiment is performed and its results are consistent with the simulation results. The circuit designed is very simple and has less components, which can further broaden the applications of discrete chaotic map in applications.

Synchronisation of Unified Chaotic Systems Using Modified Nonlinear Active Control: Circuit Design, Implementation, and Secure Communication

This paper accounts synchronisation of unified chaotic systems using a modified nonlinear active control technique, its circuit analogue circuit implementation, and secure communication. The proposed nonlinear active control approach utilises appropriate states of the unified chaotic systems. The modified nonlinear active control leads to the coupled error dynamics and does not require the external forcing parameters or gains, which differs from the active control techniques reported in the literature. The designed control law ensures the asymptotic stability in large, and the necessary condition is derived using Lyapunov stability theory. Further, the performance of the designed nonlinear active controller is compared based on different time integral performance of the errors with active, adaptive, and sliding mode control techniques. Numerical and circuit simulations are performed in MATLAB and NI-Multisim environments, respectively. Circuit simulated results accord to MATLAB simulation results. Further, unified chaotic system, its synchronisation, and application to secure communication are validated with breadboard circuit/hardware implementation.

Chaos analysis of Buck converter with non-singular fractional derivative

This paper presents a time-domain mathematical model of the Buck converter using the non-singular fractional derivative that was proposed by Caputo and Fabrizio. The time-domain waveforms of the output voltage and current of the converter in different orders are obtained, and the correctness of the time-domain model has been verified. On this basis, the discrete iterative mapping model of the fractional-order Buck converter in peak current mode is established. The chaotic behaviors of the system are studied by numerical simulations, and the bifurcation diagrams at different fractional orders are investigated. The analog circuit implementation of the fractional-order Buck converter is established, and the results obtained via circuit simulations are consistent with the results of numerical simulations, which effectively validate the accuracy of the previous theoretical analysis.

A Biasing Approach to Design Ultra-Low-Power Standard-Cell-Based Analog Building Blocks for Nanometer SoCs

This paper presents an approach to design analog building blocks for nanometer systems on a chip (SoCs) that are based on digital standard-cells. The proposed approach guarantees that all the CMOS inverters, taken from a standard-cell library, operate with well-defined quiescent current and output voltage, thus allowing the implementation of analog circuits with good robustness against PVT variations. The approach is based on an Analog Body Bias Generator (ABBG) reusable block, similar to the ones adopted in digital applications to cope with process variations, and exploits the bulk terminals of both the p-channel and n-channel MOS transistors of the standard-cell inverter as current and voltage control inputs. The bulk voltages generated by the ABBG are routed to all the standard-cell inverters used for analog functions and allow to set the quiescent current of each cell to a multiple of a reference current and the static output voltage of each cell to half the supply voltage. The full custom design of the ABBG is presented, as well as the design flow to allow the automatic place and route of the proposed standard-cell based analog building blocks. We finally give an example of application trough the design of a fully synthesizable four-stage-gain low-power operational transconductance amplifier (OTA). Both the body bias generator and the OTA have been implemented in a 65-nm CMOS technology. The OTA nominal current consumption is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.75~\mu \text{A}$ </tex-math></inline-formula> with 0.41- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> standard deviation. Good robustness against supply and temperature variations is also found.

Dynamical analysis, FPGA implementation and synchronization for secure communication of new chaotic system with hidden and coexisting attractors

This paper proposes an interesting autonomous chaotic system with hidden attractors and coexisting attractors. The system has no equilibrium, one equilibrium, three equilibria and line equilibria for different parameter regions. The existence of hidden attractors and coexisting attractors of the system has been revealed by using simulation analysis. The bifurcation diagram shows the period-doubling bifurcation route to chaos with the variation of parameters. The analog circuit and FPGA implementation of the system are presented. The synchronization for secure communication of the system is investigated. The synchronization conditions are established by using the adaptive control method.

An effective analog circuit design of approximate fractional-order derivative models of M-SBL fitting method

There is a growing interest in fractional calculus and Fractional Order (FO) system modeling in many fields of science and engineering. Utilization of FO models in real-world applications requires practical realization of FO elements. This study performs an analog circuit realization of approximate FO derivative models based on Modified Stability Boundary Locus (M-SBL) fitting method. This study demonstrates a low-cost and accurate analog circuit implementation of M-SBL fitting based approximate model of FO derivative elements for industrial electronics. For this purpose, a 4th order approximate derivative transfer function model of the M-SBL method is decomposed into the sum of first order low-pass filters form by using Partial Fraction Expansion (PFE) method, and the analog circuit design of the approximate FO derivative model is performed. Firstly, by using the final value theorem, authors theoretically show that the time response of the sum of first order low-pass filter form can converge to the time response of fractional order derivative operators. Then, the approximation performance of proposed FO derivative circuit design is validated for various input waveforms such as sinusoidal, square and sawtooth waveforms via Multisim simulations. Results indicate an accurate realization of the FO derivative in time response (an RMSE of 0.0241). The derivative circuit realization of the M-SBL fitting model in the form of the sum of first order low pass filters can yield a better time response approximation performance compared to the Continued Fraction Expansion (CFE) based ladder network realization of the approximate derivative circuit.

Implementation of Linear and Nonlinear circuits using Operational Transconductance Amplifier

This paper describes implementation of CMOS based linear and non-linear analog circuits using operational trans conductance amplifier as the basic element. These circuits have their applications in communication and signal processing areas. In this work PSPICE is used for the simulation of various analog circuits. The corresponding results are presented.

Design and Implementation of a Low Power Consumption of ASK, FSK PSK, and QSK Modulators Based on FPAA Technology

Wireless communication techniques have become more popular due to their characteristics. These systems adopt the digital modification application, which provides more information for transmission and compatibility with digital data services as well as high information security and quality improvement. Digital wave signal-based communication techniques such as PSK, FSK, ASK, and QPSK considered among the most significant digital modulation techniques. These technologies are a crucial part of digital communication systems. Digital communication devices designed by FPAAs can provide multiple communication without arranging new devices and can support new within seconds. FPAA is extremely easy to reconfigure and program concerning FPGA or DSP-based applications. This article offers real-time implementation of ASK, FSK PSK, and QPSK modulator techniques with low power consumption ”Žbased on the ”Žcapability for dynamic reprogramming of the FPAA AN231E04 device ”ŽAnadigm. FPAA techniques provide growing application and high pliability in the implementation of analog circuits. The measurements achieved from the proposed modulated circuits show that the form and properties of the theoretical outcomes agree perfectly with the practical outcomes. FPAA techniques provide growing application and high pliability in the implementation of analog circuits for minimizing the time of design and testing. Another feature is the minimum power exhaustion (165 mw) due to the switched capacitor method used by the FPAA Chip, which gives a high accuracy process.

A four-state adaptive Hopf oscillator.

Adaptive oscillators (AOs) are nonlinear oscillators with plastic states that encode information. Here, an analog implementation of a four-state adaptive oscillator, including design, fabrication, and verification through hardware measurement, is presented. The result is an oscillator that can learn the frequency and amplitude of an external stimulus over a large range. Notably, the adaptive oscillator learns parameters of external stimuli through its ability to completely synchronize without using any pre- or post-processing methods. Previously, Hopf oscillators have been built as two-state (a regular Hopf oscillator) and three-state (a Hopf oscillator with adaptive frequency) systems via VLSI and FPGA designs. Building on these important implementations, a continuous-time, analog circuit implementation of a Hopf oscillator with adaptive frequency and amplitude is achieved. The hardware measurements and SPICE simulation show good agreement. To demonstrate some of its functionality, the circuit’s response to several complex waveforms, including the response of a square wave, a sawtooth wave, strain gauge data of an impact of a nonlinear beam, and audio data of a noisy microphone recording, are reported. By learning both the frequency and amplitude, this circuit could be used to enhance applications of AOs for robotic gait, clock oscillators, analog frequency analyzers, and energy harvesting.

Analog circuit implementation based on median filter for salt and pepper noise reduction in image

In this study, an analog circuit design instead of using a software is utilized to remove Salt and Pepper (S&P) noise in image. For this purpose, a digital image filtering method which is called median filter is carried out. In median filter method, a current-mode nine-input one-output circuit architecture is preferred since 3 × 3 filtering mask is employed. Median filter circuit is based on a modified bitonic sort network and consists of 26 max/min selector circuits. A current-mode two-input two-output circuit is designed as a max/min selector and there is no biasing current source in the max/min selector structure. In analysis part, two 150 × 150 images with different amount of S&P noise are used and the noise in image is successfully reduced with the help of the proposed circuit design. The performance of the suggested median filter is also verified through the quality measurement parameters such as Structural Similarity Index Metric, Mean Squared Error, Mean Absolute Error and Peak Signal to Noise Ratio. TSMC CMOS 0.18 µm process model is utilized to simulate the introduced median filter circuit.