Implementation Of Acoustic Echo Canceller Research Articles

Design and Implementation of Acoustic Echo Cancellation on Xilinx Zynq for FPGA Co-simulation using LMS Adaptive Filter

Design and Implementation of Acoustic Echo Cancellation on Xilinx Zynq for FPGA Co-simulation using LMS Adaptive Filter

Optimization and Implementation of Acoustic Echo Canceller Based on LMS Algorithm Using FPGA

Acoustic echo is a major problem in voice communication system. It reduces significantly the quality of the signal at the far-end user side. To overcome this problem, the use of Acoustic Echo Canceller (AEC) is unavoidable. This paper presents the implementation of an acoustic echo canceller with long room impulse response of 128 taps modeling real room characteristics using fixed step size least mean square (LMS) algorithm. The floating-to-fixed point conversion of the AEC was optimized by performing different Matlab simulations to reduce the hardware resources and the power consumption while maintaining the expected performance. The Register Transfer Level (RTL) description of the designed AEC is then simulated and synthesized, using ISim from Xilinx, for the target device FPGAVirtex-6 XC6VLX240T. Simulation results proved that optimized fixed-point architecture gives the same performance in terms of convergence rate and steady-state mean square error obtained with floating-point architecture.