Integrated Circuit Implementation Research Articles

A single-IC realizable, electronically tunable, OTA-based full-wave rectifier with simultaneous positive and negative outputs

A new voltage-mode full-wave rectifier (FWR) is proposed in this study. The proposed FWR employs two single-output operational transconductance amplifiers (OTAs), four diodes, and two grounded resistors. It has high input impedance and does not need any extra bias current or voltage sources. It simultaneously provides positive and negative rectified output signals over separate output terminals. The amplitudes of both output signals can be adjusted by varying the resistor values or the transconductance (gm) values of the OTAs. It does not include any floating passive elements, so it is suitable for integrated circuit (IC) implementations. The proposed FWR can be implemented by using a single commercially available IC such as LM13700. However, the proposed FWR has a single matching condition for gm values of the OTAs. Several simulation and experimental test results are added to confirm the theory and show the operability of the proposed circuit.

Simulation and implementation of photonic integrated circuits for the filtering and optical heterodyning of mode-locked comb-lines

We present the simulation and implementation of a photonic integrated circuit (PIC) designed for the filtering and optical heterodyning of comb-lines generated by a 20.97 GHz mode-locked fiber ring laser emitting at the optical C-band. We compare simulations obtained for the coupling junction of the microrings in the PIC with the use of an analytic approach and the finite difference time-domain (FDTD) method. A PIC designed for fabrication with the Triplex asymmetric double-stripe (ADS) waveguides was demonstrated. Using the PIC, we demonstrated the optical heterodyning of pairs of comb-lines filtered by tunable microrings. The phase noise of beat signals located at 20.97 and 41.94 GHz was characterized. We provide a discussion on enhancing the RF power of the beat signals with the use of optical injection locking.

Design and development of MEMS quartz gyroscope measurement and control circuit with automatic gain control principle

Angular velocity is a very important measurement parameter for autonomous driving and industrial applications. The design of MEMS quartz gyro measurement and control circuit has always been the key to restricting the measurement angular velocity performance of gyro system. This paper introduces the application-specific integrated circuit (ASIC) design and implementation of a MEMS quartz gyro measurement and control circuit for angular velocity measurement. The designed nonlinear multiplier can use a square wave to drive the gyro’s sensitive structure at the beginning of gyro start-up, thereby reducing the gyro power-up time. The drive circuit replaces the PLL with an automatic gain control unit composed of peak detection and proportional integration (PI) controller, which makes the MEMS gyro system have good robustness. First, SIMULINK is used to model and simulate the MEMS gyroscope system-level model, which illustrates the feasibility of the drive circuit design scheme. Then, the operating principle of the drive loop is analyzed, and the design of the key circuit modules of the measurement and control circuit is introduced. Finally, the performance of the gyroscope drive and detection circuit is experimentally tested, the amplitude and frequency uncertainty of the gyroscope drive circuit are evaluated, and the bias instability and nonlinearity of the gyroscope are tested, the experiment results show that the gyroscope has good performance.

Analog RF Circuit Sizing by a Cascade of Shallow Neural Networks

A deep neural network architecture for the automatic sizing of analog circuit components is proposed, with a focus on radio frequency (RF) applications in the 2 to 5 GHz region. It addresses the challenges of the typically small number of examples for network training and the existence of multiple solutions, of which impractical values for integrated circuit implementation. We address these issues by restricting the learning to one component size at a time, thanks to a cascade of dedicated shallow neural networks (SNN), where each network constrains the prediction of the next ones. Moreover, the SNNs are individually tuned by a genetic algorithm for the prediction order and accuracy. This reduction of the solution space at each step allows the use of small training sets, and the introduced constraints between SNNs handle component interdependencies. The method is successfully validated on three different types of RF microcircuits: a low-noise amplifier (LNA), a voltage-controlled oscillator (VCO), and a mixer, using 180 nm and 130 nm CMOS implementations. All the predictions were within 5 % of the true values, both at the component and performance levels, and all the responses were obtained in less than 5 s, after 4 to 47 min. training on a regular PC station. The obtained results show that the proposed method is fast and applicable to arbitrary analog circuit topologies, with no need to retrain the developed neural network for each new set of desired circuit performances.

Experimental demonstration of position-controllable topological interface states in high-frequency Kitaev topological integrated circuits

Topological integrated circuits are integrated-circuit realizations of topological systems. Here we show an experimental demonstration by taking the case of the Kitaev topological superconductor model. An integrated-circuit implementation enables us to realize high resonant frequency as high as 13GHz. We explicitly observe the spatial profile of a topological edge state. In particular, the topological interface state between a topological segment and a trivial segment is the Majorana-like state. We construct a switchable structure in the integrated circuit, which enables us to control the position of a Majorana-like interface state arbitrarily along a chain. Our results contribute to the development of topological electronics with high frequency integrated circuits.

A New Electronically Tunable Transimpedance-Mode OTA-Based First-Order Universal Filter and its Quadrature Oscillator Application

This paper suggests a new operational transconductance amplifier (OTA) based electronically tunable transimpedance-mode first-order universal filter (FOUF). The suggested FOUF produces all-pass (AP), high-pass (HP) and low-pass (LP) filter responses simultaneously. It employs three OTAs, two grounded resistors and only one grounded capacitor. Owing to use of grounded passive elements, the suggested FOUF is suitable for integrated circuit implementation. It operates at low power supply voltages. Additionally, the resonance frequency of the suggested AP filter can be adjusted in a wide frequency range. However, the suggested FOUF consists of only one matching condition. Moreover, a sinusoidal quadrature oscillator (QO) application that is derived from the suggested FOUF topology is given. The suggested FOUF and its QO application are simulated by using 0.18-[Formula: see text]m TSMC technology parameters in the SPICE program to validate the presented theory. Finally, an experimental test is performed to demonstrate workability of the suggested AP filter.

Single CDBA-based grounded parallel lossy inductor simulator circuits

Two new configurations for the realization of lossy grounded inductor each employing one current differencing buffered amplifier (CDBA), three resistors, a voltage follower and one grounded capacitor are presented. The realized inductances from the proposed configurations have independent tunability through a single resistor. The proposed circuits make use of the intrinsic current differencing property of CDBAs by not leaving any of its input terminals open or connected to ground. Both the presented circuits use grounded capacitor (which is particularly attractive for integrated circuit implementation) connected at the Z-terminal of CDBA which may also absorb the parasitic capacitance. The proposed lossy inductors can be used in applications such as low frequency sinusoidal oscillator, low pass filter (LPF) and band pass filter (BPF). Such examples may be suitable from the viewpoint of biomedical instrumentation and geo-physical applications. Non-ideal analysis has been carried out to support the theoretical propositions for both the proposed circuits. PSPICE simulation results with CMOS CDBA have been presented to establish the workability of the proposed lossy inductor structures. Experimental results using commercially available AD844 ICs have also been included to demonstrate the viability of the proposed lossy inductors based on CDBAs.

A new deterministic PSO algorithm for real-time systems implemented on low-power devices

The paper presents a novel, deterministic particle swarm optimization (PSO) algorithm, facilitating its implementation in low-power application specific integrated circuits (ASIC) realized in CMOS technology. The PSO algorithms are commonly used in a variety of optimization problems. They allow to search for a global extreme in a selected fitness function, which is used for numerical modeling of specific optimized problems. The conventional version of the algorithm is relatively difficult to implement directly in hardware, especially when each particle is represented by a separate circuit working in parallel with other particles. In such a situation, each particle has to be equipped with its own copy of each function. One of the problems is, for example, an efficient realization of the random function block that provides for each particle some factors used in computing a cognitive and a social velocity components. In this paper we shows a novel way to work around this problem. In the proposed approach the random function does not need to be used. It has been replaced by a simple computationally deterministic mechanism, which at the level of the overall swarm allows for effective emulation of the former random mechanism. We proposed such simplifications that reduce the formulas describing the algorithm to only basic arithmetic and logic operations. Comprehensive investigations have shown that performance of the proposed approach is comparable with its original version or in may situations even better. The proposed algorithm was tested with numerous test functions (50 runs for each tested function), to verify its flexibility and adaptation abilities to different problems.

ASIC Implementation of Nonlinear CNN-Based Data Detector for TDMR System in 28 nm CMOS at 200 Mbits/s Throughput

In this work, we present the first application-specific integrated circuit (ASIC) implementation of a convolutional neural network (CNN)-based data detection channel for the two-dimensional magnetic recording (TDMR) system in hard disk drive (HDD). This chip is fabricated in TSMC 28 nm complementary metal–oxide–semiconductor (CMOS). TDMR signals captured from a real HDD are used to train and test the network, and the chip is designed to make inferences only. This work presents a systematic pipeline to codesign the neural network structure and the corresponding hardware implementation. To meet the high-throughput requirement, the CNN is fully unrolled with dedicated silicon for each convolution layer using systolic arrays. Quantization-aware training algorithms are used to help improve power efficiency without comprising accuracy. Overall, our chip achieves 200 Mbits/s throughput at 0.9 V supply voltage. In addition, it achieves improved detection accuracy compared to the physical-model-based conventional channel. Our chip consumes 173–219 mW power at 200 M3 clock rate for supply voltage 0.8–0.9 V, respectively.

Self-Parameterized Chaotic Map for Low-Cost Robust Chaos

This paper presents a general method, called “self-parameterization”, for designing one-dimensional (1-D) chaotic maps that provide wider chaotic regions compared to existing 1-D maps. A wide chaotic region is a desirable property, as it helps to provide robust performance by enlarging the design space in many hardware-security applications, including reconfigurable logic and encryption. The proposed self-parameterization scheme uses only one existing chaotic map, referred to as the seed map, and a simple transformation block. The effective control parameter of the seed map is treated as an intermediate variable derived from the input and control parameter of the self-parameterized map, under some constraints, to achieve the desired functionality. The widening of the chaotic region after adding self-parameterization is first demonstrated on three ideal map functions: Logistic; Tent; and Sine. A digitized version of the scheme was developed and realized in a field-programmable gate array (FPGA) implementation. An analog version of the proposed scheme was developed with very low transistor-count analog topologies for hardware-constrained integrated circuit (IC) implementation. The chaotic performance of both digital and analog implementations was evaluated with bifurcation plots and four established chaotic entropy metrics: the Lyapunov Exponent; the Correlation Coefficient; the Correlation Dimension; and Approximate Entropy. An application of the proposed scheme was demonstrated in a random number generator design, and the statistical randomness of the generated sequence was verified with the NIST test.

AYARLANABİLİR RADYO FREKANS (RF) ALICI (RX) ENTEGRE DEVRE (IC)

In this work tunable radio frequency (RF) receiver (Rx) integrated circuit (IC) was demonstrated. TSMC 65 nm technology node was selected to implement IC. RF technique has some advantages over biomedical optic molecule investigation methods since it is easy to design, implement. Experimental measurement on live tissue is much easier than optic methods. Nanoscopic creatures have specific binding structures. Their elements construct their shapes and neighborhood conformation between their own atoms. Based on this work differential RF waves will be used to investigate the nanoscopic creatures. Since the investigation of nanoscopic creatures will require to use electromagnetic wave phase shift and scan of different RF frequencies, ultra-wide band (UWB) tunable receiver circuit topology was designed and simulated. For this purpose, Rx block was designed, and simulation work was demonstrated here. In the circuit simulations, off-chip antenna was connected to the low-noise amplifier (LNA) circuit. Specific frequency was around 30 GHz. Frequency tuning was adjusted by changing the source and bias voltages at the active inductor voltage-controlled oscillator (VCO) circuit block. The same VCO block was also used at the Tx circuit before. Antenna signal was modeled by using 33 GHz alternative sinusoidal signal. Antenna signal and 30 GHz active-inductor VCO voltage output were mixed at the mixer circuit block, 3 GHz envelope signal was extracted in this work. Layout implementation of Rx receiver IC was demonstrated.

0.5 V Versatile Voltage- and Transconductance-Mode Analog Filter Using Differential Difference Transconductance Amplifier

In this work, a new versatile voltage- and transconductance-mode analog filter is proposed. The filter, without requiring resistors, employs three differential-difference transconductance amplifiers (DDTAs) and two grounded capacitors, which is suitable for integrated circuit implementation. Unlike previous works, the proposed filter topology provides: (1) high-input and low-output impedances for a voltage-mode (VM) analog filter, that is desirable in a cascade method of realizing higher order filters, and (2) high-input and high-output impedances for a transconductance-mode (TM) analog filter without any circuit modification. Moreover, a quadrature oscillator is obtained by simply adding a feedback connection. Both VM and TM filters provide five standard filtering responses such as low-pass, high-pass, band-pass, band-stop and all-pass responses into single topology. The natural frequency and the condition of oscillation can be electronically controlled. The circuit operates with 0.5 V supply voltage. It was designed and simulated in the Cadence program using 0.18 µm CMOS technology from TSMC.

Hardware implementations of LBlock and XXTEA lightweight block ciphers for resource-constrained IoT application

Recent growth in the number of connected Internet of Things (IoT) devices in a network has raised lot of security related issues. Since these devices are mostly battery powered, have low memory and weak computational capability, therefore lightweight ciphers are the most suitable choice for providing security. Among various lightweight ciphers available, we have chosen to implement corrected block TEA (XXTEA) and LBlock ciphers. These lightweight ciphers are feistel based, having simple encryption algorithms. In this work, two different architectures are proposed namely round-based implementation of LBlock cipher and serial implementation of XXTEA cipher with variable length message. Both the architectures are implemented on different field programmable gate array (FPGA) device families and application-specific integrated circuit (ASIC) implementation is performed on 0.18 μm complementary metal-oxide semiconductor (CMOS) technology. By analysing the performance metrics, comparison of the proposed work is done with the existing ciphers. For the proposed LBlock and XXTEA variable length architectures, the percentage improvement obtained with respect to area consumption is 50.92% and 26.04% respectively.

Mixed-mode Multiphase Sinusoidal Oscillators using Differential Voltage Current Conveyor Transconductance Amplifiers and Only Grounded Passives Components

This article is about mixed-mode multiphase sinusoidal oscillators that are made up of differential voltage current conveyor transconductance amplifier (DVCCTA) and use all the grounded passive components. The proposed multiphase sinusoidal oscillators provide a single DVCCTA, a single grounded resistor and a capacitor for each phase which is suitable for integrated circuit implementation. In addition, the sinusoidal outputs generate currents and voltages simultaneously. The current signals from the outputs have high impedances, which make it easier to connect them directly to the next circuit or stage. The proposed circuits can generate multiphase sinusoidal signals that are both equally phased and in amplitude. The oscillation can be adjusted simultaneously of the frequency of oscillation by the electronic method. A simulation with the PSPICE program and an experiment with commercially available ICs (AD830, AD844, and LM13700N) demonstrated. The results show the efficiency of the circuit is completely consistent with the theory.

Asynchronous Circuit Principles and a Survey of Associated Design Tools

Planning and implementing a semiconductor integrated circuit is a highly complex process. Although physical limits seem to be approaching, it currently follows a growing evolutionary path. As deep submicron technologies evolve towards perhaps even sub-nano geometries, the design process complicates accordingly. Once subtle in higher geometry nodes, some effects become relevant or even dominant. Examples are effects that tamper the reliability of wires, such as crosstalk, or the adequate behaviour of gates, such as the increasing sensitivity to single event effects. Design techniques must thus also evolve, to provide a wide range of tools to deal with new effects during the integrated circuit design and test processes. This tutorial covers one set of design techniques that is often overlooked, but which can reveal themselves instrumental in dealing with the mentioned technology evolution, the use of clockless or asynchronous circuits. The tutorial is divided into three parts: first it introduces a metamodel for the digital circuit design process enabling to reason about distinct design styles; second, it covers the main principles of asynchronous circuit design, differentiating it from mainstream circuit design techniques such as conventional synchronous design; the third and last part presents a set of tools and systems that can be employed to effectively design asynchronous design, with emphasis on material that can be used to produce manufacturable circuits and systems, often associated to commercial integrated circuit synthesis, implementation and test tools and frameworks.

A GaN–Si hybrid integrated driver for narrow-pulse and high-current LiDAR applications

Light detection and ranging (LiDAR) is the most important active remote sensing tool and is widely used in civilian and military fields. There are a number of methods to drive laser diodes; the most common circuit topologies are capacitor-discharge resonant circuits. However, the performance of the silicon (Si)-based switching device limits the development of Light detection and ranging, such as the large figure of merit (FOM) and the stray inductance. Although different methods have been reported to resolve these problems, there are still great challenges in reducing the pressure on Light detection and ranging driver design. Hence, this work presents a gallium nitride (GaN)–Si hybrid integrated driver for a Light detection and ranging system. In the circuit, the switching power device uses GaN instead of a Si-based device, because GaN enables much better performance for pulsed-laser operation due to its near-ideal switching performance. Furthermore, a GaN push–pull driver stage between the GaN power device and the Si-based driver integrated circuit (IC) was innovatively introduced, which is integrated in the same chip with the GaN power device, thereby effectively reducing the parasitic parameters of the signal chain and enhancing the system reliability. The design and implementation of the Si-based IC and GaN IC are based on 0.18 µm 80–120 V Bipolar-CMOS-DMOS (BCD) technology and 0.5 µm p-GaN technology, respectively. The experimental results suggest that the proposed driver circuit output pulse width is 12.6 ns, and it can normally operate at 10 MHz with turn-on/turn-off delay is 11.94 ns. In addition, the driver was capable of generating approximately 8.25 A current pulses through a low ohmic load with a pulse width of approximately 12.4 ns. This work plays a vital role in promoting the development of information equipment and aerospace equipment such as precise ranging, high-efficiency power supplies, and high-speed motors.

Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices

Achieving low-cost and high-performance network security communication is necessary for Internet of Things (IoT) devices, including intelligent sensors and mobile robots. Designing hardware accelerators to accelerate multiple computationally intensive cryptographic primitives in various network security protocols is challenging. Different from existing unified reconfigurable cryptographic accelerators with relatively low efficiency and high latency, this paper presents design and analysis of a reconfigurable cryptographic accelerator consisting of a reconfigurable cipher unit and a reconfigurable hash unit to support widely used cryptographic algorithms for IoT Devices, which require block ciphers and hash functions simultaneously. Based on a detailed and comprehensive algorithmic analysis of both the block ciphers and hash functions in terms of basic algorithm structures and common cryptographic operators, the proposed reconfigurable cryptographic accelerator is designed by reusing key register files and operators to build unified data paths. Both the reconfigurable cipher unit and the reconfigurable hash unit contain a unified data path to implement Data Encryption Standard (DES)/Advanced Encryption Standard (AES)/ShangMi 4 (SM4) and Secure Hash Algorithm-1 (SHA-1)/SHA-256/SM3 algorithms, respectively. A reconfigurable S-Box for AES and SM4 is designed based on the composite field Galois field (GF) GF(((22)2)2), which significantly reduces hardware overhead and power consumption compared with the conventional implementation by look-up tables. The experimental results based on 65-nm application-specific integrated circuit (ASIC) implementation show that the achieved energy efficiency and area efficiency of the proposed design is 441 Gbps/W and 37.55 Gbps/mm2, respectively, which is suitable for IoT devices with limited battery and form factor. The result of delay analysis also shows that the number of delay cycles of our design can be reduced by 83% compared with the state-of-the-art design, which shows that the proposed design is more suitable for applications including 5G/Wi-Fi/ZigBee/Ethernet network standards to accelerate block ciphers and hash functions simultaneously.

Area- and Power-Efficient Reconfigurable Architecture for Multifunction Evaluation

In this paper, we propose an area- and power-efficient reconfigurable architecture for multifunction evaluation based on an optimized piecewise linear (PWL) method. The proposed segmentor automatically divides nonlinear functions into the fewest segments with a predefined maximum absolute error (MAE) and fractional bit width of the slope. In addition, a multiplier was optimized via Booth encoding to reduce the number of rows in the partial product matrix. Compressors were used to shorten the critical path. The results of application-specific integrated circuit (ASIC) implementation reveal that all metrics of the proposed architecture are improved for single functions, without any compromise. Moreover, reconfigurable technology was introduced for implementing multiple functions while reusing computing resources. Compared to a corresponding architecture without reuse, the area and power of this reconfigurable architecture are reduced by 37.48% and 45.60%, respectively, at the same frequency.

A novel voltage-mode universal second-order filter using five single ended OTAs and its quadrature sinusoidal oscillator application

This study proposes a single-ended operational trans-conductance amplifier (SEOTA)-based triple inputs and single output high-input impedance voltage-mode (VM) universal second-order filter. The proposed universal VM SEOTA-based second-order filter can be realized for the non-inverting low-pass, non-inverting high-pass, non-inverting band-reject, non-inverting all-pass and inverting band-pass filtering functions by appropriately using different triple-input voltage signals. The high-input impedances of the proposed universal VM SEOTA-based configuration enable the second-order filter to be cascaded without additional buffers. The proposed configuration does not employ external resistors and accordingly is an active SEOTAs and capacitors (SEOTA-C) universal second-order filter. The proposed circuit using two grounded capacitors which is more apposite to further develop into an integrated circuit implementation. The resonance angular frequency and quality factor are orthogonal electronically adjustable. By slightly modifying the proposed universal VM SEOTA-based second-order filter configuration, the VM SEOTA-C quadrature sinusoidal oscillator is achieved. The oscillation frequency and the oscillation condition of the quadrature sinusoidal oscillator can be independently and electronically tuned by adjusting the bias currents of two SEOTAs. PSpice simulation results confirmed theoretic anticipation. The result of the experiment of the commercially available SEOTAs, LT1228s, are also used to verify the characteristics of the proposed universal VM SEOTA-based second-order filter and VM SEOTA-based quadrature sinusoidal oscillator.

Parallelism Reduction Methods in the High-Level VLSI Synthesis Implementation

The problems and solutions in the field of ensuring architectural independence and implementation of digital integrated circuits end-to-end design processes are considered. The paper focuses on the need to find a solution to the problem of program portability during the development of integrated circuits. A review of the main software and tools used to design digital circuits (Verilog, System-C, Handel-C, Lava, Hydra, Wired, COLAMO, Chisel and etc.) is presented. The method and language of parallel programming for functional flow synthesis of design solutions PIFAGOR is presented. The example of the source and generated code in the PIFAGOR and Verilog languages is given. During the method implementation, the tasks of reducing parallelism and estimating the occupied resources were highlighted. The main feature of the developed method is the introduction of the additional layer (HDL graph) into the synthesis process. Algorithms for the parallelism reduction have been developed. This method is demonstrated on the example of parallelism reduction while going to the FPGA platform solving the problem of calculating a 4-point FFT (Fast Fourier Transform). As part of the solution of this task, an assessment of memory resources and an assessment of computing resources were carried out. The results of software tools development for design support including the parallelism reduction preprocessor and resource estimation preprocessor and practical VLSI projects are presented.