ASIC Implementation of Nonlinear CNN-Based Data Detector for TDMR System in 28 nm CMOS at 200 Mbits/s Throughput

Abstract

In this work, we present the first application-specific integrated circuit (ASIC) implementation of a convolutional neural network (CNN)-based data detection channel for the two-dimensional magnetic recording (TDMR) system in hard disk drive (HDD). This chip is fabricated in TSMC 28 nm complementary metal–oxide–semiconductor (CMOS). TDMR signals captured from a real HDD are used to train and test the network, and the chip is designed to make inferences only. This work presents a systematic pipeline to codesign the neural network structure and the corresponding hardware implementation. To meet the high-throughput requirement, the CNN is fully unrolled with dedicated silicon for each convolution layer using systolic arrays. Quantization-aware training algorithms are used to help improve power efficiency without comprising accuracy. Overall, our chip achieves 200 Mbits/s throughput at 0.9 V supply voltage. In addition, it achieves improved detection accuracy compared to the physical-model-based conventional channel. Our chip consumes 173–219 mW power at 200 M3 clock rate for supply voltage 0.8–0.9 V, respectively.