Impact Of Process Variations Research Articles

An Automated Setup for the Characterization of Time-Based Degradation Effects Including the Process Variability in 40-nm CMOS Transistors

This article reports a test chip design in commercial 40-nm process technology to characterize the level of time-based degradation in metal-oxide-semiconductor field-effect transistors (MOSFETs). The two phenomena that have been concentrated on are the bias temperature instability (BTI) and the hot carrier injection (HCI). Stress tests have been carried out on both n- and p-MOSFETs with large channel widths and shorter channel lengths, as practically observed in analog and radio frequency circuits. Reliability characterization has been extended to cover the body effect and the impact of process variations both at prestress and poststress stages. The results demonstrate that the designed test chip has been instrumental in observing the extent of degradation due to BTI and HCI. Furthermore, both the body effect and the poststress variability have been found to affect the transistor and circuit performance significantly.

Modelling and optimising the impact of process variables on brown rice quality and overall energy consumption

This study aimed to optimise the impact of process variables on brown rice quality (brown rice recovery and head brown rice) and overall energy consumption. The applicability of predictive polynomial regression analysis (PRA) and artificial neural network (ANN) models were evaluated. Process variables [paddy moisture content (12-16%), soaking time (10-16 h), steaming time (20-30 min) and soaking temperature (65-75°C)] were interacted using response surface methodology and their impact on brown rice quality and overall energy consumption were determined. The influence of process variables differs significantly with brown rice recovery and head brown rice. However, a decrease in soaking temperature and paddy moisture content was observed to increase overall energy consumption. ANN shows better predictive accuracy than the PRA model. Optimum conditions that can guarantee maximum quality and minimum overall energy consumption was established at 80°C soaking temperature, 7 h soaking time, 35 min steaming time and 14% paddy moisture content.

Modelling and optimising the impact of process variables on brown rice quality and overall energy consumption

This study aimed to optimise the impact of process variables on brown rice quality (brown rice recovery and head brown rice) and overall energy consumption. The applicability of predictive polynomial regression analysis (PRA) and artificial neural network (ANN) models were evaluated. Process variables [paddy moisture content (12-16%), soaking time (10-16 h), steaming time (20-30 min) and soaking temperature (65-75°C)] were interacted using response surface methodology and their impact on brown rice quality and overall energy consumption were determined. The influence of process variables differs significantly with brown rice recovery and head brown rice. However, a decrease in soaking temperature and paddy moisture content was observed to increase overall energy consumption. ANN shows better predictive accuracy than the PRA model. Optimum conditions that can guarantee maximum quality and minimum overall energy consumption was established at 80°C soaking temperature, 7 h soaking time, 35 min steaming time and 14% paddy moisture content.

Multi-objective optimization on output responses for micro ECM of Al6063 alloy, silicon carbide and boron glass powder metal matrix composites

This study investigates the results of a rate of materials dissolution as well as overcut on aluminium 6063 alloy with reinforcement of silicon carbide and boron glass powder. The tests were performed on micro electrochemical machining (ECM) through taking into account various criteria utilising stainless steel as just a substrate. Experimental runs would be designed for the L9 invariant design utilising the Taguchi optimization grey approach with 3 input variables: applied voltage, chloride ability to concentrate and current. Variability method was done to analyse the impact of process variables on the amount of metal matrix composite materials removal rate (MRR) and overcutting of the substance. In addition to the MRR and overcut, the surface roughness (SR) was used as success metrics within that report. At the end, the optimized values of input process variables are identified from grey relational technique. The optimum value was at run 4.

Statistical Gate-Delay Modeling with Copulas

The growing impact of process variations on circuit performance has become a major concern for deep-submicron integrated circuit design, resulting in numerous SSTA-algorithms. The acceptance of such algorithms in industry however will be dependent on modeling the real silicon behavior in SSTA. This includes that the statistical gate-delay models must consider arbitrary process variations and dependencies. In this paper, we introduce the innovative concept of Copulas to handle this topic. A complete Matlab based framework starting from process parameter statistics up to the computation of the statistical gate-delay distribution is presented. Experimental results demonstrate the importance of accounting realistic process variations.

Statistical gate-delay modeling with copulas

The growing impact of process variations on circuit performance has become a major concern for deep-submicron integrated circuit design, resulting in numerous SSTA-algorithms. The acceptance of such algorithms in industry however will be dependent on modeling the real silicon behavior in SSTA. This includes that the statistical gate-delay models must consider arbitrary process variations and dependencies. In this paper, we introduce the innovative concept of Copulas to handle this topic. A complete Matlab based framework starting from process parameter statistics up to the computation of the statistical gate-delay distribution is presented. Experimental results demonstrate the importance of accounting realistic process variations.

Fabrication of Al6063 alloy, silicon carbide and boron glass powder metal matrix composites in stir casting process and analysis the impact of process variables on mechanical properties

The key purpose of this project is to research the properties of the composite aluminum matrix and to develop the specific properties relative to the contemporary Al 6063 alloys. The mechanical properties of the composites rely on not just the amount of reinforcement material, but also with the dispersion of reinforcement material. Al6063 alloy, strengthened with a blend of silicon carbide (SiC) and boron class powder, known as hybrid composite materials, has been manufactured using the stir casting method. Enhanced at various parameters such as stirring speed, processing temperature, reinforcing preheats temp and percentile adding of SiC (6%, 11% and 16%) by the Taguchi tool L 9 Orthogonal level. Its matrix composites reliability of the molded composites was calculated utilizing a computer controlled universal test system and a Brinell hardness analyzer to assess its ultimate tensile strength, tensile yield strength and Brinell hardness number. Adequate Brinell hardness number, ultimate tensile strength and tensile yield strength was identified under the impact of stirring speed, processing temperature, reinforcing pre-heat temp as well as % addition of SiC. Regression models have been developed using Minitab 19 software for prediction. Eventually, the confirmatory examination was conducted to validate the experimental findings. This matrix reinforcement material can be used to produce trusses, frames also tins used to hold medicines, dairy as well as other toxic fluids, and it can be substituted by stainless steel used for a saline atmosphere to prevent corrosion.

Abstract 372: Regional Cerebral Saturation in a Swine Model of Goal-directed Resuscitation of Prolonged Ventricular Fibrillation Cardiac Arrest

Introduction: The characteristics and limitations of near-infrared spectroscopy (NIRS) measurement of regional cerebral saturation (rSO2) for reflecting key moment-to-moment physiological changes needed to guide cardiopulmonary resuscitation (CPR) have yet to be fully determined. Objective: Examine the impact of NIRS sensor placement and resuscitation process variation on rSO2 measurements during prolonged cardiac arrest. Methods: Thirty mixed-breed domestic pigs (mean weight: 25.0kg+/-2.0) were sedated (ketamine / xylazine), anesthetized (fentanyl), paralyzed (vecuronium) and mechanically ventilated. Micromanometer pressure transducers were placed in the aorta and right atrium via femoral cutdown to measure central pressures, including mean arterial pressure (MAP) and coronary perfusion pressure (CPP). Two NIRS sensors were placed on the cranium: one on the skin surface and one on the bare skull. Ventricular fibrillation was induced electrically and untreated for 8 minutes followed by CPR. Initial BLS phase: 4 minutes of CPR at 100 compressions per minute (CPM) and 2 inches depth with manual ventilations (30:2). Randomized ALS phase: CPR with a pressor-titrated (Group A) or a compression rate/depth-titrated (Group B) strategy targeting 25mmHg CPP. Group A animals received pressor doses q1min and fixed rate/depth CPR. Group B animals received increasing rates and depth of CPR with epinephrine q3min. Defibrillation was attempted at 6min CPR q2min. rSO2 was compared between skin and skull across phases of resuscitation with t-tests and generalized estimating equations (GEE). Results: Mean skin and skull rSO2 differed marginally overall (63.8 vs 62.0, p < 0.001), at baseline (69.9 vs 64.9, p < 0.001), during BLS CPR (56.9 vs 48.7, p < 0.001), during ALS CPR (59.5 vs 51.0, p < 0.001), and following ROSC (70.0 vs 60.5, p<0.001). rSO2 measured on either skull or skin both varied throughout phases of the experiment but not between CPR groups. In GEE models, rSO2 measured on skin or skull was not associated with MAP at baseline, but was directly associated during BLS (coef 0.13; p<0.001) & ALS CPR (coef 0.09; p<0.001), and after ROSC (coef 0.02; p=0.017). Conclusion: rSO2 measures differ between skin and skull though both correlate with MAP.

RF Analysis of Double-Gate Junctionless Tunnel FET for Wireless Communication Systems: A Non-quasi Static Approach

The optimum and acceptable combination of control gate (CG) process parameters, such as dielectric materials, thickness, and metal work function for a double-gate junctionless tunnel field-effect transistor, remain a subject of great interest among researchers. We report here on the significant impact of CG process variations on the radio-frequency (RF) parameters of this device structure. Studies carried out using a non-quasi-static model with CG process variations have been analyzed for current gain (h21) and unilateral power gain with the help of a Silvaco Atlas device simulator. Systematic investigations reveal that the combination of CG process parameters, such as dielectric material (SiO2) with the thickness of 2 nm and CG metal (aluminum-〈100〉), provide the optimum RF characteristics, i.e., fT (2.9 GHz) and fmax (15 GHz), while maintaining the switching ratio (0.161 × 109), intrinsic capacitances (Cgg = 0.7 fF), and transconductance (3.8 μS) at the bias conditions of Vgs (1 V) and Vds (1 V). The results have been thoroughly interpreted from energy band diagrams and the associated band-to-band tunneling rate. The studies reported here may prove to be useful for further exploring the use of the suggested device structure for Internet of Everything communications and other related applications.

Circuit design using Schmitt Trigger to reliability improvement

This paper presents a design strategy to reduce the impact of process variations and soft error susceptibility in FinFET circuits. The mitigation is provided by connecting a Schmitt Trigger at the logic gate output. The improvements in power and delay variability can reach up to 32.6% and 42.1%, respectively, with logic cells almost immune to soft error even at the near-threshold regime. When compared with other circuit-level methods such as sleep transistor, decoupling cells, and transistor reordering, on average, the Schmitt Trigger technique is at least 6%, 8%, and 10.5% more robust to process variability, respectively.

MacLeR: Machine Learning-Based Runtime Hardware Trojan Detection in Resource-Constrained IoT Edge Devices

Traditional learning-based approaches for run-time Hardware Trojan detection require complex and expensive on-chip data acquisition frameworks and thus incur high area and power overhead. To address these challenges, we propose to leverage the power correlation between the executing instructions of a microprocessor to establish a machine learning-based run-time Hardware Trojan (HT) detection framework, called MacLeR. To reduce the overhead of data acquisition, we propose a single power-port current acquisition block using current sensors in time-division multiplexing, which increases accuracy while incurring reduced area overhead. We have implemented a practical solution by analyzing multiple HT benchmarks inserted in the RTL of a system-on-chip (SoC) consisting of four LEON3 processors integrated with other IPs like vga_lcd, RSA, AES, Ethernet, and memory controllers. Our experimental results show that compared to state-of-the-art HT detection techniques, MacLeR achieves 10\% better HT detection accuracy (i.e., 96.256%) while incurring a 7x reduction in area and power overhead (i.e., 0.025% of the area of the SoC and <0.07% of the power of the SoC). In addition, we also analyze the impact of process variation and aging on the extracted power profiles and the HT detection accuracy of MacLeR. Our analysis shows that variations in fine-grained power profiles due to the HTs are significantly higher compared to the variations in fine-grained power profiles caused by the process variations (PV) and aging effects. Moreover, our analysis demonstrates that, on average, the HT detection accuracy drop in MacLeR is less than 1% and 9% when considering only PV and PV with worst-case aging, respectively, which is ~10x less than in the case of the state-of-the-art ML-based HT detection technique.

Development in plasma arc welding process: A review

Plasma arc welding process has found wide application for joining of metals in manufacturing industries in the recent times. It has become the preferable welding process over other arc welding processes since it possesses increased welding speed, produces better weld quality, and has less impact of process variability on the process performance. A lot of advancement has taken place to enhance the stability of the plasma arc welding process, increase the depth of penetration and weld quality in recent years. The process is more preferred for welding of similar materials owing to the formation of stable, controlled, and constricted arc with low current requirements. It gives longer electrode life for high production. Variable polarity plasma arc welding (VPPAW) process, Pulsed plasma gas welding (PPGW), Double pulsed plasma arc welding (DPPAW) processes are widely used for joining the mid-thick steels (9.5 mm–12.5 mm). Pulsed plasma gas welding process helps to improve the process stability and the weld quality than other VPPAW process. Apart from these process Laser assisted Plasma arc welding, PAW-MIG hybrid welding, plasma spot welding, soft plasma arc welding process are some of the advancements to the PAW processes which are used for special industrial application. The present review paper focuses on the evolution and the development of the plasma arc welding process, its types, and the suitability of the process towards various applications in the manufacturing industries.

Impact of Process Variability on Write Error Rate and Read Disturbance in STT-MRAM Devices

Spin-transfer torque magnetic random-access memory (STT-MRAM) is the most promising next-generation memory technology that combines the advantages of mainstream memory technologies, such as SRAM, DRAM, and flash. In the STT-MRAM, a magnetic tunnel junction (MTJ) is used as a bit-cell to store the data, and its magnetic properties have a critical role in thermal noise-aware STT-switching operations. This work analyzes the impact of MTJ material and geometric parameter variations, such as saturation magnetization (MS), magnetic anisotropy (HK), damping factor (α), spin polarization efficiency factor (η), oxide thickness (tOX), free layer thickness (tF), tunnel magnetoresistance (TMR), and cross-sectional area of free layer (AF) variations on write error rate (WER) and read disturbance rate (RDR) for reliable write and read operations, respectively. To evaluate the scalability of MRAM devices, we investigate both WER and RDR with a wide range of MTJ diameters between 90 and 30 nm, which corresponds to mainstream technology nodes from 40 up to 14 nm advance node. In our work, the Fokker-Planck (FP) numerical approach is mainly utilized for an efficient analysis, which allows for parametric variation and evaluates its impact on switching. Although the impact of material and geometric parameter variations on WER is decreased as MTJ scales down from 90 to 30 nm, the variation effect can be still critical with small MTJ diameter, and the most significant influential variation is η, MS, HK, and α in that order. By contrast, the impact of material and geometric parameter variation on RDR increases in MTJ scaling, and we show that negative variations of HK and MS could be a critical bottleneck in 30 and 40 nm MTJ diameters. Our work finally emphasizes the necessity of the WER and RDR analysis by considering the parameter variation in MTJ scaling for practical STT-MRAM development.

Optimization for free glycerol, diglyceride, and triglyceride reduction in biodiesel using ultrafiltration polymeric membrane: Effect of process parameters

Membrane purification technique as an environmental-friendly process to the conventional biodiesel water washing should not only achieve high purified biodiesel but also should be feasible from an economic perspective. Consequently, a better comprehension of the process parameters on different impurities is a vital requirement for optimizing the membrane separation process for biodiesel purification. To achieve this aim, commercial PolyVinyliDene Fluoride (PVDF) membrane with 100 kDa molecular weight cut-off was used for the ultrafiltration of crude biodiesel. Response surface methodology (RSM) was applied to study the impact of process variables including temperature, transmembrane pressure, and water addition on free glycerol, diglyceride, and triglyceride reduction as well as permeate flux as responses. Simultaneous reduction of mentioned impurities to the limits imposed by international standards achieved at pressures lower than 2 bars and temperatures lower than 30 °C with a low permeate flux of 20 kg/m2.hr. This low permeate flux can be an obstacle to the commercial consumption of biodiesel. This low permeate flux is due to the limitation of triglyceride impurity in the biodiesel imposed by EN 14214 standards.

Advanced imaging techniques to understand the impact of process variables on the particle morphology in a corn stover pellet

The objective of this study is to understand the impact of process variables on particle binding during corn stover pelleting. Initial particle attrition or percent fines <425 μm in 1/4-in. (6.35 mm) and 7/16-in. (11.11-mm) hammermill screen size was measured at 34.36% and 20.24%, respectively. A single pellet press was used to do the pelleting tests by varying the hammermill screen size (1/4-in. [6.35 mm] and 7/16-in. [11.11 mm]), corn stover moisture (10, 15, and 20%, w.b.), and residence time (45, 90, 120 and 150 s). The pellet properties measured were the particle dimensions (e.g., geometric mean particle length, d10, d50, and d90 [mm]), percent fines (e.g., <425μm), and unit density (e.g., kg/m3). Results indicated that both hammermill grind sizes impacted the pellet properties. Residence time, corn stover moisture content, and hammermill screen size all influenced the percent fines in the corn stover pellets. At 10% (w.b.) corn stover moisture content and a 150-s residence time, the maximum percentage of fines observed was about 26% for a 6.35-mm and about 16–17% for a 11.11 mm hammermill screen size grind. The pelleting process conditions also influenced the particle dimensions (e.g., geometric mean particle length, d10, d50, and d90 [mm]). At lower residence times of 45 s for both 1/4- and 7/16-in. (6.35 and 11.11 mm) hammermill screen size grind pellets, the fines in the corn stover pellets were minimized. In the case of corn stover moisture content, about 10–15% (w.b.) minimized percent fines and unit density was maximized at 150-s residence time for both the grind sizes that were tested. X-ray CT-scan analysis indicated that the agglomerate size, shape, and surface area are influenced by both corn stover moisture content and residence time. Focused ion beam tomography showed a lamellar structure with voids, which might have formed due to weak adhesion between the particles.

CPAmap: On the Complexity of Secure FPGA Virtualization, Multi-Tenancy, and Physical Design

With virtualized Field Programmable Gate Arrays (FPGAs) on the verge of being deployed to the cloud computing domain, there is a rising interest in resolving recently identified security issues. Those issues result from different trusted and untrusted entities sharing the FPGA fabric and the Power Distribution Network. Researchers were able to perform both side-channel and fault attacks between logically isolated designs on the same FPGA fabric, compromising security of cryptographic modules and other critical implementations. Side-channel attacks specifically are enabled by the vast degree of freedom given to developers when making use of the basic FPGA resources. Both ring oscillators as well as long delay lines, implemented using low-level FPGA primitives, have been shown to provide sufficient data for simple or correlation-based power analysis attacks. In order to develop new or apply known countermeasures onto designs and implementations in a virtualized multi-tenant FPGA, we seek to fully understand the underlying mechanisms and dependencies of chip-internal side-channel attacks. Although the impact of process variation and other physical design parameters on side-channel vulnerability has been investigated in previous works, remote attacks between logically isolated partitions in multi-tenant FPGAs introduce new and unique challenges. Thus, we systematically analyze the impact of physical mapping of both attacker and victim design on the success of correlation power analysis attacks on the Advanced Encryption Standard (AES). We report our findings on a Xilinx Zynq 7000-based platform, which show that the effect of global and local placement as well as routing and process variation on the success of side-channel attacks almost exceeds the impact of hiding countermeasures. This result reveals fundamental challenges in secure virtualization of FPGAs, which have been mostly ignored so far. Eventually, our results may also help vendors and hypervisors in developing zero overhead side-channel countermeasures based on adequate global and local placement of isolated designs on a multi-tenant FPGA.

Gate Sizing Methodology with a Novel Accurate Metric to Improve Circuit Timing Performance under Process Variations

The impact of process variations on circuit performance has become more critical with the technological scaling, and the increasing level of integration of integrated circuits. The degradation of the performance of the circuit means economic losses. In this paper, we propose an efficient statistical gate-sizing methodology for improving circuit speed in the presence of independent intra-die process variations. A path selection method, a heuristic, two coarse selection metrics, and one fine selection metric are part of the new proposed methodology. The fine metric includes essential concepts like the derivative of the standard deviation of delay, a path segment analysis, the criticality, the slack-time, and area. The proposed new methodology is applied to ISCAS Benchmark circuits. The average percentage of optimization in the delay is 12%, the average percentage of optimization in the delay standard deviation is 27.8%, the average percentage in the area increase is less than 5%, and computing time is up to ten times less than using analytical methods like Lagrange Multipliers.

Design Exploration of Energy-Efficient Accuracy-Configurable Dadda Multipliers With Improved Lifetime Based on Voltage Overscaling

This article investigates an energy-efficient accuracy-configurable Dadda (X-Dadda) multiplier. The structure employs the voltage overscaling and approximate width setting as the approximation knobs for improving the energy consumption as well as the reliability and lifetime of the multiplier. While the former may be set in the design time as well as the runtime, the latter may only be invoked in the design time. For a given accuracy level, the partial product columns and the overscaled voltage for optimizing the energy are determined. Normally, to have the error within a tolerable limit, the voltage overscaled columns are those at lower bit significances which have higher switching activities. The structure makes use of a low number of level shifters for a low-overhead realization. The approximate columns which start from the first column are contiguous. To further improve the efficiency of the multiplier, four-bit truncation of the multiplier output is also suggested. The efficiency of the X-Dadda structure is investigated using a 15-nm FinFET technology. The results indicate that, for example, when the approximate mode with the mean relative error distance (MRED) of 0.11 is considered, up to 43% energy saving is achieved. In addition, for this case, the Bias temperature instability (BTI)-induced delay degradation of the multiplier decreases up to 9.9% compared to 50% in the case of the exact mode. Also, the impact of process variations on the accuracy of the X-Dadda is studied. Finally, the efficacy of the X-Dadda multiplier, when used in neural networks for image classification and image-processing applications, is assessed.

Design and Analysis of Leakage-Induced False Error Tolerant Error Detecting Latch for Sub/Near-Threshold Applications

The digital designs operating in sub/near-threshold region are susceptible to timing errors due to the extreme impact of process, voltage, and temperature (PVT) variations. This paper proposes a new error-detecting latch (EDL) to mitigate the impact of PVT variations. The proposed EDL is a single-phase clocked design, which significantly reduces the clock power consumption of the design. The proposed EDL follows a merged and shared architecture of two latches along with an XNOR gate, which leads to a compact layout of EDL. The post-layout simulations in an industrial 28 nm CMOS technology node, show a minimum clock power savings of 31%, average power savings of 16%, and reduction in leakage power by 23% in comparison to the state-of-the-art EDLs at 0.4 V. The 10K rigorous Monte-Carlo simulations across the supply voltage range of 0.23 V - 0.8 V and clock frequency range of 1.6 MHz - 70 MHz shows that the proposed EDL is tolerant to leakage-induced false errors and glitches. SSEDL is robust to process variations even with minimum-sized transistors.

Analysis of the Impact of Process Variations and Manufacturing Defects on the Performance of Carbon-Nanotube FETs

Carbon-nanotube FETs (CNFETs) are potential successors to CMOS transistors; these emerging devices have a low intrinsic delay due to near-ballistic transport in carbon nanotubes (CNTs). As CNFETs are evaluated for circuit/system design, it is important to analyze variations in CNT process parameters. In this article, we present a systematic approach to quantify the impact of these imperfections on the transistor- and gate-level performances of CNT-based circuits. Process variations are investigated to identify the critical device parameters that have maximum impact on the device on-current. We also present a model that predicts the realistic CNFET yield in the presence of process variations. Finally, the impact of manufacturing defects, such as pinholes in the gate dielectric and parasitic CNFETs formed due to imperfect etching, are modeled and evaluated using HSPICE.