Impact Of Line Edge Roughness Research Articles

Influence of line edge roughness in optical critical dimension metrology

We present the impact of line edge roughness (LER) on the optical critical dimension (OCD) metrology of nanostructures. The consideration of LER in OCD requires numerically expensive forward models and is therefore usually neglected. We present an analytical approach that allows estimation of the impact on the uncertainty. Systematic differences between CD measured by SEM and OCD were observed in different experiments. While SEM is basically sensitive to the local volume density, optical methods are sensitive to the permittivity of the material. We discuss an analytical upper bound on the contribution of the LER. For high index gratings, the contribution is as high as 3.7 nm for TM-polarized light and 1.2 nm for TE-polarized light, making this crucial for sub-nanometer metrology.

A machine learning approach to model the impact of line edge roughness on gate-all-around nanowire FETs while reducing the carbon footprint.

The performance and reliability of semiconductor devices scaled down to the sub-nanometer regime are being seriously affected by process-induced variability. To properly assess the impact of the different sources of fluctuations, such as line edge roughness (LER), statistical analyses involving large samples of device configurations are needed. The computational cost of such studies can be very high if 3D advanced simulation tools (TCAD) that include quantum effects are used. In this work, we present a machine learning approach to model the impact of LER on two gate-all-around nanowire FETs that is able to dramatically decrease the computational effort, thus reducing the carbon footprint of the study, while obtaining great accuracy. Finally, we demonstrate that transfer learning techniques can decrease the computing cost even further, being the carbon footprint of the study just 0.18 g of CO2 (whereas a single device TCAD study can produce up to 2.6 kg of CO2), while obtaining coefficient of determination values larger than 0.985 when using only a 10% of the input samples.

Enabling Wavelength-Dependent Adjoint-Based Methods for Process Variation Sensitivity Analysis in Silicon Photonics

To reach its potential as an emerging technology platform, integrated silicon photonics needs accompanying design-for-manufacturability (DFM) methods and tools to assist the design of silicon photonic devices and circuits. Here, we explore spatial sampling in adjoint-based methods for analysis of the sensitivity of photonic components against key fabrication process variations. We apply and test these spatial sampling adjoint analysis methods to examine the impact of line edge roughness (LER) on a passive Y-branch at a given operating wavelength, achieving about 3% relative error. We extend the approach to also study LER variation sensitivity across a range of wavelengths and validate our results with ensemble virtual fabrication and FDTD simulations. The adjoint sensitivity and variance estimation of Y-branch transmission imbalance is seen to be highly efficient in comparison to direct ensemble simulation, with consistent results in the 95% confidence interval.

Line-Edge Roughness on Fin-Field-Effect-Transistor Performance for 7-nm and 5-nm Patterns.

The line-edge roughness (LER) is a critical issue that significantly impacts the critical dimension (CD) because the LER does not scale with the feature size. Hence, the LER influences the device performance with 7-nm and 5-nm patterns. In this study, LER impact on the performance of the fin-field-effect-transistors (FinFETs) are investigated using a compact device method. The fin-width roughness (FWR) is based on the stochastic fluctuation such as the LER and the line-width roughness (LWR) in the lithography process. The calculated results of the FWRs and the gate lengths L = 7-nm and 5-nm are addressed with the cases of electric potentials with the y-direction along the gate length, electric potentials with the x-direction along the fin width, and the absolute drain currents with the gate lengths L = 7-nm or 5-nm due to gate voltages. According to the gate length, the impact of the FWR patterns on the performance of fin-field-effect-transistors (FinFETs) can find regular fluctuations.

Comparison of LER Induced Mismatch in NWFET and NSFET for 5-nm CMOS

Nanosheet field-effect transistors (NSFETs) have emerged as a novel device replacement for sub-7nm CMOS technology nodes. However, due to smaller fin thickness (Tfin = 5nm), NSFETs are more vulnerable to the process-induced variations. Among various types of process-induced variations, Line edge roughness (LER) is becoming a significant concern for multi-gate field-effect transistors (MugFETs) with smaller feature sizes. In this article, we have reported and compared the impact of LER on the electrical characteristics of NSFETs and nanowire field-effect transistors (NWFETs) for the sub-7nm technology node. We have generated a 3-D LER profile using 2-D Auto Covariance Function (ACVF) that considers two degrees of freedom for a realistic roughness analysis at advanced CMOS technology nodes. For a complete study of 3-D LER effect in NSFET, we have considered roughness along the nanosheet’s sidewalls as well as top and bottom surfaces. We have shown using 3D TCAD simulations that the sidewall roughness in NSFETs contributes to a negligible mismatch in threshold voltage and ON current. The mismatch performance of NSFET is compared with that of the NWFET for sub-7nm technology node. NSFET appears to be more immune to mismatch in ON current than NWFETs considered in this work. On the other hand, as compared with NSFET, owing to its superior gate all-around control, the NWFET achieves lower mismatch in drain induced barrier lowering (DIBL) and subthreshold slope (SS) in presence of LER. In addition to this, FETs with different channel doping modes such as inversion (IM) and Junction less (JL) mode have been compared for their matching performance against 3-D LER. It can be concluded from the results that IM FETs are more immune to 3-D LER as compared to JL FETs.

Study of line edge roughness on various types of gate-all-around field effect transistor

The impact of line edge roughness (LER) on gate-all-around FETs (GAAFETs) with various channel types is investigated. Among various channel types of GAAFET, (i) nanowire (NW), (ii) nanosheet (NS), and (iii) stacked channel are investigated. Considering the Si/SiGe stacking and selective etching process (which is commonly used to release the channel of GAAFET), we modeled the LER profile for channels. Moreover, 3D LER modeling is adopted to represent the LER profile in non-planar device structure. It turned out that the NS channel GAAFET has not only higher on-state drive current but also better performance variation immunity than the NW channel GAAFET. This is because the aspect ratio of channel affects the LER profile. Compared against single-channel GAAFET, the stacked channel GAAFET has better variation immunity because of its complementary effect in-between stacked channels. To investigate the impact of complementary effect, we simulated two different stacked channels, one of which has no correlation between stacked channels, and the other of which has the correlation induced from the channel-releasing processing step. It turned out that the stacked channel GAAFET with no correlation in-between the channels can have better variation-robustness.

Source/Drain Engineered Charge-Plasma Junctionless Transistor for the Immune of Line Edge Roughness Effect

In this paper, the charge-plasma structure over the source/drain region is incorporated into a dopingless junctionless transistor for obtaining the superior immunity of line edge roughness (LER). An optimized on/off current ratio is observed by using numerical simulations. It is also demonstrated that the proposed charge-plasma junctionless transistor (CP-JLT) is insensitive to the variation of LER magnitude. We further reveal the physics that LER affects the electrical characteristics of CP-JLT. Channel minimal width position variation and channel width variation are put forward to explore the impact of LER for the first time. It is observed that the LER affects the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> of CP-JLT due to the changes of the source width caused by channel minimal width position variation, whereas the LER affects the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> , SS, and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> mainly through channel width variation. It is thus proved to be a helpful guide to suppress the LER variation of CP-JLT.

Impact of line edge roughness on the performance of 14-nm FinFET: Device-circuit Co-design

With the evolution of sub-20 nm FinFET technology, line edge roughness (LER) has been identified as a critical problem and may result in critical device parameter variation and performance limitation in the future VLSI circuit application. In the present work, an analytical model of fin-LER has been presented, which shows the impact of correlated and uncorrelated LER on FinFET structure. Further, the influence of correlated and uncorrelated fin- LER on all electrical performance parameters is thoroughly investigated using the three-dimensional (3-D) Technology Computer Aided Design (TCAD) simulations for 14-nm technology node. Moreover, the impact of all possible fin shapes on threshold voltage (VTH), drain induced barrier lowering (DIBL), on-current (ION), and off-current (IOFF) has been compared with the well calibrated rectangular FinFET structure. In addition, the influence of all possible fin geometries on the read stability of six-transistor (6-T) Static-Random-Access-Memory (SRAM) has been investigated. The study reveals that fin-LER plays a vital role as it directly governs the electrostatics of the FinFET structure. This has been found that there is a high degree of fluctuations in all performance parameters for uncorrelated fin-LER type FinFETs as compared to correlated fin-LER with respect to rectangular FinFET structure. This paper gives physical insight of FinFET design, especially in sub-20 nm technology nodes by concluding that the impact of LER on electrical parameters are minimum for correlated LER.

Effective–CD: a contribution toward the consideration of line edge roughness in the scatterometric critical dimension metrology

We present an overview of our research on the relation between line edge roughness (LER) and optical critical dimension metrology (OCD). Referring to a known fact that LER does have an impact on OCD, we discuss a novel approach that allows for its better understanding. Namely, we show that, in the presence of LER, one can observe a characteristic scatterometry-measured CD offset, which we call effective–CD. The fact that the effective–CD is characteristic renders it to be a good means of accessing the information about LER present on the CD. To assure the completeness of this overview, we begin by reviewing some previously published results, which have drawn our attention and first led us to observing the characteristic influence of LER on a CD measurement. Next, we extend our model-based simulations to confirm the presence of the effective–CD for complex-roughness models, and finally, we demonstrate an experimental verification of our effective–CD hypothesis. We are convinced that our approach will help to better understand the impact of LER on a CD measurement and will be considered a useful contribution to the development of measurement methods for challenging scenarios, in which realistic CD is affected by the presence of LER.

Impact of Short-Wavelength and Long-Wavelength Line-Edge Roughness on the Variability of Ultrascaled FinFETs

We examine the impact of line-edge roughness (LER) on the variability in the on-current and saturation threshold voltage of ultrascaled FinFET devices via quantum-mechanical transport simulation. We obtain a realistic model of LER by decomposing the LER into short- $\lambda $ and long- $\lambda $ fluctuations, and we consider their separate influences on device performance. We show that the long- $\lambda $ fluctuations lead to greater device variability than the short- $\lambda $ fluctuations, and we explain the difference between the two cases via the influence of fluctuating quantum confinement arising from the LER. Finally, we consider devices in which the long- $\lambda $ fluctuations of the two fin edges are correlated and demonstrate that this correlation significantly improves the variability. Thus, we show the continued need for fabrication technology either to reduce the amplitude of the long- $\lambda $ fluctuations or to ensure the long- $\lambda $ fluctuations between the sidewalls of ultrascaled FinFET devices are correlated.

3-D Quasi-Atomistic Model for Line Edge Roughness in Nonplanar MOSFETs

As the physical sizes of devices have been scaled down, the negative impact of process-induced random variation on device performance has increased; therefore, there is an urgent demand for advanced simulation methods for variation. In this paper, a 3-D quasi-atomistic simulation methodology for line edge roughness (LER) in nonplanar devices, such as FinFETs and gate-all-around (GAA) FETs, is proposed. In addition, a simple gate oxide layer model is proposed to analyze the impact of LER on device performance while excluding the impact of oxide thickness variation. To verify the importance of the quasi-atomistic 3-D LER model and to compare the LER-induced performance variation in a FinFET to that in a GAA FET, the case studies using the 3-D quasi-atomistic LER model for FinFETs and GAA FETs are performed.

Impact of different stochastic line edge roughness patterns on measurements in scatterometry - A simulation study

Abstract The impact of line edge roughness (LER) on measured light diffraction pattern of photo masks is investigated. This is relevant for scatterometry as an accurate, indirect method in wafer metrology to determine geometry parameters of periodic surface structures from scattered light intensities. The sensitivity to roughness increases the smaller the wavelength of the incident light is. For EUV scatterometry at 13.5 nm, the efficiencies of many higher diffraction orders can be measured. In the nanometer range they are sensitive to deviations from the ideal periodic straight line structure such as LER. Applying the Fraunhofer approximation, we calculate the far field diffraction pattern of an illuminated 2D aperture plane composed of many rough slits by its 2D-Fourier transform. The rough edges of the aperture gaps are created by means of power spectrum density (PSD) functions used with a random complex exponential phase term. A simple theory neglecting correlation in the roughness profile predicts for the intensities an exponential decrease with the diffraction order and the standard deviation of the roughness amplitude which can be tested by our numerical solutions. The calculated light intensities for a rough aperture are compared with the ones found for an ideal periodic aperture whose edges are straight lines. Ensembles of rough apertures with different values for the imposed standard deviation of the roughness amplitude σ , the linear correlation length ξ , and the roughness exponent α were examined. The validity of the exponential decrease was investigated for correlation lengths ξ from 5 nm up to 1000 nm and roughness exponents α from 0.3 to 1.0. It was found that the results for the exponential correction factor deviate substantially from the mentioned theoretical value for large correlation lengths and small roughness exponents.

Device- and Circuit-Level Variability Caused by Line Edge Roughness for Sub-32-nm FinFET Technologies

The variability impact of line edge roughness (LER) on sub-32-nm fin-shaped FET (FinFET) technologies is investigated from both device- and circuit-level perspectives using computer-aided design simulations. Resist-defined FinFETs exhibit sizeable device performance variation (up to 10% fluctuation in threshold voltage and 200% in leakage current) when subjected to fin roughness up to 1 nm root-mean-square amplitude. Spacer-defined FinFETs show negligible device performance variation and exhibit quadratic dependence with LER amplitude. For both patterning technologies, the resulting impact on large-scale digital-circuit performance variation is found to be minimal in terms of the overall delay mean and variation. This is attributed to self-averaging of uncorrelated LER effects between individual devices within the circuits, resulting in minimal delay impact for digital-circuit design. The impact of LER on leakage power variation is also found to be minimal for all technologies; however, the mean value increases by up to 40% for 15-nm resist FinFETs. On this basis, the impact of LER on sub-32-nm FinFET device-level variability is only significant for resist devices, whereas the resulting digital-circuit impact is important only in terms of mean leakage power increase.

Linking EUV lithography line edge roughness and 16nm NAND memory performance

Resist roughness is one of the effects of process uncertainties in extreme UV lithography. All the lithographic elements, such as source, mask, optical system, resist and metrology, contribute to line roughness. As a result, line edge roughness is still a challenge to be tackled for 22 and 16nm transistor devices. In this paper, the impact of post-litho smoothing processes such as ion-beam implant and plasma etch treatment on state-of-the-art extreme UV lithography is reported. Top-down and cross section electron microscopy were used to evaluate low and high frequency components of line edge roughness by means of power spectral density analysis. To compute roughness impact on bit error rate performance of floating gate devices, line edge profiles were first rebuilt, and then injected into a Monte Carlo variability aware simulator for electrical evaluation of a 16nm multi-level NAND Flash memory array. Electrical variability simulations based on actual experimental roughness profiles were executed to quantify the impact of line edge roughness on the device reliability. It was found that inter-transistor low frequency roughness impacts the memory performance with a failure factor 3-5 times higher compared to the same electrical model without considering any stochastic variation. Intra-transistor high frequency roughness showed only a marginal effect compared inter-transistor variations. Moreover, it was demonstrated that the bit error rate exponentially depend on resist line edge roughness. Finally, by combining both experimental analysis and electrical assessment, it was possible to quantify the contribution of post-litho smoothing processes on the error correction code performance for such memory devices.

Variability of Inversion-Mode and Junctionless FinFETs due to Line Edge Roughness

We investigated the variability impact of line edge roughness (LER) on standard inversion-mode (IM) and junctionless FinFETs (JL-FinFET) designed for the 2009 ITRS high-performance logic 32-, 21-, and 15-nm nodes using technology computer-aided design simulations. Fluctuations in threshold voltage, drive current, leakage current, subthreshold swing, and drain-induced barrier lowering were found to be significantly worse in junctionless devices compared to IM devices at root-mean-square LER amplitudes up to 1 nm. We invoke a simple physical argument to explain these findings based on the operating principles of IM and junctionless devices and the specific means by which LER affects both device architectures. Our findings show that JL-FinFETs are inherently more sensitive to variability than standard IM devices and will pose significant challenges as a feasible post-CMOS technology.

A Comprehensive LER-Aware TDDB Lifetime Model for Advanced Cu Interconnects

A time-dependent dielectric breakdown (TDDB) lifetime model predicting the impact of line-edge roughness (LER) on Cu interconnect reliability is proposed. The structure, validity, and accuracy of the model are evaluated and discussed. The model is applied to an interconnect scaling scenario that includes conventional patterning and spacer-defined patterning of nanometer-scale Cu wires. LER-aware TDDB lifetime predictions are obtained from the model, and consequent recommendations on how to improve the TDDB lifetime of future interconnects are derived.

Variability Induced by Line Edge Roughness in Double-Gate Dopant-Segregated Schottky MOSFETs

Intrinsic parameter fluctuations introduced by process variations, such as line edge roughness (LER), create an increasing challenge to the CMOS technology scaling. In this paper, variations in double-gate dopant-segregate Schottky (DSS) MOSFETs, caused by LER of silicon-fin, are systematically investigated using statistical technology computer-aided design simulations. The impact of LER on both Schottky barrier and DSS-MOSFETs are examined contrastively. The results show that DSS-MOSFETs offer a larger and more uniform drive current, but suffer a more serious Vt fluctuation. The cause of such larger Vt flutuation is also analyzed, thus providing a good starting point to propose way to solve this problem.

Matching Performance of FinFET Devices With Fin Widths Down to 10 nm

In this letter, the matching performances of FinFET devices with high-k dielectric, metal gates, and fin widths down to 10 nm are experimentally analyzed. The stochastic variation of threshold voltage and current factor is examined for both p- and n-type FinFETs. An improvement of the matching performance is expected compared to conventional planar bulk devices since the fins are undoped. The impact of line edge roughness and charge density in the high-k dielectric is evaluated in order to understand which physical parameter fluctuation is dominant on the measured matching parameters.

Fin shape fluctuations in FinFET: Correlation to electrical variability and impact on 6-T SRAM noise margins

Threshold voltage ( V T ) and drive current ( I ON ) variability of low stand-by power (LSTP)-32 nm FinFETs subject to fin line-edge roughness (LER) is investigated through Technology Computer-Aided Design (TCAD) simulations featuring quantum-corrected hydrodynamic transport. Statistical results provided by an ensemble Monte Carlo (MC) approach highlight an increase in the average V T and a decrease in the average I ON with respect to sensitivity analysis based predictions. Correlations of fin shape fluctuations to electrical performance are investigated, thus assessing further limitations of sensitivity analysis and proposing better alternatives to the expensive MC approach. An equivalent fin width is calculated, which allows reducing the spread in I ON scatter plots and highlights relative importance of LER in different fin regions. Simplified device instances with linearly varying fin width are simulated to better assess the impact of local thinning/thickening in the channel, source and drain extensions. Asymmetries in the device behavior are observed upon swapping the taper direction and the critical role of extensions is identified. Moreover, the impact of LER on noise margins of FinFET-based Static Random Access Memories (SRAMs) is investigated, considering the hold, read and write operating modes. Results are compared to published data on fabricated cells with similar device features. “ μ - 6 σ ” statistics extracted from 1000 mixed-mode simulations helps with assessing variability concerns for mainstream integration of aggressively scaled of FinFET-SRAMs.

Impact of Line-Edge Roughness on Double-Gate Schottky-Barrier Field-Effect Transistors

The impact of line-edge roughness (LER) on double-gate (DG) Schottky-barrier field-effect transistors (SBFETs) in the level of device and circuit was investigated by a statistical simulation. The LER sequence is statistically generated by a Fourier analysis of the power spectrum of the Gaussian autocorrelation function. The results show that SBFETs are more sensitive to the LER effect in the high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> region and less sensitive in the subthreshold region compared with DG FinFETs. The aggressive fluctuation of drive current can be attributed to the variation of tunneling barrier width. Lowering the Schottky-barrier height and increasing the silicon-body thickness can suppress the parameter fluctuations from the LER effect. The simulation also shows that a 6T SRAM cell consisting of SBFETs is more vulnerable to noise disturbance than its counterpart consisting of FinFETs, particularly for the read operation, which is due to a larger mismatch of drivability of SBFETs within the cell.