Impact Of Interface States Research Articles

Impact of Interface Recombination on Quantum Efficiency of a‐Si:H/c‐Si Solar Cells Based on Si Wires

The impact of interface states on the quantum efficiency of a‐Si:H/c‐Si solar cells based on Si wires is studied using simulation and experimental measurements. The key role of the Si wire geometry for sensitivity of quantum efficiency to interface states on the sidewall is demonstrated. A decrease in Si wire diameter leads to enhanced recombination at the radial interface due to full inversion of the wire. Structures based on n‐Si wires with diameter of 0.5 and 1.5 μm and doping level of 2 × 1015 cm−3 fabricated using a combination of latex sphere lithography and cryogenic dry etching exhibit similar values of open‐circuit voltage (0.5 V) and strong differences for quantum efficiency spectra. For the structures based on Si wires with a radius (0.25 μm) smaller than the space‐charge region (0.6 μm) losses related to interface recombination leads to decrease in the quantum efficiency in the short‐wavelength region. The recombination losses may be reduced for Si wires with a radius exceeding the space charge region in silicon. In case of Si with a doping level of 1015–1016 cm−3, which is used for solar cells, the diameter of the wires should be above 1 μm.

Gate-Voltage Tunability of Plasmons in Single-Layer Graphene Structures—Analytical Description, Impact of Interface States, and Concepts for Terahertz Devices

The strong light-matter interaction in graphene over a broad frequency range has opened up a plethora of photonics applications of graphene. The goal of this paper is to present the voltage tunability of plasmons in gated single- and multi-layer graphene structures. Device concepts for plasmonic interconnects and antennas and their performance for THz communication are presented. For the first time, the role of gate voltage and the thickness of the gate dielectric on the characteristics of plasmon propagation in graphene are quantified by accounting for both the interface trap capacitance and the quantum capacitance. The gate voltage serves as a powerful knob to tweak the carrier concentration and allows building electrically reconfigurable terahertz devices. By optimizing the gate voltage to maximize the plasmon propagation length in a gated multi-layer graphene geometry, we derive simple scaling trends that give intuitive insight into device modeling and design.

On the Ballistic Performance of InGaSb XOI FET: Impact of Channel Thickness and Interface States

Here, we report the effect of channel thickness on the performance of a InGaSb-on-insulator FET with 15-nm gate length. The ballistic current-voltage characteristic is computed by nonequilibrium Green’s function method using thickness-dependent effective mass, which is extracted from tight binding dispersion. Simulation result reveals that the threshold voltage and subthreshold slope decrease with decreasing channel thickness. Nearly three times enhancement in the ON-state current is observed for 3 nm compared with a 5-nm channel when the OFF-state current is made equal in each case by tuning the gate metal work function (WF). The drain-induced barrier lowering is found to decrease with decreasing channel thickness. However, interface states and roughness greatly affect the performance of such ultrathin-body device. Nevertheless, impact of interface states can be compensated by engineering the gate metal WF.

The impact of interface states on the mobility and drive current of [formula omitted] semiconductor n-MOSFETs

Accurate Schrödinger-Poisson and Multi-Subband Monte Carlo simulations are used to investigate the effect of interface states at the channel-insulator interface of In0.53Ga0.47As MOSFETs. Acceptor states with energy inside the conduction band of the semiconductor can explain the dramatic Fermi level pinning observed in the experiments. Our results show that these states significantly impact the electrical mobility measurements but they appear to have a limited influence on the static current drive of short channel devices.

Role of interface states and depletion layer in NO2 sensing mechanism of n-InP epitaxial layers

The electronic properties of n-type InP epitaxial layers covered by their native oxides have been investigated in order to explain the NO2 gas sensing mechanism. The impact of interface states on the interface Fermi level, EF, carrier concentration in-depth profiles, n(x), and resistance, R, of n-InP layers has been studied by means of numerical analysis. The U-shaped interface state continuum, with the density minimum, NSS0, from 1010 to 1013eV−1cm−2, has been assumed at the InP interface according to the disordered-induced gap state model. Moreover, the surface fixed charge, QFC, representing adsorbed ions at the semiconductor surface has been introduced. Also the influence of temperature on the electron distribution n(x) has been analysed. The n-InP layer resistance and Hall-effect measurements (using the Van der Pauw method) have been performed for the InP sensors before and upon NO2 action in order to assess the influence of gas adsorption on the electron concentration and mobility as well as on the depletion layer width, W. On this basis the influence of interface states and near-surface region on the InP layer response to NO2 adsorption has been determined. In addition, the conclusions for optimising the InP-based resistive sensor structure (in terms of the layer thickness and doping) have been obtained.

Impact of Interface States and Bulk Carrier Lifetime on Photocapacitance of Metal/Insulator/GaN Structure for Ultraviolet Light Detection

The influence of interface state density and bulk carrier lifetime on the dependencies of photocapacitance versus wide range of gate bias (-0.1 to -3 V) and light intensity (109 to 1020 photon cm-2 s-1) was studied for metal/insulator/n-GaN UV light photodetector by means of numerical simulations. The light detection limit and photocapacitance saturation were analyzed in terms of the interface charge and interface Fermi level for electrons and holes and effective interface recombination velocity. It was proven that the excess carrier recombination through interface states is the main reason of photocapacitance signal quenching. It was found that the photodetector can work in various modes (on–off or quantitative light measurement) adjusted by the gate bias. A comparison between experimental data and theoretical capacitance-light intensity characteristics was made. A new method for the determination of the interface state density distribution from capacitance–voltage-light intensity measurements was also proposed.

Impact of Interface States and Bulk Carrier Lifetime on Photocapacitance of Metal/Insulator/GaN Structure for Ultraviolet Light Detection

Impact of Interface States and Bulk Carrier Lifetime on Photocapacitance of Metal/Insulator/GaN Structure for Ultraviolet Light Detection

Effect of interface state trap density on the characteristics of n-type, enhancement-mode, implant-free In 0.3Ga 0.7As MOSFETs

The effect of interface state trap density, D it, on the device characteristics of n-type, enhancement-mode, implant-free (IF) In 0.3Ga 0.7As MOSFETs [1,2] has been investigated using a commercial drift-diffusion (DD) device simulation tool. Methodology has been developed to include arbitrary D it distributions in the input simulation decks to more accurately fit the measured subthreshold characteristics of recently reported 1.0 μm gate length IF In 0.3Ga 0.7As MOSFETs [3]. The impact of interface states on a scaled 30 nm gate length IF MOSFET is also reported.

Probing proton damage in SOI CMOS technology by using lateral bipolar action

We investigate proton damage in SOI CMOS devices on UNIBOND using a variety of lateral bipolar operational modes. We show that the impact of interface states and oxide charge can be more clearly observed using lateral bipolar action than by using normal FET operational characteristics. We also investigate the radiation-induced interface states at the Si/buried oxide interface and oxide charges in the buried oxide of this SOI CMOS technology using the DCIV method.

A new model for the current factor mismatch in the MOS transistor

This paper presents a new model for the current factor mismatch of the MOS transistor. It demonstrates that the impact of interface states is negligible. Therefore, the analytical model is based on the random variations of the dopant number in the channel region, similarly to V t mismatch model. As a result, the theoretical value of the matching parameter A β is 0.26%.μm for NMOS and 0.51%.μm for PMOS transistors that is close to experimental results.