Impact Of Bias Temperature Instability Research Articles

Exploring BTI aging effects on spatial power density and temperature profiles of VLSI chips

The Long-term reliability of a chip, encompassing factors like bias temperature instability (BTI), plays a substantial role in the chip's operational efficiency and overall lifespan. Most studies primarily center around performance-related aspects like delay and timing impacts, and fewer studies are performed on reliability impacts on the spatial power density and thermal profiles of the chips. In this study, we propose to investigate the BTI impacts on the spatial power density and temperature profiles of VLSI chips for the first time. We assessed the BTI aging impact on the on-chip spatial power density and temperature for two widely used circuit functional blocks (dual port RAM, Discrete Cosine Transform (DCT) block) at T = 130◦C and T = 25◦C to account for the worst-case BTI degradation, using degradation-aware cell libraries for a 10-year aging scenario. Furthermore, we showcased the essential role of BTI aging-aware timing analysis in evaluating the impact of BTI aging on total power, on-chip spatial power density, and thermal maps. Neglecting this aspect can result in a substantial underestimation of the results related to the parameters mentioned above. We developed a power map generation method from the circuit layout and power analysis from EDA tools. We demonstrate that both circuits’ maximum power density reduction is approximately 12 % and 20 %, respectively. Furthermore, to analyze the BTI impact on spatial temperature, we built the heat transfer model using a multiphysics tool to imitate a real chip (Intel i7-8650U) and performed thermal simulations to evaluate the spatial thermal map. The resulting maximum temperature reduction for both these circuits is approximately 10 % and 12 %, respectively, which is quite significant.Our analysis has further unveiled that, in the context of a specific circuit, the position of maximum power density and the occurrence of a hot spot remains consistent over time, unaffected by aging. However, it's important to note that these positions can vary between different circuits, primarily influenced by the workload the circuit is currently handling. Furthermore, our findings demonstrate that the effects of Bias Temperature Instability (BTI) aging are significantly more pronounced when the circuit operates at higher temperatures (T = 130◦C) compared to lower operating temperatures (T = 25◦C).

Enabling efficient rate and temporal coding using reliability‐aware design of a neuromorphic circuit

AbstractReliability aspects such as bias temperature instability (BTI) and hot carrier injection (HCI) affecting devices in advanced CMOS‐based technology have been the subject of active research in recent decades. Due to these reliability issues, various digital and analog circuits were investigated for degradation. However, circuit blocks like the neuron circuits of neuromorphic systems are not fully explored. This work is inclined toward examining the collective degradation impact of BTI and HCI due to aging in an adaptive exponential “integrate and fire” (I&F) model‐based, neuromorphic neuron circuit. Detailed degradation analysis of the stimulated neuron circuit aided in identifying possible mismatches/faults associated with neuron spikes. These factors could reduce the efficiency of the neuronal circuit by potentially affecting the transmission of information in a neuromorphic system. Various performance parameters were then derived to quantify the extent of circuit deterioration. The proposed reliability‐aware design aims to improve the circuit degradation through its effectiveness in alleviating the overall reliability impact. It demonstrates enhanced circuit operation in spike generation even after aging. The circuit performance is validated through simulations at “Time0” (pre‐degradation) and “Aged” (post‐degradation) neuron netlists, which is then compared with the proposed reliability‐aware circuit.

Crosstalk Induced Shoot-Through in BTI-Stressed Symmetrical & Asymmetrical Double-Trench SiC Power MOSFETs

In this paper, the crosstalk-induced shoot-through current and induced gate voltage of SiC planar MOSFETs, SiC symmetrical double-trench MOSFETs and SiC asymmetrical double-trench MOSFETs is investigated on a half-bridge circuit to analyse the impact of temperature, drain-source voltage switching rate, gate resistance and load current level on crosstalk-induced properties of different SiC MOSFET structures. It shows that due to the smaller gate-source capacitance, the two double-trench MOSFETs exhibit higher induced gate voltage during crosstalk with the same external gate resistance, which together with the higher transconductance, yield higher shoot-through current than the planar MOSFET. Accordingly, their shoot-through current decreases with increasing of the load current while the planar MOSFET exhibits an opposite trend. The different trend of shoot-through current with temperature on DUTs reveals that the crosstalk in different device structures are dominated by different mechanisms, i.e. threshold voltage and channel mobility with the gate-source capacitance influencing the amplitude. Impact of bias temperature instability with positive and negative gate stressing is measured with a range of stress and recover periods at temperateness ranging between 25 °C to 175 °C. These measurements show that the peak shoot-through correlates with the threshold drift, though with less sensitivity for SiC symmetrical and asymmetrical double-trench MOSFETs compared with the planar SiC MOSFET where the inter-dependence is pronounced. A model is developed for the induced gate voltage and shoot-through current during crosstalk with channel current considered. The comparison of the model results with measurement confirms its capability to predict crosstalk in different MOSFET structures.

Reliability‐aware design of temporal neuromorphic encoder for image recognition

AbstractVery large scale integration (VLSI)‐based neuromorphic systems have been evolving quickly in recent years. These systems have been used in complex cognitive tasks such as image classification and pattern recognition. A neuromorphic encoder is an essential component in a neuromorphic system, which converts sensory data into spike trains. The advancement in CMOS technology nodes leads to various reliability issues. Bias temperature instability (BTI) and hot carrier injection (HCI) are major reliability issues in analog/mixed VLSI circuits. This paper implements a temporal neuromorphic encoder, and a corresponding mathematical model is derived for image processing applications. The relationship between an input image pixel value and output of the encoder, that is, interspike interval (ISI), is found to be exponential. The impact of BTI and HCI on the temporal neuromorphic encoder is analyzed. The degradation analysis revealed a loss of encoding functionality for which three mitigation techniques are discussed. Finally, a reliability‐aware neuromorphic encoder is proposed to minimize the effect of degradation over its lifetime. The power consumption of conventional and proposed reliability‐aware neuromorphic encoders is also presented.

Performance of Parallel Connected SiC MOSFETs under Short Circuits Conditions

This paper investigates the impact of parameter variation between parallel connected SiC MOSFETs on short circuit (SC) performance. SC tests are performed on parallel connected devices with different switching rates, junction temperatures and threshold voltages (VTH). The results show that VTH variation is the most critical factor affecting reduced robustness of parallel devices under SC. The SC current conducted per device is shown to increase under parallel connection compared to single device measurements. VTH shift from bias–temperature–instability (BTI) is known to occur in SiC MOSFETs, hence this paper combines BTI and SC tests. The results show that a positive VGS stress on the gate before the SC measurement reduces the peak SC current by a magnitude that is proportional to VGS stress time. Repeating the measurements at elevated temperatures reduces the time dependency of the VTH shift, thereby indicating thermal acceleration of negative charge trapping. VTH recovery is also observed using SC measurements. Similar measurements are performed on Si IGBTs with no observable impact of VGS stress on SC measurements. In conclusion, a test methodology for investigating the impact of BTI on SC characteristics is presented along with key results showing the electrothermal dynamics of parallel devices under SC conditions.

Impact of Bias Temperature Instabilities on the Performance of Logic Inverter Circuits Using Different SiC Transistor Technologies

All electronic devices, in this case, SiC MOS transistors, are exposed to aging mechanisms and variability issues, that can affect the performance and stable operation of circuits. To describe the behavior of the devices for circuit simulations, physical models which capture the degradation of the devices are required. Typically compact models based on closed-form mathematical expressions are often used for circuit analysis, however, such models are typically not very accurate. In this work, we make use of physical reliability models and apply them for aging simulations of pseudo-CMOS logic inverter circuits. The model employed is available via our reliability simulator Comphy and is calibrated to evaluate the impact of bias temperature instability (BTI) degradation phenomena on the inverter circuit’s performance made from commercial SiC power MOSFETs. Using Spice simulations, we extract the propagation delay time of inverter circuits, taking into account the threshold voltage drift of the transistors with stress time under DC and AC operating conditions. To achieve the highest level of accuracy for our evaluation we also consider the recovery of the devices during low bias phases of AC signals, which is often neglected in existing approaches. Based on the propagation delay time distribution, the importance of a suitable physical defect model to precisely analyze the circuit operation is discussed in this work too.

Bias Temperature Instability and Junction Temperature Measurement Using Electrical Parameters in SiC Power MOSFETs

Junction temperature sensing is an integral part of both online and offline condition monitoring where direct access to the bare die surface is not available. Given a defined power input, the junction temperature enables the estimation of the junction-to-case thermal resistance, which is a key indicator of packaging failure mechanisms like solder voiding and cracks. The use of temperature sensitive electrical parameters (TSEPs) has widely been proposed as a means of junction temperature sensing; however, there are certain challenges regarding their use in SiC MOSFETs. Bias temperature instability (BTI) from charge trapping in the gate dielectric causes threshold voltage drift, which in SiC affects some of the key TSEPs including on -state resistance, body diode forward voltage as well as the current commutation rate. This article reviews the impact of BTI on the accurate junction temperature measurement using TSEPs in SiC MOSFETs.

Impact of BTI-Induced Threshold Voltage Shifts in Shoot-Through Currents From Crosstalk in SiC MOSFETs

In this article, a method for evaluating the implications of threshold voltage (VTH) drift from gate voltage stress in SiC MOSFETs is presented. By exploiting the Miller coupling between two devices in the same phase leg, the technique uses the shoot-through charge from parasitic turn-on to characterize the impact of bias temperature instability (BTI)-induced VTH shift. Traditional methods of BTI characterization rely on the application of a stress voltage without characterizing the implication of the VTH shift on the switching characteristics of the device in a circuit. Unlike conventional methods, this method uses the actual converter environment to investigate the implications of VTH shift and should therefore be of more interest to applications engineers as opposed to device physicists. Furthermore, a common problem is the underestimation of the VTH shift since recovery from charge detrapping can mask the true extent of the problem. The impact of temperature, the recovery time after stress removal, and polarity of the stress has been studied for a set of commercially available SiC MOSFETs.

Soft error hardening enhancement analysis of NBTI tolerant Schmitt trigger circuit

Bias temperature instability (BTI) and soft errors are major reliability concerns for deep submicron technologies. Negative BTI leads to an increase of the threshold voltage of PMOS transistors and is thus considered a serious challenge for improving circuit performance. In this paper, we concentrate on a design-time solution, i.e., more reliable NMOS only Schmitt Trigger with Voltage Booster (NST-VB). For this we analyzed the impact of BTI on the soft-error susceptibility of different CMOS circuits using HSPICE and performed critical charge simulations considering different supply voltages and stress time. From our results, we conclude that the NST-VB circuit has a higher critical charge when compared to CMOS inverters and Schmitt trigger (ST) based counterparts. NST-VB has improved the sensitivity of 62.48% and 55.10%, as compared to CMOS inverter and ST circuits, respectively, after three years of operation. To better assess soft error resilience, we introduce a soft error rate ratio (SERR) as a performance metric. Our analysis indicates that NST-VB has 12.62%, and 12.39% less SERR compared to ST and CMOS inverters. The effect of process variation on CMOS inverter, ST inverter and NST-VB circuit are analyzed using 5000 Monte Carlo simulations for critical voltages and we observe that the deviation of NST-VB is 6.06× and 6.89× less as compared to the CMOS and ST based inverters, respectively.

Selective Flip-Flop Optimization for Reliable Digital Circuit Design

Runtime variability sources, such as bias temperature instability (BTI) and supply voltage fluctuation affect both timing and functionality of the flip-flops inside a VLSI circuit. In this paper, we propose a method to improve the timing and reliability of the VLSI circuits by optimizing the flip-flops for resiliency against aging and supply voltage fluctuation. In the proposed selective reliability optimization method, we first extend the standard cell libraries by adding optimized versions of the flip-flops designed for better resiliency against severe BTI impact and/or supply voltage fluctuation. Then, we optimize the VLSI circuit by replacing the aging-critical and voltage-drop-critical flip-flops (VC) of the circuit with the reliability-optimized versions to improve the timing and the reliability of the entire circuit in a cost-effective way. The simulation results show that incorporating the optimized flip-flops in a processor can prolong the lifetime of the processor by 36.9% compared to the original design, which translates into better reliability. This is achieved with negligible leakage overhead (less than 0.1% on the processor) and no area overhead which facilitates the integration of the proposed method in the standard VLSI design flow.

A comparative study of lifetime reliability of planar MOSFET and FinFET due to BTI for the 16 nm CMOS technology node based on reaction-diffusion model

Intensive scaling of Integrated Circuits is a crucial factor for achieving high performance and astronomical packing density. However, this scaling is pushing planar MOSFET to its physical limitations. Nowadays, FinFET emerges as a promising alternative technology for planar MOSFET, due to their better efficiency. Nevertheless, this inevitably leads to a rising concern on the reliability of FinFET as the circuit lifetime reliability cannot be neglected due to this accelerated scaling of Integrated Circuits. This paper is considered as the first work that: 1) detects which CMOS technology, planar MOSFET or FinFET, is more robust against Bias Temperature Instability (BTI) aging degradation for the advanced nodes such as 16 nm; 2) precisely computes the effect of BTI on 16 nm FinFET using an adequate BTI Reaction Diffusion model that takes into consideration the effects of finite oxide thickness, and the influence of polysilicon; 3) investigates the efficiency in terms of power consumption and area for the predominant circuit level techniques that could be implemented to overcome the negative impact of BTI for FinFET technology. This research clearly indicates that FinFET technology is more robust against BTI aging degradation than planar MOSFET as the delay percentage for FinFET technology is lower than planar MOSFET technology by 26%.

Impact of Bias Temperature Instability (BTI) Aging Phenomenon on Clock Deskew Buffers

In this paper we analyze the effect of the Bias Temperature Instability (BTI) aging phenomenon on the delay of deskew buffers employed in high performance microprocessors. Our analysis shows that, during circuit lifetime, the delay induced by BTI on each deskew buffer within the microprocessor can be significantly different, depending on how each deskew buffer is configured after fabrication (to compensate clock skews occurring during the fabrication process) and the operating temperature. Therefore, we show that even if deskew buffers compensate skews among clock signals after fabrication, their different level of degradation during circuit lifetime can generate significant skews between clock signals after only some month of circuit operation in the field. Moreover, the variations in the delay of deskew buffers due to BTI can exceed the maximum compensation range enabled by such schemes, thus making skew compensation during circuit lifetime ineffective. Finally, we propose a simple mathematical model enabling to estimate the maximum skew among clock signals during the chip lifetime. The model can be used to activate proactive compensation approaches (e.g., clock frequency reduction) allowing to avoid malfunctions caused by an excessive skew among clock signals generated by BTI degradation of the deskew buffers.

Low-Cost Strategy to Mitigate the Impact of Aging on Latches’ Robustness

Analyses recently presented in the literature have shown that the Bias Temperature Instability (BTI) ageing phenomenon may increase significantly the susceptibility to soft errors (SEs) of robust latches. Particularly, this is the case of low-cost robust latches, whose robustness is obtained by increasing the critical charge of their most susceptible node, that is the node most contributing to the latch soft error rate (SER). Therefore, in applications mandating the use of low-cost robust latches, designers will have to face the problem of such latches’ robustness degradation during the IC operation. In order to cope with this problem, we here propose a strategy to reduce the impact of BTI on the SER of standard and low-cost robust latches. It will be proven that our approach enables to reduce by approximately the 50 percent the SER increase due to BTI during circuit lifetime with respect to original latches, at limited increase in terms of area overhead, latch setup time and power consumption, and with no impact on the latch input-output delay.

Bias temperature instability and condition monitoring in SiC power MOSFETs

Threshold voltage shift due to bias temperature instability (BTI) is a major concern in SiC power MOSFETs. The SiC/SiO2 gate dielectric interface is typically characterized by a higher density of interface traps compared to the conventional Si/SiO2 interface. The threshold voltage shift that arises from BTI has significant implications on the reliability of SiC power MOSFETs, hence, techniques for detecting the change in electrical parameters due to gate oxide degradation are desirable. Using accelerated high temperature gate bias stress tests on SiC MOSFETs, it has been shown that the output and transfer characteristics are affected by BTI. This paper presents the impact BTI induced threshold voltage shift on the forward voltage of the SiC MOSFET body diode during third quadrant operation. Using the forward voltage of the body diode during reverse conduction of low currents, threshold voltage shift can be detected, hence, the impact of BTI can be evaluated. The implications of the body diode forward voltage shift on junction temperature measurements are also studied in the context of TSEPs. The findings in this paper are important for engineers seeking to implement condition and health monitoring techniques on SiC power devices.

Time-zero-variability and BTI impact on advanced FinFET device and circuit reliability

In this study a careful analysis of the device and the circuit level variability and reliability are presented. Planar 20nm System on Chip (SoC), 16nm FinFET (16FF) and 10nm FinFET (10FF) devices are studied to understand the time-zero process variability and Bias Temperature Instability (BTI) stress induced (time dependent) threshold voltage (VT) variations to evaluate the device degradation. Moreover, to understand the circuit level variability, the 6-Transistor (6T) SRAM performance is assessed in terms of the static noise margin (SNM) degradation under the influence of BTI stress. Finally, the product level SRAM performance is studied in terms of the minimum SRAM operating voltage (Vmin) degradation.

Reliability in Super- and Near-Threshold Computing: A Unified Model of RTN, BTI, and PV

Near-threshold computing (NTC) poses stringent constraints on designing reliable circuits, as degradations have a magnified impact at lower supply voltages ( $V_{\text {dd}}$ ) compared with super-threshold supply voltages. While phenomena, such as bias temperature instability (BTI) scale down with $V_{\text {dd}}$ , mitigate their magnified impact with reduced degradations and, thus, have little impact on NTC reliability. Process variation (PV) and random telegraph noise (RTN) do not scale with $V_{\text {dd}}$ and, therefore, become key reliability challenges in NTC. On the other hand, in super-threshold computing (STC), PV and BTI are the dominant phenomena, as BTI induces considerable degradations at nominal $V_{\text {dd}}$ and PV imposes large enough shifts to matter at any supply voltage. Therefore, to allow $V_{\text {dd}}$ -scaling from super-to near-threshold, we need to consider all of BTI, RTN, and PV. Ergo, we present a unified RTN and BTI model that models their shared physical origin and is validated against experimental data across a wide voltage range. Our unified model and PV model capture the joint impact of RTN, BTI, and PV within a probabilistic reliability estimation for NTC and STC circuits. We employed our proposed model to analyze the reliability of SRAM cells showing how taking error correction codes into account is able to mitigate the deleterious effects of BTI, RTN, and PV by 36% compared with unprotected circuits.

Estimating Circuit Aging Due to BTI and HCI Using Ring-Oscillator-Based Sensors

The performance of nanometer-scale circuits is adversely affected by aging induced by bias temperature instability (BTI) and hot carrier injection (HCI). Both BTI and HCI impact transistor electrical parameters at a level that depends on the operating environment and usage of the circuit. This paper presents a novel method, using on-chip sensors based on ring oscillators (ROSCs), to detect the delay shifts in circuits as a result of aging. Our method uses presilicon analysis of the circuit to compute calibration factors that can translate BTI- and HCI-induced delay shifts in the ROSC to those in the circuit of interest. Our simulations show that the delay estimates are within 1% of the true values from presilicon analysis. Further, for post-silicon analysis, a refinement strategy is proposed where sensor measurements can be amalgamated with infrequent online delay measurements on the monitored circuit to partially capture its true workloads. This leads to about 8% lower delay guardbanding overheads compared to the conventional methods as demonstrated using benchmark circuits.

Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier

The CMOS technology scaling faced over the past recent decades severe variability and reliability challenges. One of the major reliability challenges is bias temperature instability (BTI). This paper analyzes the impact of BTI on the sensing delay of standard latch-type sense amplifier (SA), which is one of the critical components of high performance memories; the analysis is done by incorporating the impact of process, voltage, and temperature variations (in order to investigate the severity of the integral impact) and by considering different workloads and four technology nodes (i.e., 45, 32, 22, and 16 nm). The results show the importance of taking the SA degradation into consideration for robust memory design; the SA degradation depends on the application and technology node, and the sensing delay can increase with 184.58% for the worst case conditions at 16 nm. The results also show that the BTI impact for nominal conditions at 16 nm reaches a 12.10% delay increment. On top of that, when extrinsic conditions are considered, the degradation can reach up to 168.45% at 398 K for 16 nm.

Bias Temperature Instability Mitigation via Adaptive Cache Size Management

Bias temperature instability (BTI) is one of the major CMOS reliability issues in nanoscales. The main impact of BTI on SRAM memory cells is the degradation of the static noise margin (SNM), which leads to a higher susceptibility to failures. A variety of techniques for mitigating the impact of BTI on caches have been proposed at architecture level. However, their considerable overheads limit the application of such techniques. Recent studies showed that the utilization of the cache capacity widely varies from one workload to another and even within a workload. When cache utilization is low, for the majority of the cells, the same value is stored for a very long period, which significantly degrades SNM due to BTI. In this paper, we propose a technique to dynamically adjust the cache size according to the running workload cache requirement by monitoring the cache miss rate. The unused cache capacity is power gated to increase the energy efficiency and mitigate aging of the entire cache. The experimental results show that the proposed technique reduces hold and read SNM degradation by up to 48.1% and 33.3%, respectively, at the cost of 2.0% performance penalty.

Impact of Bias Temperature Instability on Soft Error Susceptibility

In this paper, we address the issue of analyzing the effects of aging mechanisms on ICs' soft error (SE) susceptibility. In particular, we consider bias temperature instability (BTI), namely negative BTI in pMOS transistors and positive BTI in nMOS transistors that are recognized as the most critical aging mechanisms reducing the reliability of ICs. We show that BTI reduces significantly the critical charge of nodes of combinational circuits during their in-field operation, thus increasing the SE susceptibility of the whole IC. We then propose a time dependent model for SE susceptibility evaluation, enabling the use of adaptive SE hardening approaches, based on the ICs lifetime.