Impact Ionization Transistors Research Articles

High drain field impact ionization transistors as ideal switches

Impact ionization effect has been demonstrated in transistors to enable sub-60 mV dec−1 subthreshold swing. However, traditionally, impact ionization in silicon devices requires a high operation voltage due to limited electrical field near the device drain, contradicting the low energy operation purpose. Here, we report a vertical subthreshold swing device composed of a graphene/silicon heterojunction drain and a silicon channel. This structure creates a low voltage avalanche impact ionization phenomenon and leads to steep switching of the silicon-based device. Experimental measurements reveal a small average subthreshold swing of 16 µV dec−1 over 6 decades of drain current and nearly hysteresis-free, and the operating voltage at which a vertical subthreshold swing occurs can be as low as 0.4 V at room temperature. Furthermore, a complementary silicon-based logic inverter is experimentally demonstrated to reach a voltage gain of 311 at a supply voltage of 2 V.

Robust Impact-Ionization Field-Effect Transistor Based on Nanoscale Vertical Graphene/Black Phosphorus/Indium Selenide Heterostructures.

Maintaining the rapid development of information technology by scaling down a metal-oxide semiconductor field-effect transistor faces two serious challenges. First, the gate field loses control of the channel as it continuously decreases. Second, the fundamental thermionic limit restricts the reduction in supply voltage. Thus, further scaling down necessitates alternative device structures and different switching mechanisms. Here, we report impact-ionization transistors (IITs) based on nanoscale (∼30 nm) vertical graphene/black phosphorus (BP)/indium selenide (InSe) heterostructures. By facilitating the carrier multiplication of the ballistic impact-ionization process as the internal gain mechanism in sub-mean-free-path (sub-MFP) channels, the IITs exhibit a low average subthreshold swing (SS < 1 mV/dec) over five current levels. High stability (>10 000 cycles) and small hysteresis (<1%) switching properties are also obtained. The experimental demonstration of such transistor combining steep SS, high ON-state current density, reliable robustness, miniature footprint, and low bias voltage approaches fulfillments of targets for next-generation devices in the International Technology Roadmap for Semiconductors.

Observation of ballistic avalanche phenomena in nanoscale vertical InSe/BP heterostructures.

Impact ionization, which supports carrier multiplication, is promising for applications in single photon detection1 and sharp threshold swing field effect devices2. However, initiating the impact ionization of avalanche breakdown requires a high applied electric field in a long active region, which hampers carrier multiplication with a high gain, low bias and superior noise performance3,4. Here we report the observation of ballistic avalanche phenomena in sub-mean free path (MFP) scaled vertical InSe/black phosphorus (BP)5-9 heterostructures10. We use these heterojunctions to fabricate avalanche photodetectors (APDs) with a sensitive mid-infrared light detection (4 μm wavelength) and impact ionization transistors with a steep subthreshold swing (<0.25 mV dec-1). The devices show a low avalanche threshold (<1 V), low noise figure and distinctive density spectral shape. Our transport measurements suggest that the breakdown originates from a ballistic avalanche phenomenon, where the sub-MFP BP channel support the lattice impact ionization by electrons and holes and the abrupt current amplification without scattering from the obstacles in a deterministic nature. Our results provide new strategies for the development of advanced photodetectors1,11,12 via efficient carrier manipulation at the nanoscale.

Current Status of Reliability in Extended and Beyond CMOS Devices

In the history of electronics, solid-state materials replaced the vacuum parts to reduce power consumption and to obtain better reliability at a reduced cost. The size of solid-state transistors continued to reduce since its introduction, and currently, we have transistors with dimensions on the order of ~10 nm. This downscaling of transistor dimension accompanied with proportionate changes in supply voltage so that the overall power consumption stays below a tolerable limit. The situation dramatically changed when requirements of proper electrostatic control over the entire length of the transistor and its reliable operation stopped supply voltage scaling, increased OFF-state leakage, and hence caused exponential increase in power consumption. The introduction of a high-κ gate dielectric and then a multiple/ surround gate within the CMOS architecture have improved the situation, but still have not provided the complete solution for the future. For future electronic devices, we need switches with extremely low OFF-state leakage, small supply voltage, and high-drive current without compromising the yield and reliability currently available in modern-day nanoscale transistors. The available options are based on extensions of current CMOS transistors by using nanowires, III-V compounds, carbon nanomaterials, transition metal dichalcogenides as channel, ferroelectrics as dielectric, and ferromagnets as source/drain. On the other hand, device architectures that are completely different from conventional CMOS (so-called beyond CMOS devices) such as tunnel transistors, nanoelectromechanical devices, and impact ionization transistors are also under consideration for future electronics. The performance of many of these beyond CMOS devices is yet to be comparable to that obtained in the current-day CMOS transistors. In addition, many of these proposed devices have a number of classical and some novel reliability concerns. This review article presents reliability concerns for a set of extended and beyond CMOS devices and shows that defects in different parts of these devices require detailed study to ensure their usability in electronics industry. Therefore, in addition to the current ongoing research to obtain better performance using the proposed devices, a parallel reliability analysis is also needed. This kind of early-stage reliability analysis may reveal whether any reliability concern is intrinsically related to the device design-hence suggests us to look for alternative device concepts for future CMOS.

Properties and mechanisms of Z2-FET at variable temperature

This paper presents a systematic study of Z2-FET (Zero Subthreshold Swing and Zero Impact Ionization transistor) fabricated in advanced Fully Depleted Silicon On Insulator (FDSOI) 28nm technology with Ultra-Thin Body and Buried Oxide (UTBB). It is a recent sharp-switching device that achieves remarkable performance in terms of leakage current and triggering control. The device features an extremely sharp on-switch, an adjustable triggering voltage (VON), and is considered for Electro-Static Discharge (ESD) protection. The operation principle relies on the modulation of electrons and holes injection barriers. Experimental results show the effect of low and high temperature on the output characteristics, triggering voltage and leakage current.