Image Rejection Receiver Research Articles

A Q-Band CMOS Image-Rejection Receiver Integrated with LO and Frequency Dividers

This paper presents a Q-band image-rejection receiver using a 65 nm CMOS technology. For a high image-rejection ratio (IMRR), the Q-band receiver employs the Hartley architecture which consists of a Q-band low-noise amplifier, two down-conversion mixers, a 90° hybrid coupler, and two IF baluns. In addition, a Q-band fundamental voltage-controlled oscillator (VCO) and a frequency divider chain divided by 256 are integrated into the receiver for LO. A charge injection technique is employed in the mixers to reduce the DC power while maintaining a high conversion gain and linearity. The VCO adopts a cross-coupled topology to secure stable oscillation with high output power in the Q-band. The frequency divider chain is composed of an injection-locked frequency divider (ILFD) and a multi-stage current-mode logic (CML) divider to achieve a high division ratio of 256, which facilitates the LO signal locking to an external phase-locked loop. An inductive peaking is employed in the ILFD to widen the locking range. The Q-band image-rejection receiver exhibits a peak conversion gain of 16.4 dB at 43 GHz. The IMRR is no less than 35.6 dBc at the IF frequencies from 1.5 to 5 GHz.

All-Optical and Broadband Microwave Image-Reject Receiver Based on Phase Modulation and I/Q Balanced Detection

Image-reject radio frequency (RF) receiver is the backbone of modern RF systems, but often suffers from limited bandwidth, local oscillator (LO) leakage, even-order distortion, and I/Q imbalance. A wideband photonic image-reject RF receiver based on two phase-modulators (PMs) in a Sagnac loop and an I/Q balanced detector is proposed. In the experiment, excellent I/Q amplitude balance (<0.8 dB) and phase balance (<0.7 degrees) over a wide operating frequency from 8 to 40 GHz are achieved. Due to balanced detection, the even-order distortion and dc-offset are significantly suppressed. Combined with an analog intermediate frequency (IF) quadrature coupler, the image-reject RF receiver is implemented with a spurious free dynamic range (SFDR) of 99.4 dB·Hz2/3 and an image rejection of 50.3 dB. An antenna remoting RF vector signal with image interference is down-converted to the IF domain. Benefiting from the significant image rejection and Sagnac loop architecture, a good constellation diagram and a low error vector magnitude (EVM) of the desired signal are obtained.

A 20–44-GHz Image-Rejection Receiver With &gt;75-dB Image-Rejection Ratio in 22-nm CMOS FD-SOI for 5G Applications

This article presents a 20–44-GHz image-rejection receiver in GlobalFoundries 22-nm fully-depleted silicon-in-insulator (FD-SOI). The receiver includes a wideband LNA with a three-pole high-pass rejection filter coupled to a double-balanced mixer with a wideband LO driver and an intermediate frequency (IF) amplifier. At an IF of 16 GHz, the image band at dc −12 GHz is filtered by the LNA response and is greater than 75 dB over the entire 20–44-GHz range. The receiver results in a gain of 24–28.5 dB and a noise figure (NF) of 3.3–5 dB at 20–44 GHz and achieves an error vector magnitude (EVM) of 3.6%–3.7% at the carrier frequency of 28 and 39 GHz with 2-Gbaud symbol rate at 64-QAM waveform. To the best of the authors’ knowledge, this is the first wideband image-rejection receiver that covers the entire millimeter-wave 5G band based on GF 22-nm CMOS FD-SOI.

Research Progress of Ka Band Monolithic Integrated Image Rejection Receiver

Image rejection mixer and low noise amplifier (LNA) are the key components of the receiver system. After low noise amplification, the received RF signal is moved to the IF frequency and the interference signal at the image frequency is suppressed. Image rejection receiver is widely used in microwave communication, global positioning system, remote sensing and other systems, which is an essential circuit of the above systems. This paper introduces the research background and significance of Ka band monolithic integrated image rejection receiver, summarizes and prospects the research progress at home and abroad. Finally, a new integration scheme is proposed, which can reduce chip area and cost without reducing performance.

A Micropulse eye-safe all-fiber molecular backscatter coherent temperature lidar

In this paper, we analyze the performance of an all-fiber, micropulse, 1.5 μ m coherent lidar for remote sensing of atmospheric temperature. The proposed system benefits from the recent advances in optics/electronics technology, especially an all-fiber image-reject homodyne receiver, where a high resolution spectrum in the baseband can be acquired. Due to the presence of a structured spectra resulting from the spontaneous Rayleigh-Brillouine scattering, associated with the relevant operating regimes, an accurate estimation of the temperature can be carried out. One of the main advantages of this system is the removal of the contaminating Mie backscatter signal by electronic filters at the baseband (before signal conditioning and amplification). The paper presents the basic concepts as well as a Monte-Carlo system simulation as the proof of concept.

A 90-nm CMOS V-Band Low-Power Image-Reject Receiver Front-End With High-Speed Auto-Wake-Up and Gain Controls

A low-power auto-wake-up image-reject receiver front-end in 90-nm CMOS technology is presented for V-band applications. The proposed front-end generally operates in the sleep mode and consumes 19 mW. When an RF signal greater than ${-}{\hbox{50}}$ dBm is received, the front-end wakes up automatically and enters into the active mode consuming only 46-mW power. Adjustable linearity $({\rm IP}_{{{1{\rm dB}}}})$ of the front-end is provided by changing two gain modes (high- and low-gain modes). When input RF power is higher than $-{\hbox{30}}$ dBm, ${\rm IP}_{{{1{\rm dB}}}}$ will be improved (from high-gain mode to low-gain mode). Experiments show ${\rm IP}_{{{1{\rm dB}}}}$ of $-{\hbox{25.2}}$ and $-{\hbox{22.5}}$ dBm in high- and low-gain modes, respectively. An image-reject ratio greater than 32 dB is measured when using the proposed image-reject mixer topology. All passive phase-shift couplers for realizing the image-rejection are composed of standard CMOS lumped elements, thereby considerably reducing the chip size (0.82 mm $^{{{2}}}$ ).

Calibration study of dual-band Weaver–Hartley receiver architecture

This paper presents a calibration study of dual-band image rejection receiver based on combined Weaver–Hartley architecture, with improved image rejection of first and second image signals. The system implementation is based on dual-band WLAN 802.11 a/g. When the desired signal is at 5.7-GHz band, the 2.4-GHz band becomes the first image signal and vice versa. The output IF frequency is at 30-MHz. The detection of the gain and phase mismatches is based on modeling, extraction of related error signals and correcting them in closed loop. Moreover, we demonstrate an open loop technique to reach the phase and gain correction signals. The correction signals can be digitally stored and applied as digital trimming control on the LO signals. Simulation showed close to 60dB of image rejection ratio for the first image signal. Second image signal is rejected by a 4-section poly-phase filter.

A fully analog calibration technique for phase and gain mismatches in image-reject receivers

A systematic approach to I/Q mismatch calibration in image-reject receivers is presented in this paper. A new error detection algorithm is proposed, which automatically calibrates for phase and gain mismatches limiting the performance of image-reject receivers. A dual-loop feedback is employed which looks for the minimum phase/gain error using a 2-dimensional analog-based search algorithm and then finds the minimum value for the error. An experimental CMOS prototype RF front-end for cognitive radio applications operating at 400–800MHz is proposed and simulated in the 0.18μm CMOS technology, achieving an image rejection ratio (IRR) better than 55-dB in post-layout simulation. The comprehensive mathematical model of this analog algorithm is thoroughly studied in the appendix and the convergence is verified theoretically.

하이사이드와 로우사이드 LO 신호를 동시에 적용하는 새로운 이미지 제거 수신기 구조

본 논문에서 높은 주파수 LO 신호와 낮은 주파수 LO신호를 동시에 사용하는 새로운 구조의 이미지 제거 수신기 구조를 제안하였다. 제안된 구조는 기존의 하나의 LO 신호를 사용하는 경우보다 저 잡음 지수 성능과 높은 선형성 특성을 갖는다. 또한 제안된 수신기는 기존의 Weaver 이미지 제거 수신기 구조 보다 같은 이득 error와 위상 error가 존재할 때도 6dB 이상의 높은 이미지 제거 특성을 보인다. 제안된 수신기 구조의 특성을 증명하기 위하여 이득 및 위상 error가 존재할 때의 이미지 제거 특성 공식을 유도하였다. 그리고 이 공식의 유용성을 시스템 시뮬레이션을 통하여 증명하였다. 따라서 높은 이미지 제거 특성 때문에 제안된 새로운 수신기 구조가 이미지 제거 수신기로써 널리 사용이 가능할 것으로 기대한다. In this paper, we propose a new image rejection receiver architecture using simultaneously the high-side and low-side injected LO signals. The proposed architecture has a lower noise figure (NF) performance and a higher linearity characteristic than the previous receiver architecture using a single LO signal. Also, the proposed receiver shows a higher IRR performance about 6dB than that of the previous Weaver image rejection architecture even though the same gain and phase errors between I-path and Q-path exist. To verify these characteristics, we derive an IRR formular of the proposed architecture as a function of mismatch parameters. And we demonstrate its formular's usefulness through the system simulation. Therefore, the proposed architecture will be widely used to implement the image rejection receiver due to its higher IRR performance.

Image-rejection receiver using on-chip active notch filters for 2.4-GHz band wireless communication applications

This paper presents the design and experimental results of image-rejection (IR) receiver front-end for 2.4-GHz band applications. The proposed IR-receiver front-end integrates a third-order active notch filter into each of conventional cascode low noise amplifier and down-conversion mixer to achieve high image-rejection ratio (IRR). The image signal is suppressed and the wanted signal is maximized due to series and parallel resonator effects of the notch filter, respectively. Consequently, the proposed IR-receiver front-end implemented in a standard 0.18 μm CMOS technology has the power gain of 21.5 dB, the noise figure of 3.5 dB, the input third order intermodulation product of ?15 dBm and the IRR of 56 dB. The IR-receiver front-end dissipates a total of 5.5 mA from supply voltage of 1.8 V.

A CMOS adaptive RF front-end receiver for wireless applications

Design and implementation of an image-rejection double-quadrature radio frequency front-end receiver based on tunable polyphase filters (PPF) are presented in this article. The front-end consists of two sets of PPFs and a double-quadrature down-converter. The design contains devices that allow process spread and frequency drift control, making it suitable for multi-standard applications. Formal analysis and statistical method leading to the polyphase filter optimal sizing have been dealt with in this article. The effects of parasitic capacitances and component mismatch are also considered and discussed. Steps within CMOS polyphase filter design flow are then provided to guarantee high image rejection ratio (IRR) performance. The front-end receiver exhibits more than 60 dB IRR and good linearity in high-frequency applications.

Gain and Phase Mismatch Calibration Technique in Image-Reject RF Receiver

This paper presents a gain and phase mismatch calibration technique for an image-reject RF receiver. The gain mismatch is calibrated by directly measuring the output signal amplitudes of two signal paths. The phase mismatch is calibrated by measuring the output amplitude of the final IF output at the image band. The calibration of the gain and phase mismatch is performed at power-up, and the normal operation of the RF receiver does not interfere with the mismatch calibration circuit. To verify the proposed technique, a 2.4-㎓ Weaver image-reject receiver with the gain and phase mismatch calibration circuit is implemented in a 0.18-㎛ CMOS technology. The overall receiver achieves a voltage gain of 45 ㏈ and a noise figure of 4.8 ㏈. The image rejection ratio(IRR) is improved from 31 ㏈ to 59.76 ㏈ even with 1 ㏈ and 5° mismatch in gain and phase, respectively.

Optical homodyne receiver utilizing image rejection in FSK/ASK re-modulation WDM-PON

Optical frequency shift keying (FSK) homodyne detection utilizing image rejection in FSK/amplitude shift keying (ASK) re-modulation wavelength-division-multiplexed passive optical network (WDM-PON) is proposed and demonstrated. Image rejection is adopted to achieve better performance. We show the result in back-to-back and 40-km distance respectively and apparent improvement is obtained in the latter situation by using image rejection. Several factors which affect the image rejection receiver are analyzed in order to find out the optimum parameters. Result shows that the presented scheme is suitable for super long reach access network, especially for future metro access network.

Integrated Quadrature Couplers and Their Application in Image-Reject Receivers

Several fully-integrated multi-stage lumped-element quadrature hybrids that enhance bandwidth, amplitude and phase accuracies, and robustness are presented, and a fully-integrated double-quadrature heterodyne receiver front-end that uses two-stage Lange/Lange couplers is described. The Lange/Lange cascade exploits the inherent wide bandwidth characteristic of the Lange hybrid and enables a robust design using a relatively low transformer coupling coefficient. The measured image-rejection ratio is > 55 dB over a 200 MHz bandwidth centered around 5.25 GHz without any tuning, trimming, or calibration; the front-end features 23.5 dB gain, -79 dBm sensitivity, 5.6 dB SSB NF,-7 dBm IIP3, -18 dB S11 and a 1 mm times 2 mm die area in 0.18 mum CMOS.

Shielded Passive Devices for Silicon-Based Monolithic Microwave and Millimeter-Wave Integrated Circuits

This paper introduces floating shields for on-chip transmission lines, inductors, and transformers implemented in production silicon CMOS or BiCMOS technologies. The shield minimizes losses without requiring an explicit on-chip ground connection. Experimental measurements demonstrate Q-factor ranging from 25 to 35 between 15 and 40 GHz for shielded coplanar waveguide fabricated on 10 /spl Omega//spl middot/cm silicon. This is more than a factor of 2 improvement over conventional on-chip transmission lines (e.g., microstrip, CPW). A floating-shielded, differentially driven 7.4-nH inductor demonstrates a peak Q of 32, which is 35% higher than an unshielded example. Similar results are realizable for on-chip transformers. Floating-shielded bond-pads with 15% less parasitic capacitance and over 60% higher shunt equivalent resistance compared to conventional shielded bondpads are also described. Implementation of floating shields is compatible with current and projected design constraints for production deep-submicron silicon technologies without process modifications. Application examples of floating-shielded passives implemented in a 0.18-/spl mu/m SiGe-BiCMOS are presented, including a 21-26-GHz power amplifier with 23-dBm output at 20% PAE (at 22 GHz), and a 17-GHz WLAN image-reject receiver MMIC which dissipates less than 65 mW from a 2-V supply.

Phase Calibration Technique for Mismatch Optimization in Image-Reject Receivers

This paper presents phase calibration technique without using any external tone for weaver image-reject receiver. Error signal (phase mismatch information) is generated using a simple algorithm and this signal is used for mismatch elimination. Calibration system has been implemented using simulink which shows an image rejection ratio of 59.5 dB can be achieved for RF signal operating at 1.8 GHz.

A 2.5-GHz eight-phase VCO in SiGe BiCMOS technology

We present a 2.5-GHz voltage-controlled oscillator (VCO) with eight equally distributed phases derived from a 10-GHz LC VCO. Stochastic and static phase errors were obtained by spectrum analyzer measurements in conjunction with an on-chip single-sideband mixer. From the measured phase noise spectrum, we predict an absolute rms jitter contribution of 130 fs in a 2-MHz bandwidth phase-locked loop. A static phase error of less than 0.7/spl deg/ was deduced from the sideband suppression. The eight-phase VCO is tunable from 2.35 to 2.85 GHz and draws 16 mA from a 2.0-V supply. Possible applications include clock and data recovery of a 10-Gb/s signal in a fiber-optic receiver as well as high-precision image rejection receivers and I/Q direct up-converters for radio-frequency applications.

A 410-mW 1.22-GHz Downconverter in a Dual-Conversion Tuner IC for OpenCable Applications

A 1.22-GHz downconverter used in a dual-conversion tuner IC for OpenCable applications is presented. The downconverter is configured as an image-reject receiver and utilizes a trifilar transformer in conjunction with capacitively cross-coupled common-gate mixer input stages to achieve a large dynamic range with relatively low power consumption. Fabricated in a five-metal 0.35-/spl mu/m, 27-GHz f/sub T/, silicon-on-insulator BiCMOS technology and consuming 124 mA from a 3.3-V supply, it downconverts the input to an IF of 44 MHz and achieves 26-dB gain, 23-dB gain control range, 5.1-dB noise figure, 33-dBmV P/sub 1dB/, 56-dBmV IIP/sub 3/, -72-dBc composite triple beat (CTB), -60-dBc cross-modulation, and 30-dB image rejection.

Calibration of Phase and Gain Mismatches in Weaver Image-Reject Receiver

A modified image-reject Weaver architecture is presented. The design automatically calibrates for phase and gain mismatches that limit the performance of image-reject receivers. On-line or off-line calibrations are possible without using any calibrating tone. An experimental CMOS prototype RF front-end operating at 1.8 GHz achieves an image rejection ratio of 59 dB using on-line calibration. The design was fabricated in a 0.35-/spl mu/m CMOS process and dissipates 160 mW from a 3-V supply during on-line calibration, and 95 mW during normal receiving. The die area is 4 mm/sup 2/.

A 2-GHz CMOS image-reject receiver with LMS calibration

This paper describes a sign-sign least-mean squares (LMS) technique to calibrate gain and phase errors in the signal path of a Weaver image-reject receiver. The calibration occurs at startup and the results are stored digitally, allowing continuous signal reception thereafter. Fabricated in a standard digital 0.25-μm CMOS technology, the receiver achieves an image-rejection ratio of 57 dB after calibration, a noise figure of 5.2 dB, and a third-order input intercept point of -17 dBm. The circuit consumes 55 mW in calibration mode and 50 mW in normal receiver mode from a 2.5-V power supply. The prototype occupies an area of 1.23 × 1.84 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .