III-V Transistors Research Articles

Performance Assessment of CMOS circuits using III-V on Insulator MOS Transistors

In this work, with the help of extensive technology computer-aided design simulations, we report a comprehensive study of MOSFET based circuit design using ultra-thin body III-V on-insulator (OI) CMOS transistors. We demonstrate the circuit performance of III-V CMOS by combining InAs-OI n-channel and GaAs-OI junction-less p-channel transistors. The performance metrics of different circuits designed using III-V transistors are also compared with III-V/Germanium and Silicon-on-insulator (SOI) based CMOS logic. CMOS inverter circuit designed using III-V/Ge (InAs-OI/GeOI) CMOS shows 51% and 17% reduction in rise and fall time compared to SOI CMOS. The oscillation frequency of the ring oscillator designed using III-V/Ge (InAs-OI/GeOI) and III-V (InAs-OI/GaAs-OI) CMOS logic is approximately three times and two times higher than SOI based design. The unity-gain bandwidth of the inverting amplifier using III-V/Ge (InAs-OI/GeOI) and III-V (InAs-OI/GaAs-OI) architecture is 22 times and 9.5 times higher compared to SOI CMOS based circuit. Static noise margin (SNM) of conventional six-transistor (6-T) SRAM cell is also analyzed during hold operation. Due to the poor electrostatic integrity of III-V transistors, degradation in SNM is observed compared to its SOI counterparts. The cascode low noise amplifier (LNA) circuit designed using InAs-OI transistor shows the higher gain and low noise figure at the same operating frequency compared to the SOI transistor-based LNA.

Highly Stable Self-Aligned Ni-InGaAs and Non-Self-Aligned Mo Contact for Monolithic 3-D Integration of InGaAs MOSFETs

Self-heating has emerged as an important performance/reliability challenge for modern MOSFETs. The challenge is further acerbated for III-V transistors, especially when integrated monolithically in a 3-D platform for applications in ultrafast logic, imagers, etc. A key challenge is the difficulty of heat-dissipation through the ultra-thin channels needed to ensure electrostatic integrity of scaled transistors. In this paper, we demonstrate an innovative use of a heat-dissipating shunt of Ni-InGaAs on InGaAs(111) in the S/D extension region, as well as the use of high-conductivity Mo contact to simultaneously improve electrical and thermal stability and heat dissipation in III-V transistors, such that the peak channel temperature is reduced by as much as 25%–30%. Given the exponential temperature sensitivity of transistor reliability, heat shunts will improve transistor lifetime significantly.

(Invited) The Dynamics of Nickelidation for Self-Aligned Contacts to InGaAs Channels

The rapid development of ultrascaled III−V compound-semiconductor devices requires the detailed investigation of metal-semiconductor contacts at the nanoscale where crystal orientation, size, and structural phase play dominant roles in device performance. Here, we report comprehensive studies on the solid-state reaction between metal (Ni) and ternary III−V semiconductor (In0.53Ga0.47As) nanochannels to reveal their reaction kinetics, dynamics, formed crystal structure, and interfacial properties. We observed size-dependent reaction kinetics that are dominated by Ni surface-diffusion at small channel dimensions. We also employed in-situ heating in a transmission electron microscope (TEM) to record and analyze the atomic scale dynamics of contact reactions both in the cross-section and along the nanowire channel directions of InGaAs nanowires. Atomic models and nucleation models were introduced to depict the ledge formation and nucleation events. Deformation theory was applied to calculate the strain-induced shift in band-edge energies at the nickelide/InGaAs interface. These observations pave the way for engineered nanoscale contact to III-V transistors.

(Invited) Enabling Hetero-Integration of III-V and Ge-Based Transistors on Silicon with Ultra-Thin Buffers Formed by Interfacial Misfit Technique

III-V and Ge semiconductors have been researched as alternative channel materials for future technology nodes [1]-[26]. A key challenge is the integration of p- and n-FETs having different channel materials on Si substrates. In this paper, we discuss the application of the interfacial misfit (IMF) technique to enable the heterogeneous integration of III-V and Ge-based transistors on Si substrates. IMFs are capable of relieving the large lattice strain and minimizing the formation of threading dislocations. Ge p-FETs and InAs n-FETs were co-integrated on a Si substrate using common contact formation, digital etch, and gate stack formation modules. In addition, vertically stacked GaSb nanowire p-FETs and InAs nanowire n-FETs on Si substrates were also realized with promising electrical characteristics. GaSb Grown on GaAs with IMF Technique IMF is a key technique used to enable the heterogeneous integration on Si substrate. For both integration schemes, the III-V layers were grown on the GeOI (100) substrate with a 6° offcut. After the growth of a 70 nm-thick GaAs, a ~50 nm-thick GaSb was grown using the IMF technique. An array of misfits can be observed at the GaAs/GaSb interface as shown in the HRTEM image in Fig. 1(a). These misfits relieve most of the strain in the 7.78 % lattice mismatched GaSb and GaAs system. Under optimized growth conditions, the separation between two misfits is ~5.6 nm, implying that every 14thGa atom from GaAs has a dangling bond [Fig. 1 (b)]. Thanks to confinement of the majority of the defects within a few nanometers at the GaAs/GaSb interface, subsequent layers with high quality can be grown for device fabrication. Integration of Ge P-FETs and InAs N-FETs on a Si Platform The first application of the IMF is in integrating Ge p-FETs and InAs n-FETs on a Si substrate using CMOS compatible modules (see Fig. 2). Key features include: First, a sub-120 nm-thick buffer growth technique was used to grow the high-quality channel materials; Second, a common digital etch was employed to precisely control the etch rates of n+ -InAs and Ge, enabling the formation of UTB structures; Third, Ge p-FETs and InAs n-FETs share the same process modules to form the gate stacks and raised S/D structure. Both InAs n-FETs and Ge p-FETs show the highest reported ION with good control of short channel effects, among all co-integrated III-V n-FETs and Si1-x Ge x p-FETs on Si. Integration of GaSb P-FETs and InAs N-FETs based on Vertically-Stacked Nanowires on a Si Platform Using III-V as channel materials for both p- and n-FETs is another option for future low power and high performance logic applications. Here, we discuss the demonstration of monolithic integration of III-V on a Si platform with vertically stacked III-V nanowire CMOS (Fig. 3). The InAs n-FETs and GaSb p-FETs were integrated on a common Si platform with an extremely-thin buffer layer. Decent electrical characteristics were achieved for both InAs n-FETs with a L CH of 20 nm and GaSb p-FETs with a L CHof 500 nm.

(Invited) Enabling Hetero-Integration of III-V and Ge-Based Transistors on Silicon with Ultra-Thin Buffers Formed by Interfacial Misfit Technique

In this paper, we discuss the application of the interfacial misfit (IMF) technique to enable the heterogeneous integration of III-V and Ge-based transistors on Si substrates. Ge pFETs and InAs nFETs were co-integrated on a Si substrate using common contact formation, digital etch, and gate stack formation modules. In addition, vertically stacked nanowire (NW) GaSb pFETs and InAs nFETs on Si substrates were also realized.

Electrical properties of the HfO2–Al2O3 nanolaminates with homogeneous and graded compositions on InP

For possible application to a gate dielectric in high-performance III-V transistors, nanolaminated HfO2–Al2O3 films with artificial compositional profiles were deposited on n-type InP substrates using atomic layer deposition. The films were vertically graded (HfO2 and Al2O3 at the surface and interface regions, respectively) and had a homogeneous composition. To compare their electrical properties, a similar physical thickness and capacitance-equivalent thickness (CET) were maintained, and the graded structure showed an increase in the Al2O3 content near the high-k and InP interface region without an increase in CET, which suppresses the In incorporation at the near-interface region and reduces the density of the interface trap. However, doing so results in a degradation of the leakage current characteristics under voltage stressing when compared to homogeneously-nanolaminated films.

(Invited) Technology Options to Reduce Contact Resistance in Nanoscale III-V MOSFETs

III-V semiconductors have emerged as a leading candidate to replace Si as channel material in future low power logic applications. To realize the full performance benefits of III-V channels, it is crucial that external parasitic resistance (REXT) be minimized. Among the different components of REXT, contact resistance (RC) between metal and source/drain (S/D) junctions has become a critical area of focus to lower REXT. Historically, multi-layered Au-based metal contacts (e.g. Au/Ge/III-V) were used in III-V processing. However, the renewed interest in III-V semiconductors for CMOS has attracted an increasing interest by many to develop Au-free contacts to III-V with low RC. In addition, a “silicide-like” metal contact process for III-V was recently developed by reacting Ni with InGaAs to form Ni-InGaAs. This is significant as it is a self-aligned process and it offers the option of using a common S/D contact metal in a hetero-integrated device flow (e.g. Si/Ge/III-V). In this paper, we will review these technology options for RC reduction and present some of our recent results on contact/junction engineering to lower RC in III-V transistors.

InP-Si BiCMOS Heterointegration Using a Substrate Transfer Process

Broadband transmitters for radio links in the millimeter band are key building blocks for future wireless communication systems. Such components can be realized by means of an InP-on-BiCMOS technology. This allows the combination of the high performance of III-V transistors with the advantages of BiCMOS circuits. Critical performance trade-offs can be avoided in comparison to the pure III-V or BiCMOS versions. The passive elements and the interconnections between InP and BiCMOS were fabricated in a first run. The results are shown in the present work. This run showed the feasibility of the wafer bond process for the hetero-integration of InP and BiCMOS. An aluminum back-end was built on the silicon wafer with silicon dioxide as interlayer dielectric. A gold metallization in benzocyclobutene (BCB) as insulating dielectric represented the environment for the InP hetero-junction bipolar transistors. Thin film micro strip lines and specially designed interconnections between the two metallization systems were characterized in dependence on frequencies up to 100 GHz.

(Invited) Integration of High-κ Dielectrics on Epitaxial (100), (110) and (111) Germanium for Multifunctional Devices

With continued scaling of Si CMOS technology, new channel materials and device architectures are needed to address power consumption and constrained high-speed operation. With the demonstration of n-channel III-V transistors, the development of equivalent p-channel transistor is mandatory to realize energyefficient CMOS logic. The bulk transport properties of Ge make it an ideal candidate for p-channel transistor. The ultra-high hole mobility Ge can be realized through a III-V/Ge/III-V transistor configuration with different surface orientations would enable much faster switching, thus addressing dynamic power consumption, while the superior high- κ gate dielectric and larger bandgap barrier would help minimize OFF-state leakage. This paper discusses the i) in-situ growth of III-V/Ge/III-V heterostructure, ii) tailor-made surface orientations of Ge enable to achieve both high-hole and high-electron mobilities, and iii) band offsets of high- κ dielectrics on crystallographic oriented epitaxial (100)Ge, (110)Ge, and (111)Ge layers using solid state molecular beam epitaxy.

InP-Si BiCMOS Heterointegration Using a Substrate Transfer Process

Broadband transmitters for radio links in the mm-wave range are key building blocks for future wireless communication systems. In this work such components are to be realized by means of an InP-on-BiCMOS technology. This allows the combination of the favorable power performance of III-V transistors with the advantages of BiCMOS circuits such as complexity and integration density.This helps to avoid critical performance trade-offs compared to the pure III-V or BiCMOS versions. The heterointegration technology allows the integration of sub-mm-wave front-ends together with control logics and other lower-frequency components on a single chip. This drastically reduces packaging efforts. The strategy is to rely on BiCMOS as far as possible and to apply III-V elements only for functions for which they show clear superiority. In a first run the passive elements and the dc- and rf-interconnects between InP and BiCMOS were tested. This test showed the feasibility of the wafer bond process for the heterointegration of InP and BiCMOS. For that purpose a five metal layer Al back-end with silicon dioxide as interlayer dielectric was built on the silicon wafer. A three layer metallization (Au) in benzocyclobutene (BCB) as insulating dielectric represented the environment for the InP-HBTs. Thin film micro strip lines and special designed interconnects between the two metallization systems were characterized in dependence of frequencies up to 100 GHz to estimate the insertion losses.

Metal/III-V effective barrier height tuning using atomic layer deposition of high-κ/high-κ bilayer interfaces

In this work, we use thin dielectrics to reduce the Al/n-GaAs effective barrier height (ΦB,eff) of metal-insulator-semiconductor (MIS) contacts. We investigate the use of atomic layer deposition of HfO2, Al2O3, TiO2, ZrO2, and bilayer high-κ dielectrics and confirm there is a shift in the Fermi level that reduces the contact resistance. In studying high-κ/high-κ interfaces, we find that despite a thicker dielectric, there is further reduction in ΦB,eff beyond that of a single dielectric, which can be explained by the formation of a high-κ/high-κ dipole. This MIS structure provides great flexibility in the design of source/drain contacts for III-V transistors.

Technology Assessment Methodology for Complementary Logic Applications Based on Energy–Delay Optimization

Historically, the off-state current <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> and the supply voltage <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vdd</i> are specified as technology targets for Si metal-oxide-semiconductor field-effect transistors (MOSFETs) at each technology node. Emerging device technologies such as III-V transistors, carbon-nanotube FETs (CNFETs), and tunneling FETs (TFETs) are often targeted to outperform Si MOSFETs at the same <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vdd</i> values. However, the conclusions from the conventional methodology are limited for advanced technology and diversified applications, when Dennard scaling is inefficient and different device structures are invented. We present a new device-technology assessment methodology based on energy-delay optimization, which takes into consideration key circuit-level information, such as logic depth, activity factors, and fanout (FO). Our methodology starts from device <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> characteristics and treat <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vdd</i> as “free variables.” Together with device and supply-voltage variations, we obtain a corresponding and different optimal set of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vdd</i> and optimal energy-delay for each emerging device. We show that today's best available III-V transistors and CNFETs can outperform the best Si FETs by 1.5-2 and 2-3.5 times in terms of energy efficiency, respectively. Projected into the 10-nm-gate-length regime, III-V-on-insulator, CNFETs, and TFETs are 1.25, 2-3, and 5-10 times better than the International Technology Roadmap for Semiconductors target, for FO1 delays of 0.3, 0.1, and 1 ns, respectively.