The semiconductor industry is currently at a pivotal juncture, with major chip fabrication facilities having exhausted FINFET technology and now transitioning to a new device architecture of gate all around (GAA). The next architecture in this progression (beyond 1nm), crucial for scaling down is Complementary Field-Effect Transistors (cFETs). In cFETs, nMOS and pMOS are stacked on top of each other, eliminating the gap and resulting in significant reduction of area and maximization of channel width and drive current.[1-3] In this work, we present our research on epitaxial growth of cFET stacks and discuss our design strategies and the key evaluation metrics in accordance with the downstream processes. We delve deeper into the bottom-up growth of cFETs using Chemical Vapor Deposition (CVD) epitaxy and explore the impact of temperature, precursor gases, and Germanium content on the quality and strain engineering of cFETs. We exploit various characterization techniques to quantify defects, strain, uniformity, and composition of the epitaxial layers comprising the cFET stacks, followed by tuning of the process parameters accordingly to achieve a high-quality, fully-strained stack. Through this study, we aim to provide valuable insights into the growth and optimization of cFET structures, thereby facilitating their integration into future transistor nodes.[1] P. Schuddincket al., 2022 IEEE Symp. on VLSI Techn. & Circuits, Digest of Technical Papers, p. 365.[2] S. Subramanian et al., 2020 IEEE Symp. on VLSI Techn. & Circuits, Digest of Technical Papers, TH3.1.[3] A. Vandooren et al., 2022 IEEE Symp. on VLSI Techn. & Circuits, Digest of Technical Papers, p. 330.
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