IEEE Electron Research Articles

Formation of ZnO Nanoparticles by Atomic Layer Deposition for the Nonvolatile Memory Thin-Film Transistor Applications

Charge-trap-type memory device employing oxide-semiconductor charge-trap layers (CTL), such as ZnO and In-Ga-Zn-O (IGZO), have been intensively investigated for nonvolatile memory TFT applications [1]. Although encouraging device characteristics could be obtained for the proposed memory TFT, they can be expected to be far improved by using nano-particle (NP) mono-layers as alternative CTLs thanks to their isolated structures. So far, various methods such as spray pyrolysis and high-temperature-assisted self-assembly have been suggested to form discrete NP mono-layers [2]. However, low controllability in areal density of NPs and high process temperature limit device performance as well as process compatibility on flexible substrate.In this work, we propose a low-temperature atomic-layer-deposition (ALD) process for the formation of ZnO NPs with an island-growth mechanism and fabricated the memory TFTs using the ZnO-NP CTLs. We also investigate the effects of ALD conditions for the ZnO NPs on the device performance of the fabricated ZnO-NP memory TFTs (NP-MTFT). The gate-stack structure of top-gate NP-MTFTs were designed as In-Sn-O (ITO) gate electrode (150 nm)/Al2O3 blocking oxide (50 nm)/ZnO NP CTL/Al2O3 tunneling layer (10 nm)/IGZO active channel layer (20 nm)/ITO source-drain electrode (100 nm). ALD cycles for the ZnO NPs were varied to 5, 20, 30, and 40 and the deposition temperature was modulated from 100 to 190oC to investigate the effects of ALD conditions on the island formation of ZnO NPs. Diethylzinc (DEZn) and H2O was used as Zn and O precursors, respectively. The size and areal density of the ZnO NPs prepared at 160oC with 20 ALD cycles were estimated to be approximately 33 nm and 3×109 cm-2, respectively. It was interesting to note the changes in arithmetic average of surface roughness (Ra) at various ALD temperatures when the ALD cycles increased from 5 to 20 cycles. The variations in Ra were summarized to be from 0.24 to 0.28 nm at 100oC, from 0.26 to 0.40 nm at 130oC, from 0.98 to 2.13 nm at 160oC, and from 0.21 to 0.22 nm at 190oC. Consequently, it was found that the island growth of ZnO NPs could not be available at 100 and 190oC. On the other hand, at 160oC, the ZnO NPs could be successfully formed with appropriate deposition rate with increasing the ALD cycles.The NP-MTFTs employing these ZnO NP CTLs exhibited typical charge-trap nonvolatile memory device behaviors. The memory window (MW) width of the fabricated NP-MTFTs monotonously increased with increasing the ALD cycles from 0.6 to 14.6 V when VGS was swept in the forward and reverse directions in the range of ±20V at a drain bias (VDS) of 0.1 V. The MW (12.2 V) of the NP-MTFT drastically was increased for the 20-cycle device compared with that for the 5-cycle device. This result suggests that the areal density of ZnO NPs could be effectively modulated by controlling the ALD cycles of DEZ between 5 and 20 cycles. The on- and off-program characteristics of the NP-MTFTs were evaluated as a function of program voltage pulse width. The read-out operations were performed at VGS of -2 V and VDS of 0.1 V. The ratios of programmed IDS of on-states to that of off-states (Ion/Ioff) were obtained as more than 3×107 and did not experienced marked degradation when the program pulse width decreased from 1 s to 1 µs. These results suggest that the proposed NP-MTFT exhibited nonvolatile memory operations with wide memory window and high-speed program time. This is the first demonstration for the NP-MTFTs using the ALD-assisted ZnO-NP CTLs. Flexible memory device will be fabricated as future works and detailed device characteristics will be discussed at the presentation. [1] S. J. Kim, W. H. Lee, C. W. Byun, C. S. Hwang, and S. M. Yoon, IEEE Electron. Dev. Lett. 36 (11) 1153, 2015.[2] Z. Liu, C. H. Lee, V. Narayanan, G. Pei, and E. C. Kan, IEEE Trans. Electron. Dev. 49 (9), 1606, 2002.

Effect of Al Doping on the Reliability of ALD HfO2

CMOS device scaling below the 22 nm technology node requires gate dielectric materials with superior properties to those of conventional high-k materials. It was found that, Al incorporation into HfO2 results in an increase in the transition temperature from amorphous to polycrystalline state (1-2). Improved thermal stability (2) and enhanced permittivity (3) by Al doping into ALD HfO2 was also reported. As a result of the improvement in film properties, improved equivalent oxide thickness (EOT) values, reduced gate leakage current, lower hysteresis and improved interface quality were also observed for Al doped HfO2 (4-6). However, intermixing of HfO2 and Al2O3 depends significantly on the stack structure, which results in variations in the stoichiometry in the film (7). The relative position of HfO2 and Al2O3 in HfO2/Al2O3bi-layer has a significant influence on positive charge formation in the dielectrics and also on the quality of the interfacial layer (IL) (8-10).In this work, we deposited and studied the reliability of 40 cycles ALD HfO2 doped with Al in the deposition process. The ALD thin film composition was measured by X-ray photoelectron spectroscopy (XPS). Thin films with Al/(Al+Hf)% composition ranging 0% to 8% were deposited and annealed at 800oC in N2 ambient. MOS capacitors were then fabricated with ALD TiN as the metal gate. The electrical measurements show that, devices with ~2% Al/(Hf+Al)% have an optimized performance with 17% lower EOT than undoped HfO2. The amount of positive charge and gate leakage current density were also evaluated for all devices.The reliability of these devices was monitored by subjecting them to a constant field stress at E= 27.5 MV/cm in the gate injection mode, where the applied voltage to the gate was modified according to the EOT to have equal field across all the dielectrics. Stress-induced trap generation in the dielectrics was observed due to bulk and interface defects. Trap formation followed a power law function with stress time. Observed stress induced flat-band voltage shift (Fig. 1) shows that devices with Al/(Hf+Al)% =2% have 36% reduction in the rate of trap generation as compared to HfO2, whereas degraded flat-band voltage shift was observed for devices with Al/(Hf+Al)% =7%. It can be inferred that an optimized Al concentration in HfO2can lead to an improvement of the device performance. In order to further understand the reliability characteristics we plan to evaluate the change in interface state density with stress and their time dependent dielectric breakdown (TDDB) characteristics. References M.-Y. Ho et al., Appl. Phys. Lett., 81, 4218 (2002). H. Y. Yu et al., Appl. Phys. Lett., 81, 3618(2002). P. K. Park et al., Appl. Phys. Lett., 89, 192905(2006). W. J. Zhu et al., IEEE Electron. Dev. Lett., 23(11), 649(2002). V. Mikhelasvili et al., Appl. Phys. Lett., 85, 5950(2004).Y.-K. Chiou et al., J. Electrochem. Soc., 154 (4) G99(2007).M. H. Cho et al., Appl. Phys. Lett., 81, 1071(2002).B. H. Lee et al., Appl. Phys. Lett., 76, 1926 (2000).L. G. Gosset et al., J. Non-Cryst. Solids, 303, 17(2002).W. Wang et al., J. Appl. Phys., 105, 064108 (2009).

Charge Trapping Characterization of LaLuO3/p-Si Interfaces at Cryogenic Temperatures

Ternary rare-earth oxide LaLuO3 shows clear experimental evidence of being one of the most perspective gate dielectrics for application in upcoming MOSFET technology [1]. On the one hand, these oxides are thermally stable in the amorphous phase and possess high permittivity, and, on the other hand, complex composition of the oxide leads to more heterogeneity and defectiveness of the dielectric – semiconductor transition layer (TL). Therefore the study of electronic processes in the transition layers LaLuO3/Si is one of the major challenges associated with further implementation of the LaLuO3in CMOS technology. In this article we present an experimental investigation of charge trapping and emission from shallow traps in the TL of the LaLuO3 /p-Si structures in the temperature range 6– 40 K, which allows us to estimate quality of the gate dielectric TL. The experimental approach adopted in this work is based on the techniques of thermally stimulated charge release (TSCR), isothermal transient emission currents (ITC), dynamic I(V) characteristics and extends on our previous reports of applying the technique to study charge trapping in TL of LaSiOx /Si, GdSiOx /Si [2], HfO2/Si [3] and SiO2/Si structures [4]. The dielectric layers in the Pt/LaLuO3/p-Si(100) MOS structures were deposited by molecular beam deposition. Evaporation of La and Lu in O2 was performed at a substrate temperature of 450°C. Nominal physical thicknesses of LaLuO3 were 6.5 nm and 20 nm. The Pt gates (area - 1×10-4 cm2 ) were prepared by e-gun evaporation through a shadow mask. The MOS stacks were annealed in forming gas at 400°C for 10 minutes (10% H2). The TSCR spectra for the Pt/LaLuO3 /p-Si structure for different charging temperatures are presented in Fig. 1. Regimes of trap’s charging are depicted on the field of Fig.1. Some peculiarities of thermally stimulated currents need to be point out. At first, the TSC peak shifts towards lower temperatures, when charging temperature decreases. At second, amplitude of the TSC peak grows steadily when accumulation charging voltage (Vch) increases (not shown here). The activation energy of the TSC process was found using the initial rise method. Activation energies for hole traps have been as much as 24.3–27.9 meV, 30.3–30.6 meV and 36–39 meV (LaLuO3 thickness - 6.5nm) and 12.3-12.4 meV, 21.1-22meV, 23.4-24.4 meV (LaLuO3 thickness - 20nm). The total concentration of hole shallow traps is as large as 6.2×1010cm-2 for LaLuO3 thickness 6.5nm and 4.1×1010cm-2 for thickness 20nm. The strong current relaxation has been found to occur after Vthswitching-off (see Fig.2). Approximating relaxation time by exponential decay function from 1/τ~ f(1/kT) dependence activation energy of relaxation processes (8.8 meV) have been determined. Formation of TSCR spectra in the LaLuO3/p-Si structures is supposed to result from the recharging of traps, localized in the transition layer. The process of recharging of the traps may be due to the tunnel – activation mechanism assisted by phonons localized on the defects in transition layer. This work was partially supported by NAS of Ukraine (the project No. 53-32-10). The authors from Tyndall National Institute acknowledge the financial support of Science Foundation Ireland through the project 09/IN.1/I2633.1. E. Durğun Őzben, J.M.J. Lopes, A. Nichau, M. Schnee, S. Lenk, A. Besmehn, K.K. Bourdelle, Q.T. Zhao, J. Schubert and S. Mantl, IEEE Electron. Dev. Lett., 32 15 (2011).2 I.P. Tyagulskii, S.I. Tyagulskii, A.N. Nazarov, V.S. Lysenko, K. Cherkaoui, P.K. Hurley, Microelectronic Engineering, 109 31 (2013).3. I.P. Tyagulskyy, I.N. Osiyuk, V.S. Lysenko, A.N. Nazarov, S. Halb, O. Buiu, Y. Lu, R. Potter, P. Chalker Microelectronics Reliability, 47 726 (2007).4. V.S. Lysenko, T.N. Sytenko, V.I. Zimenko, I.P. Tyagulskyy, O.V. Snitko, I.N. Osiyuk, A.N. Nazarov, T.E. Rudenko, Solid State Commun., 57 171 (1986).

Full band Monte Carlo simulation of dislocation effects on 250 nm AlGaN-GaN HEMT

In this work, we present a full band Monte Carlo simulation of the effects of dislocation scattering on the performance of a 0.25 μm AlGaN/GaN HEMT (high electron mobility transistor). We performed a full characterization of the device and validated the simulation results with experimental data (Lee et al. in IEEE Electron. Dev. Lett. 24:613–615, [2003]). Here we show a study of the DC device performance as a function of the density of thread dislocations.

Preview of EDSSC2008 in Hong Kong, Three-day Program in December to Feature 150 Papers and Plenary Talks by SSCS DLs T. Kawahara and I. Young

Three-Day Program in December to Feature 150 Papers and Plenary Talks by SSCS DLs T. Kawahara and I. Young The 4th IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC2008) will be a three-day program from 8-10 December, 2008 featuring 150 technical papers covering broad areas in electron devices and solid-state circuits. The event is being organized by the IEEE Electron Devices/Solid-State Circuits Hong Kong Joint Chapter, and sponsored by the Hong Kong Applied Science and Technology Institute and K. C. Wong Education Foundation.

Optimal lightpath placement on a metropolitan-area network linked with optical CDMA local nets

A flexible optical metropolitan-area network (OMAN) [J.F. Huang, Y.F. Wang, C.Y. Yeh, Optimal configuration of OCDMA-based MAN with multimedia services, in: 23rd Biennial Symposium on Communications, Queen's University, Kingston, Canada, May 29–June 2, 2006, pp. 144–148] structured with OCDMA linkage is proposed to support multimedia services with multi-rate or various qualities of service. To prioritize transmissions in OCDMA, the orthogonal variable spreading factor (OVSF) codes widely used in wireless CDMA are adopted. In addition, for feasible multiplexing, unipolar OCDMA modulation [L. Nguyen, B. Aazhang, J.F. Young, All-optical CDMA with bipolar codes, IEEE Electron. Lett. 31 (6) (1995) 469–470] is used to generate the code selector of multi-rate OMAN, and a flexible fiber-grating-based system is used for the equipment on OCDMA–OVSF code. These enable an OMAN to assign suitable OVSF codes when creating different-rate lightpaths. How to optimally configure a multi-rate OMAN is a challenge because of displaced lightpaths. In this paper, a genetically modified genetic algorithm (GMGA) [L.R. Chen, Flexible fiber Bragg grating encoder/decoder for hybrid wavelength-time optical CDMA, IEEE Photon. Technol. Lett. 13 (11) (2001) 1233–1235] is used to preplan lightpaths in order to optimally configure an OMAN. To evaluate the performance of the GMGA, we compared it with different preplanning optimization algorithms. Simulation results revealed that the GMGA very efficiently solved the problem.

Internetworking and Resource Management in Satellite Systems - A series of articles in the IEEE Aerospace and Electronics Systems Magazine

Internetworking and Resource Management in Satellite Systems - A series of articles in the IEEE Aerospace and Electronics Systems Magazine

Hydrogenation∕deuteration of the Si–SiO2 interface: Atomic-scale mechanisms and limitations

The mechanisms responsible for exchange of hydrogen with deuterium at the Si–SiO2 interfaces are analyzed through first-principles calculations. The associated reaction barrier is found to be 1.94 eV, in agreement with experiments of Cheng et al. [IEEE Electron. Device Lett. 22, 203 (2001); Cheng et al.J. Appl. Phys. 90, 6536 (2001)] that studied the kinetics of the phenomenon through electrical measurements. The substitution of hydrogen by deuterium can be limited by another possible process, the breakup of the D2 molecule to a pair of Si–D bonds, which has a similar barrier.

Charging and discharging properties of electron traps created by hot-carrier injections in gate oxide of n-channel metal oxide semiconductor field effect transistor

The charging and discharging properties of electron traps created by hot-carrier injections in the thin gate oxide of n-channel metal oxide semiconductor transistors are analyzed by means of the effects that charge state transitions induce on the low-level gate current (lower than 1 pA) of the transistor. This current is measured by a very senstive floating-gate technique [F.H. Gaensslen and J.M. Aitken, IEEE Electron. Device Lett. EDL-1, 231 (1980)]. Two traps with electron capture cross sections of the order of 10−14 and 10−15 cm2 are analyzed which are linked with optical and field-dependent measurements of electron emission properties. Thermal and optical ionization energies of these defects are determined at ≊1.7±0.2 and ≊3.0±0.5 eV, respectively. Comparison with theory suggests that Si dangling bonds or oxygen vacancy in the oxide should be the defects created by hot-carrier injections.

Experimental realization of a resonant tunneling transistor

We report experimental realization of a three-terminal negative differential resistance (NDR) device. As proposed by A. R. Bonnefoi, T. C. McGill, and R. D. Burnham [IEEE Electron. Dev. Lett. EDL-6, 636 (1985)], the structure consists of a GaAs-AlxGa1−xAs double-barrier tunneling heterostructure, the current through which is controlled by an integrated vertical field-effect transistor. We present results for two samples grown by metalorganic chemical vapor deposition. Both samples exhibit NDR in their source-drain current-voltage characteristics at 77 K, with peak-to-valley current ratios ranging between 3 and 5.3. One sample exhibits NDR at room temperature. The position and peak-to-valley current ratio of the NDR can be modulated by gate voltage. Due to asymmetry in the doping levels of the two GaAs cladding layers, resonant tunneling peaks occur at much larger voltages in reverse bias than in forward bias.

Semiconductors face the '80s: Seven leaders of the boomingest business in the U.S. prognosticate the problems supergrowth could lead to

Gordon Moore, president of Intel, put it succinctly: “By 1986, the semiconductor industry could be producing something of the order of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">14</sup> functions per year. Who will use it all?” He, and 800 other participants in a recent colloquium in California's Silicon Valley, organized by the Santa Clara Chapter of IEEE's Electron Devices Society, heard some attempts at answers from industry leaders. But Dr. Moore was not satisfied. The rate of growth is such, he told Spectrum in a follow-up interview, that if the industry stays on its present upward curve of producing functions and tries to solve its problems as it always has in the past — by lowering prices — there will come a time in the 1980s when it could face disruption and a significant drop in revenues. “And that,” he says, “despite exciting new markets on the horizon, in an otherwise blossoming economy, could be a disaster.”

Maintenance of electronic equipment : L. Tweeddale, IEEE Electronics & Power, p. 262 (August 1965)

Maintenance of electronic equipment : L. Tweeddale, IEEE Electronics & Power, p. 262 (August 1965)