Idle Cycles Research Articles

Dynamic MIPS Rate Stabilization for Complex Processors

Modern microprocessor cores reach their high performance levels with the help of high clock rates, parallel and speculative execution of a large number of instructions, and vast cache hierarchies. Modern cores also have adaptive features to regulate power and temperature and avoid thermal emergencies. All of these features contribute to highly unpredictable execution times. In this article, we demonstrate that the execution time of in-order (IO), out-of-order (OoO), and OoO simultaneous multithreaded processors can be stable and predictable by stabilizing their mega instructions executed per second (MIPS) rate via a proportional, integral, and differential (PID) gain feedback controller and dynamic voltage and frequency scaling (DVFS). Processor cores in idle cycles are continuously consuming power, which is highly undesirable in systems, especially in real-time systems. In addition to meeting deadlines in real-time systems, our MIPS rate stabilization framework can be applied on top of it to reduce power and energy by avoiding idle cycles. If processors are equipped with MIPS rate stabilization, the execution time can be predicted. Because the MIPS rate remains steady, a stabilized processor meets deadlines on time in real-time systems or in systems with quality-of-service execution latency requirements at the lowest possible frequency. To demonstrate and evaluate this capability, we have selected a subset of the MiBench benchmarks with the widest execution rate variations. We stabilize their MIPS rate on a 1GHz Pentium III--like OoO single-thread microarchitecture, a 1.32GHz StrongARM-like IO microarchitecture, and the 1GHz OoO processor augmented with two-way and four-way simultaneous multithreading. Both IO and OoO cores can take advantage of the stabilization framework, but the energy per instruction of the stabilized OoO core is less because it runs at a lower frequency to meet the same deadlines. The MIPS rate stabilization of complex processors using a PID feedback control loop is a general technique applicable to environments in which lower power or energy coupled with steady, predictable performance are desirable, although we target more specifically real-time systems in this article.

Low-Cost Concurrent Error Detection for GCM and CCM

In many applications, encryption alone does not provide enough security. To enhance security, dedicated authenticated encryption (AE) mode are invented. Galios Counter Mode (GCM) and Counter with CBC-MAC mode (CCM) are the AE modes recommended by the National Institute of Standards and Technology. To support high data rates, AE modes are usually implemented in hardware. However, natural faults reduce its reliability and may undermine both its encryption and authentication capability. We present a low-cost concurrent error detection (CED) scheme for 7 AE architectures. The proposed technique explores idle cycles of the AE mode architectures. Experimental results shows that the performance overhead can be lower than 100 % for all architectures depending on the workload. FPGA implementation results show that the hardware overhead in the 0.1–23.3 % range and the power overhead is in the 0.2–23.2 % range. ASIC implementation results show that the hardware overhead in the 0.1–22.8 % range and the power overhead is in the 0.3–12.6 % range. The underlying block cipher and hash module need not have CED built in. Thus, it allows system designers to integrate block cipher and hash function intellectual property from different vendors.

DisCoP: A P2P Framework for Managing and Searching Computing Markets

Peer-to-Peer (P2P) computing, the harnessing of idle CPU cycles through the Internet, offers new research challenges in the domain of distributed computing. This paper proposes an efficient, dynamic and scalable overlay orientated towards P2P computing, called DisCoP. Our proposal gathers the peers into markets according to their computational resources. Each market is arranged in an N-ari Tree and these trees are linked by a Bruijn graph. The tree topology allows efficient searching of available resources in a specific market, while the Bruijn provides good scalability. A Hilbert function is used to arrange markets in one ordered and mono-dimensional space. This way, the proposed architecture exploits the Bruijn and the N-ari tree topologies together with the Hilbert function to classify the computing markets. Searching efficiently for computational resources in P2P systems is a challenge and in turn, an essential requirement for the platform to provide. This article also proposes different search algorithms, each adapted to the DisCoP overlay and optimized to locate computing resources in different ways: exact, range, multi-attribute and approximate searches. A large number of experiments demonstrate the correct behavior of our proposals. The comparison of the obtained results obtained compared to other approaches in the literature reveals their competitiveness in terms of efficiency, latency and hit rates.

HEVC를 위한 저면적 고성능 다중 모드 1D 변환 블록 설계

본 논문에서는 연산 시간이 긴 곱셈기 패스를 낮은 주파수에서 동작하는 저면적의 HEVC(High Efficiency Video Coding)용 다중 모드 일차원 변환 블록을 구현하는 효율적인 방법을 제시하였다. 제시한 방법은 전체 면적을 줄이기 위하여 일반적인 변수와 변수를 입력으로 받는 곱셈기 대신 행렬의 계수 특성을 이용한 상수와 변수를 입력으로 받는 상수 곱셈기를 사용하였다. 상수 곱셈기 사용으로 인하여 전체적인 처리량을 증가시켰으며 늘어난 처리량으로 인해 남는 동작 사이클을 이용하여 연산시간이 많이 걸리는 곱셈기 부분에 멀티 사이클 패스를 구성하여 곱셈기의 동작 주파수를 낮게 하면서 전체 연산량은 유지시켰다. TSMC 0.18um CMOS 공정 라이브러리를 이용하여 실제 하드웨어를 구현한 결과 4k(<TEX>$3840{\times}2160$</TEX>) 영상을 기준으로 최소 동작 주파수는 186MHz이고 최대 동작 주파수는 300MHz이다. This paper suggest an effective idea to implement an low area multi-mode one dimension transform block of HEVC(High Efficiency Video Coding). The time consuming multiplier path is designed to operate on low frequency. Normal multipliers dealing with variable operands are replaced with smaller constant multipliers which do the product with constant coefficient and variable only using shifters and adders. This scheme increases total multiplier counts but entire areas are reduced owing to smaller area of constant multiplier. Idle cycles caused by doubled multipliers enable to use multi-cycle paths on the cycle eating multiplier data path. Operating frequency is lowered by multi-cycle path but total throughput is maintained. This structure is implemented with TSMC 0.18 CMOS process library, and operated on 186MHz frequency to process a 4k(<TEX>$3840{\times}2160$</TEX>) image. Max operating frequency is 300MHz.

Asynchronous Data Sampling Within Clock-Gated Double Edge-Triggered Flip-Flops

For synchronous designs, a large portion of the total power consumption of the integrated circuit (IC) is due to the storage elements and the clock distribution. Energy efficiency from the clock elements plays a critical role in low-power circuit design. One technique for efficiency is the use of double edge-triggered flip-flops (DETFFs), since they can maintain the same throughput as single edge-triggered flip-flops (SETFFs) while only using half of the clock frequency. Clock gating is another well-accepted technique to reduce the dynamic power of idle modules or idle cycles. However, incorporating clock gating with DETFFs to further reduce dynamic power consumption introduces an asynchronous data sampling (i.e., a change in output between clock edges) that was not addressed in previous research. This asynchronous data sampling is explored in detail in this paper by analyzing the mechanisms of several different clock-gated DETFFs. Three special clock-gating strategies are evaluated to mitigate this issue in DETFFs. Each of these three solutions has limitations, and the respective tradeoffs are discussed.

Idle cycles

column Share on Idle cycles Author: Glyn Anderson View Profile Authors Info & Claims ACM SIGSOFT Software Engineering NotesVolume 38Issue 4July 2013 pp 6–9https://doi.org/10.1145/2492248.2492284Published:12 July 2013Publication History 0citation74DownloadsMetricsTotal Citations0Total Downloads74Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

SLA Constrained Adaptive Scheduling of Parallel Jobs in a Computational Desktop Grid

Desktop grids are usually equipped with hundreds or thousands of desktops which use the idle cycles of desktop PCs of small enterprises and institutions. From conventional multi -site cluster grids, desktop grids vary markedly in terms of their dynamic nature. In terms of their dynamic nature such grids vary markedly from conventional grids] .This causes the need of new scheduling algorithms ,tailor-made for such systems .Such desktop grids become worthwhile research issue since the nature of these grids attract highly parallel algorithms ,designing efficient scheduling algorithms of parallel jobs on desktop grids .A SLA based adaptive scheduling framework (ASF) for desktop grids has been presented in this paper ,where based on a resource selection algorithm after SLA verification that set by the users tasks are assigned to different available grid resources .Based on a given set of parameter and previous execution log in an adaptive(flexible) manner the resource selection algorithm ,which works in an online mode, selects resources .Whether the user submitted jobs can be executed within the deadline and other constraints specified in the SLA or not the execution log decides .Choosing the most relevant computational parameter depending upon the tasks that are assigned to grid resources is also decided by it during task execution. Later, if performance of any task degrades during the task execution, then adaptive algorithm assists the scheduling policy to adapt the system to achieve the high throughput by re-scheduling to either the server node or to the best available local node at present. Unpredictable execution conditions commonly encountered on desktop grids which can violate the SLA constraints set by the user can also be handled by this method. In this paper, for setting up desktop grid test bed GridGain 2.0 has been used and the performance of the aforesaid SLA based adaptive scheduling framework has been presented.

Catnap

Multiple networks have been used in several processor implementations to scale bandwidth and ensure protocol-level deadlock freedom for different message classes. In this paper, we observe that a multiple-network design is also attractive from a power perspective and can be leveraged to achieve energy proportionality by effective power gating. Unlike a single-network design, a multiple-network design is more amenable to power gating, as its subnetworks (subnets) can be power gated without compromising the connectivity of the network. To exploit this opportunity, we propose the Catnap architecture which consists of synergistic subnet selection and power-gating policies. Catnap maximizes the number of consecutive idle cycles in a router, while avoiding performance loss due to overloading a subnet. We evaluate a 256-core processor with a concentrated mesh topology using synthetic traffic and 35 applications. We show that the average network power of a power-gating optimized multiple-network design with four subnets could be 44% lower than a bandwidth equivalent single-network design for an average performance cost of about 5%.

Power-Aware Minimum NBTI Vector Selection Using a Linear Programming Approach

Transistor aging is a major reliability concern for nanoscale CMOS technology that can significantly reduce the operation lifetime of very large-scale integration chips. Negative bias temperature instability (NBTI) is a major contributor to transistor aging that affects pMOS transistors. On the other hand, leakage power is becoming a dominant factor of the total power with successive technology scaling. Since the input combinations applied to a logic core have a significant impact on both NBTI and leakage power, input vector control can be used to optimize both phenomena during idle cycles. In this paper, we present an efficient input vector selection technique based on linear programming for cooptimizing the NBTI-induced delay degradation and leakage power consumption during standby mode. Since the NBTI-induced delay degradation and leakage power are not affected by the input vector in the same direction, we provide a pareto curve based on both phenomena. A suitable point from such a pareto curve is chosen based on circuit conditions and requirements during runtime.

Scheduling in an unstructured peer‐to‐peer‐based high performance computing system

PurposePeer‐to‐peer (P2P) communities have the capability to construct a powerful virtual supercomputer by assembling idle internet cycles. The purpose of this paper is to present the scheduling issues in an unstructured P2P‐based high performance computing (HPC) system to achieve high performance for applications.Design/methodology/approachA new application model is proposed for the system, where applications are parallelized in the program level. To address high performance for these applications, the system resources are controlled in a semi‐centralized 3‐layer network, where volunteers form many autonomous unstructured P2P domains. Furthermore, based on such a resource management policy, a job scheduling strategy is adopted, which is collaborated by global and domain scheduling. The global scheduling is responsible for the balance among domains, while the domain scheduling resolve workpiles' execution in a domain.FindingsTheoretical analysis and a benchmark experiment show that the scheduling provides scalable and enormous computing capability in the P2P‐based HPC system.Originality/valueThe paper shows that scheduling helps P2HP (an unstructured P2P‐based HPC system) provide scalable and enormous computing capability for HPC applications.

CycloidGrid: A proximity-aware P2P-based resource discovery architecture in volunteer computing systems

Volunteer computing which benefits from idle cycles of volunteer resources over the Internet can integrate the power of hundreds to thousands of resources to achieve high computing power. In such an environment the resources are heterogeneous in terms of CPU speed, RAM, disk capacity, and network bandwidth. So finding a suitable resource to run a particular job becomes difficult. Resource discovery architecture is a key factor for overall performance of peer-to-peer based volunteer computing systems. The main contribution of this paper is to develop a proximity-aware resource discovery architecture for peer-to-peer based volunteer computing systems. The proposed resource discovery algorithm consists of two stages. In the first stage, it selects resources based on the requested quality of service and current load of peers. In the second stage, a resource with higher priority to communication delay is selected among the discovered resources. Communication delay between two peers is computed by a network model based on queuing theory, taking into account the background traffic of the Internet. Simulation results show that the proposed resource discovery algorithm improves the response time of user’s requests by a factor of 4.04 under a moderate load.

Low-leakage soft error tolerant port-less configuration memory cells for FPGAs

As technology scales the area constraint is becoming less restrictive, but soft error rate and leakage current are drastically increased with technology down scaling. Therefore, in nano-scaled CMOS technology, the reduction of soft error rate and leakage current is the most important challenge in designing field programmable gate arrays (FPGA). To overcome these difficulties, based on the observations that most configuration bit-streams of FPGA are zeros across different designs and that configuration memory cells are not directly involved with signal propagation delays in FPGA, this paper presents a new family of configuration memory cells for FPGAs in nano-scaled CMOS technology. When zeros are stored in the cells, the injected glitch due to particle strike is removed from the stroked node by pull-up or pull-down network of the cells. Thus, our proposed cells are completely hardened and cannot flip from particle strikes at the sensitive cell nodes when zeros are stored in the cells. Furthermore, in the proposed cells, when zeros are stored, the sub-threshold leakage current components are reduced by using stacks of transistors in series. These new cells are port-less and the storage nodes of cells are manipulated through the transistors which apply the supply voltages to the cell. Simulation results show that the proposed cells are working correctly during their configuration and idle cycles and that our cells have a lower soft error rate and leakage current in 22-nm, as well as 65-nm technologies.

Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications

As transistor dimensions are reduced due to technological advances, the area constraint is becoming less restrictive, but soft error rate, leakage current, and process variation are drastically increased. Therefore, in nano-scaled CMOS technology, soft error rate, leakage current and process variation are the most important issues in designing embedded cache memory. To overcome these challenges, and based on the observation that cache-resident memory values of ordinary programs exhibit a strong bias towards zero, this paper deals with new low leakage, hardened, and read-static-noise-margin-free SRAM memory cells for nano-scaled CMOS technology. These cells are completely hardened and cannot flip from particle strikes at the sensitive cell nodes. Furthermore, these new SRAM cells have free read-static-noise-margin, such that transistor mismatching, due to process variation, cannot destroy stored-data of the cells during read operation. The new cells retain their data with leakage currents and positive feedback without a refresh cycle. The basic version of new cells consists of one write port with differential write-bit-lines and one read port with differential read-bit-lines, and the improved-leakage version of new cells consists of one write port with differential write-bit-lines and one read port with a single read-bit-line. Simulation results show that the proposed cells in this work correctly operate during their read, write, and idle cycles even while considering the process variation in 22-nm technology. In the worst case, our cells have 40% lower average leakage current in comparison with conventional 6T SRAM cell without any performance degradation. Also, our cells are hardened. Thus, they have zero soft error rate.

An Adaptive Combination Query Tree Protocol for Tag Identification in RFID Systems

A reader must be able to identify tags as quickly as possible, so tag anti-collision is a significant issue for the RFID system. In this paper, we propose a novel tag anti-collision protocol (ACQT), which is suitable for a large mobile tags environment. Based on a 3-ary tree, it has the optimal capacity to identify for tree-based protocols. Using a combination query tree, it can solve the problem of not being able to generate a 3-ary tree when the length of a tag's ID is not a multiple of 3. The joining and leaving strategies can efficiently be applied for tag mobility. The simulation results show that the protocol we present can achieve better performance than previous protocols by decreasing identification delay, collision cycles and idle cycles.

Compiler-assisted energy optimization for clustered VLIW processors

Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving the clock speed, reducing the energy consumption of the logic, and making the design simpler, it introduces extra overheads by way of inter-cluster communication. This communication happens over long global wires having high load capacitance which leads to delay in execution and significantly high energy consumption. Inter-cluster communication also introduces many short idle cycles, thereby significantly increasing the overall leakage energy consumption in the functional units. The trend towards miniaturization of devices (and associated reduction in threshold voltage) makes energy consumption in interconnects and functional units even worse, and limits the usability of clustered architectures in smaller technologies. However, technological advancements now permit the design of interconnects and functional units with varying performance and power modes. In this paper, we propose scheduling algorithms that aggregate the scheduling slack of instructions and communication slack of data values to exploit the low-power modes of functional units and interconnects. Finally, we present a synergistic combination of these algorithms that simultaneously saves energy in functional units and interconnects to improves the usability of clustered architectures by achieving better overall energy–performance trade-offs. Even with conservative estimates of the contribution of the functional units and interconnects to the overall processor energy consumption, the proposed combined scheme obtains on average 8% and 10% improvement in overall energy–delay product with 3.5% and 2% performance degradation for a 2-clustered and a 4-clustered machine, respectively. We present a detailed experimental evaluation of the proposed schemes. Our test bed uses the Trimaran compiler infrastructure.

New configuration memory cells for FPGA in nano-scaled CMOS technology

In nano-scaled CMOS technology, the reduction of soft error rate and leakage current are the most important challenges in designing Field Programmable Gate Arrays (FPGA). To overcome these challenges, based on the observations that most configuration bit-streams of FPGA are zeros across different designs and that configuration memory cells are not directly involved with signal propagation delays in FPGA, this paper presents three new low-leakage and hardened configuration memory cells for nano-scaled CMOS technology. These cells are completely hardened when zeros are stored in the cells and cannot flip from particle strikes at the sensitive cell nodes. These cells retain their data with leakage currents and positive feedback without a refresh cycle. Simulation results show that the proposed cells are working correctly during their configuration and idle cycles and that our cells have a lower soft error rate and leakage current in 22-nm as well as in 65-nm technologies.

Pipeline processing in low-density parity-check codes hardware decoder

Pipeline processing in low-density parity-check codes hardware decoderLow-Density Parity-Check (LDPC) codes are one of the best known error correcting coding methods. This article concerns the hardware iterative decoder for a subclass of LDPC codes that are implementation oriented, known also as Architecture Aware LDPC. The decoder has been implemented in a form of synthesizable VHDL description. To achieve high clock frequency of the decoder hardware implementation - and in consequence high data-throughput, a large number of pipeline registers has been used in the processing chain. However, the registers increase the processing path delay, since the number of clock cycles required for data propagating is increased. Thus in general the idle cycles must be introduced between decoding subiterations. In this paper we study the conditions for necessity of idle cycles and provide a method for calculation the exact number of required idle cycles on the basis of parity check matrix of the code. Then we propose a parity check matrix optimization method to minimize the total number of required idle cycles and hence, maximize the decoder throughput. The proposed matrix optimization by sorting rows and columns does not change the code properties. Results, presented in the paper, show that the decoder throughput can be significantly increased with the proposed optimization method.

High-Efficiency Processing Schedule for Parallel Turbo Decoders Using QPP Interleaver

This paper presents a high-efficiency parallel architecture for a turbo decoder using a quadratic permutation polynomial (QPP) interleaver. Conventionally, two half-iterations for different component codewords alternate during the decoding flow. Due to the initialization calculation and pipeline delays in every half-iteration, the functional units in turbo decoders will be idle for several cycles. This inactive period will degrade throughput, especially for small blocks or high parallelism. To resolve this issue, we impose several constraints on the QPP interleaver and rearrange the processing schedule; then the following half-iteration can be executed before the completion of the current half-iteration. Thus, it can eliminate the idle cycles and increase the efficiency of functional units. Based on this modified schedule with 100% efficiency, a parallel turbo decoder which contains 32 radix-24 SISO decoders is implemented with 90 nm technology to achieve 1.4 Gb/s while decoding size-4096 blocks for 8 iterations.

Smart Bus Arbiter for QoS control in H.264 decoders

H.264 decoders usually have pipeline architecture by a macroblock or a 4 × 4 sub-block. The period of the pipeline is usually fixed to guarantee the operation in the worst case which results in many idle cycles and higher data bandwidth. Adaptive pipeline architecture for H.264 decoders has been proposed for efficient decoding and lower the requirement of the bandwidth for the memory bus. However, it requires a controller for the adaptive priority control to utilize the advantage. We propose a smart bus arbiter that replaces the controller. It is introduced to adjust the priority adaptively the QoS (Quality of Service) control of the decoding process. The smart arbiter can be integrated the arbiter of bus systems and it works when certain conditions are met so that it does not affect the original functions of the arbiter. An H.264 decoder using the proposed architecture is designed and implemented to verify the operation using an FPGA.

Dynamic scheduling for heterogeneous Desktop Grids

Desktop Grids have emerged as an important methodology to harness the idle cycles of millions of participant desktop PCs over the Internet. However, to effectively utilize the resources of a Desktop Grid, it is necessary to use scheduling policies suitable for such systems. In this paper, we analyze the performance of a policy which is shown to perform well in highly heterogeneous Desktop Grids. The policy utilizes the solution to a linear programming (LP) problem which maximizes system capacity. We suggest robust modifications to address several limitations of the policy.